projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c6337e2 KH |
1 | /* |
| 2 | * Header for code common to all DaVinci machines. | |
| 3 | * | |
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
| 5 | * | |
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | |
| 7 | * the terms of the GNU General Public License version 2. This program | |
| 8 | * is licensed "as is" without any warranty of any kind, whether express | |
| 9 | * or implied. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H | |
| 13 | #define __ARCH_ARM_MACH_DAVINCI_COMMON_H | |
| 14 | ||
| 280faffb TK |
15 | #include <linux/compiler.h> |
| 16 | #include <linux/types.h> | |
| 17 | ||
| 7c6337e2 KH |
18 | struct sys_timer; |
| 19 | ||
| 20 | extern struct sys_timer davinci_timer; | |
| 21 | ||
| d0e47fba | 22 | extern void davinci_irq_init(void); |
| 673dd36f | 23 | extern void __iomem *davinci_intc_base; |
| 0b0c4c2a | 24 | extern int davinci_intc_type; |
| d0e47fba | 25 | |
| f64691b3 | 26 | struct davinci_timer_instance { |
| 1bcd38ad | 27 | u32 base; |
| f64691b3 MG |
28 | u32 bottom_irq; |
| 29 | u32 top_irq; | |
| 3abd5acf MG |
30 | unsigned long cmp_off; |
| 31 | unsigned int cmp_irq; | |
| f64691b3 MG |
32 | }; |
| 33 | ||
| 34 | struct davinci_timer_info { | |
| 35 | struct davinci_timer_instance *timers; | |
| 36 | unsigned int clockevent_id; | |
| 37 | unsigned int clocksource_id; | |
| 38 | }; | |
| 39 | ||
| c12f415a CC |
40 | struct davinci_gpio_controller; |
| 41 | ||
| bcd6a1c6 CC |
42 | /* |
| 43 | * SoC info passed into common davinci modules. | |
| 44 | * | |
| 45 | * Base addresses in this structure should be physical and not virtual. | |
| 46 | * Modules that take such base addresses, should internally ioremap() them to | |
| 47 | * use. | |
| 48 | */ | |
| 79c3c0b7 MG |
49 | struct davinci_soc_info { |
| 50 | struct map_desc *io_desc; | |
| 51 | unsigned long io_desc_num; | |
| b9ab1279 MG |
52 | u32 cpu_id; |
| 53 | u32 jtag_id; | |
| 3347db83 | 54 | u32 jtag_id_reg; |
| b9ab1279 MG |
55 | struct davinci_id *ids; |
| 56 | unsigned long ids_num; | |
| 08aca087 | 57 | struct clk_lookup *cpu_clks; |
| e4c822c7 | 58 | u32 *psc_bases; |
| d81d188c | 59 | unsigned long psc_bases_num; |
| 779b0d53 | 60 | u32 pinmux_base; |
| 0e585952 MG |
61 | const struct mux_config *pinmux_pins; |
| 62 | unsigned long pinmux_pins_num; | |
| bd808947 | 63 | u32 intc_base; |
| 673dd36f MG |
64 | int intc_type; |
| 65 | u8 *intc_irq_prios; | |
| 66 | unsigned long intc_irq_num; | |
| bd808947 | 67 | u32 *intc_host_map; |
| f64691b3 | 68 | struct davinci_timer_info *timer_info; |
| 686b634a | 69 | int gpio_type; |
| b8d44293 | 70 | u32 gpio_base; |
| a994955c MG |
71 | unsigned gpio_num; |
| 72 | unsigned gpio_irq; | |
| 7a36071e | 73 | unsigned gpio_unbanked; |
| c12f415a CC |
74 | struct davinci_gpio_controller *gpio_ctlrs; |
| 75 | int gpio_ctlrs_num; | |
| 65e866a9 | 76 | struct platform_device *serial_dev; |
| 972412b6 | 77 | struct emac_platform_data *emac_pdata; |
| 0d04eb47 DB |
78 | dma_addr_t sram_dma; |
| 79 | unsigned sram_len; | |
| c78a5bc2 CC |
80 | struct platform_device *reset_device; |
| 81 | void (*reset)(struct platform_device *); | |
| 79c3c0b7 MG |
82 | }; |
| 83 | ||
| 84 | extern struct davinci_soc_info davinci_soc_info; | |
| 85 | ||
| 86 | extern void davinci_common_init(struct davinci_soc_info *soc_info); | |
| 7a9978a1 | 87 | extern void davinci_init_ide(void); |
| 79c3c0b7 | 88 | |
| 0d04eb47 DB |
89 | /* standard place to map on-chip SRAMs; they *may* support DMA */ |
| 90 | #define SRAM_VIRT 0xfffe0000 | |
| 91 | #define SRAM_SIZE SZ_128K | |
| 92 | ||
| 7c6337e2 | 93 | #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ |