Commit | Line | Data |
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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
3d9edf09 | 18 | |
a09e64fb | 19 | #include <mach/gpio.h> |
3d9edf09 VB |
20 | |
21 | #include <asm/mach/irq.h> | |
22 | ||
c12f415a CC |
23 | struct davinci_gpio_regs { |
24 | u32 dir; | |
25 | u32 out_data; | |
26 | u32 set_data; | |
27 | u32 clr_data; | |
28 | u32 in_data; | |
29 | u32 set_rising; | |
30 | u32 clr_rising; | |
31 | u32 set_falling; | |
32 | u32 clr_falling; | |
33 | u32 intstat; | |
34 | }; | |
35 | ||
ba4a984e | 36 | #define chip2controller(chip) \ |
99e9e52d | 37 | container_of(chip, struct davinci_gpio_controller, chip) |
ba4a984e | 38 | |
99e9e52d | 39 | static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
3d9edf09 | 40 | |
99e9e52d | 41 | static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) |
3d9edf09 | 42 | { |
c12f415a CC |
43 | void __iomem *ptr; |
44 | void __iomem *base = davinci_soc_info.gpio_base; | |
45 | ||
46 | if (gpio < 32 * 1) | |
47 | ptr = base + 0x10; | |
48 | else if (gpio < 32 * 2) | |
49 | ptr = base + 0x38; | |
50 | else if (gpio < 32 * 3) | |
51 | ptr = base + 0x60; | |
52 | else if (gpio < 32 * 4) | |
53 | ptr = base + 0x88; | |
54 | else if (gpio < 32 * 5) | |
55 | ptr = base + 0xb0; | |
56 | else | |
57 | ptr = NULL; | |
58 | return ptr; | |
3d9edf09 VB |
59 | } |
60 | ||
99e9e52d | 61 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
21ce873d | 62 | { |
99e9e52d | 63 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 64 | |
99e9e52d | 65 | g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); |
21ce873d KH |
66 | |
67 | return g; | |
68 | } | |
69 | ||
dc756026 | 70 | static int __init davinci_gpio_irq_setup(void); |
dce1115b DB |
71 | |
72 | /*--------------------------------------------------------------------------*/ | |
73 | ||
3d9edf09 | 74 | /* |
dce1115b DB |
75 | * board setup code *MUST* set PINMUX0 and PINMUX1 as |
76 | * needed, and enable the GPIO clock. | |
3d9edf09 | 77 | */ |
dce1115b | 78 | |
ba4a984e CC |
79 | static inline int __davinci_direction(struct gpio_chip *chip, |
80 | unsigned offset, bool out, int value) | |
3d9edf09 | 81 | { |
99e9e52d CC |
82 | struct davinci_gpio_controller *d = chip2controller(chip); |
83 | struct davinci_gpio_regs __iomem *g = d->regs; | |
b27b6d03 | 84 | unsigned long flags; |
dce1115b | 85 | u32 temp; |
ba4a984e | 86 | u32 mask = 1 << offset; |
3d9edf09 | 87 | |
b27b6d03 | 88 | spin_lock_irqsave(&d->lock, flags); |
dce1115b | 89 | temp = __raw_readl(&g->dir); |
ba4a984e CC |
90 | if (out) { |
91 | temp &= ~mask; | |
92 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); | |
93 | } else { | |
94 | temp |= mask; | |
95 | } | |
dce1115b | 96 | __raw_writel(temp, &g->dir); |
b27b6d03 | 97 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 98 | |
dce1115b DB |
99 | return 0; |
100 | } | |
3d9edf09 | 101 | |
ba4a984e CC |
102 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
103 | { | |
104 | return __davinci_direction(chip, offset, false, 0); | |
105 | } | |
106 | ||
107 | static int | |
108 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
109 | { | |
110 | return __davinci_direction(chip, offset, true, value); | |
111 | } | |
112 | ||
3d9edf09 VB |
113 | /* |
114 | * Read the pin's value (works even if it's set up as output); | |
115 | * returns zero/nonzero. | |
116 | * | |
117 | * Note that changes are synched to the GPIO clock, so reading values back | |
118 | * right after you've set them may give old values. | |
119 | */ | |
dce1115b | 120 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 121 | { |
99e9e52d CC |
122 | struct davinci_gpio_controller *d = chip2controller(chip); |
123 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 124 | |
dce1115b | 125 | return (1 << offset) & __raw_readl(&g->in_data); |
3d9edf09 | 126 | } |
3d9edf09 | 127 | |
dce1115b DB |
128 | /* |
129 | * Assuming the pin is muxed as a gpio output, set its output value. | |
130 | */ | |
131 | static void | |
132 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 133 | { |
99e9e52d CC |
134 | struct davinci_gpio_controller *d = chip2controller(chip); |
135 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 136 | |
dce1115b DB |
137 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
138 | } | |
139 | ||
140 | static int __init davinci_gpio_setup(void) | |
141 | { | |
142 | int i, base; | |
a994955c MG |
143 | unsigned ngpio; |
144 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
c12f415a | 145 | struct davinci_gpio_regs *regs; |
dce1115b | 146 | |
686b634a CC |
147 | if (soc_info->gpio_type != GPIO_TYPE_DAVINCI) |
148 | return 0; | |
149 | ||
a994955c MG |
150 | /* |
151 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
152 | * and "ngpio" is one more than the largest zero-based |
153 | * bit index that's valid. | |
154 | */ | |
a994955c MG |
155 | ngpio = soc_info->gpio_num; |
156 | if (ngpio == 0) { | |
474dad54 DB |
157 | pr_err("GPIO setup: how many GPIOs?\n"); |
158 | return -EINVAL; | |
159 | } | |
160 | ||
161 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) | |
162 | ngpio = DAVINCI_N_GPIO; | |
163 | ||
164 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { | |
dce1115b DB |
165 | chips[i].chip.label = "DaVinci"; |
166 | ||
167 | chips[i].chip.direction_input = davinci_direction_in; | |
168 | chips[i].chip.get = davinci_gpio_get; | |
169 | chips[i].chip.direction_output = davinci_direction_out; | |
170 | chips[i].chip.set = davinci_gpio_set; | |
171 | ||
172 | chips[i].chip.base = base; | |
474dad54 | 173 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
174 | if (chips[i].chip.ngpio > 32) |
175 | chips[i].chip.ngpio = 32; | |
176 | ||
b27b6d03 CC |
177 | spin_lock_init(&chips[i].lock); |
178 | ||
c12f415a CC |
179 | regs = gpio2regs(base); |
180 | chips[i].regs = regs; | |
181 | chips[i].set_data = ®s->set_data; | |
182 | chips[i].clr_data = ®s->clr_data; | |
183 | chips[i].in_data = ®s->in_data; | |
dce1115b DB |
184 | |
185 | gpiochip_add(&chips[i].chip); | |
186 | } | |
3d9edf09 | 187 | |
c12f415a CC |
188 | soc_info->gpio_ctlrs = chips; |
189 | soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); | |
190 | ||
dc756026 | 191 | davinci_gpio_irq_setup(); |
3d9edf09 VB |
192 | return 0; |
193 | } | |
dce1115b | 194 | pure_initcall(davinci_gpio_setup); |
3d9edf09 | 195 | |
dce1115b | 196 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
197 | /* |
198 | * We expect irqs will normally be set up as input pins, but they can also be | |
199 | * used as output pins ... which is convenient for testing. | |
200 | * | |
474dad54 | 201 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 202 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 203 | * |
474dad54 | 204 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
205 | * serve as EDMA event triggers. |
206 | */ | |
207 | ||
208 | static void gpio_irq_disable(unsigned irq) | |
209 | { | |
99e9e52d | 210 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e | 211 | u32 mask = (u32) get_irq_data(irq); |
3d9edf09 VB |
212 | |
213 | __raw_writel(mask, &g->clr_falling); | |
214 | __raw_writel(mask, &g->clr_rising); | |
215 | } | |
216 | ||
217 | static void gpio_irq_enable(unsigned irq) | |
218 | { | |
99e9e52d | 219 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e | 220 | u32 mask = (u32) get_irq_data(irq); |
df4aab46 | 221 | unsigned status = irq_desc[irq].status; |
3d9edf09 | 222 | |
df4aab46 DB |
223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
224 | if (!status) | |
225 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
226 | ||
227 | if (status & IRQ_TYPE_EDGE_FALLING) | |
3d9edf09 | 228 | __raw_writel(mask, &g->set_falling); |
df4aab46 | 229 | if (status & IRQ_TYPE_EDGE_RISING) |
3d9edf09 VB |
230 | __raw_writel(mask, &g->set_rising); |
231 | } | |
232 | ||
233 | static int gpio_irq_type(unsigned irq, unsigned trigger) | |
234 | { | |
99e9e52d | 235 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e | 236 | u32 mask = (u32) get_irq_data(irq); |
3d9edf09 VB |
237 | |
238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
239 | return -EINVAL; | |
240 | ||
241 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
242 | irq_desc[irq].status |= trigger; | |
243 | ||
df4aab46 DB |
244 | /* don't enable the IRQ if it's currently disabled */ |
245 | if (irq_desc[irq].depth == 0) { | |
246 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
247 | ? &g->set_falling : &g->clr_falling); | |
248 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
249 | ? &g->set_rising : &g->clr_rising); | |
250 | } | |
3d9edf09 VB |
251 | return 0; |
252 | } | |
253 | ||
254 | static struct irq_chip gpio_irqchip = { | |
255 | .name = "GPIO", | |
256 | .enable = gpio_irq_enable, | |
257 | .disable = gpio_irq_disable, | |
258 | .set_type = gpio_irq_type, | |
259 | }; | |
260 | ||
261 | static void | |
262 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
263 | { | |
99e9e52d | 264 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
3d9edf09 VB |
265 | u32 mask = 0xffff; |
266 | ||
267 | /* we only care about one bank */ | |
268 | if (irq & 1) | |
269 | mask <<= 16; | |
270 | ||
271 | /* temporarily mask (level sensitive) parent IRQ */ | |
dc756026 | 272 | desc->chip->mask(irq); |
3d9edf09 VB |
273 | desc->chip->ack(irq); |
274 | while (1) { | |
275 | u32 status; | |
3d9edf09 VB |
276 | int n; |
277 | int res; | |
278 | ||
279 | /* ack any irqs */ | |
280 | status = __raw_readl(&g->intstat) & mask; | |
281 | if (!status) | |
282 | break; | |
283 | __raw_writel(status, &g->intstat); | |
284 | if (irq & 1) | |
285 | status >>= 16; | |
286 | ||
287 | /* now demux them to the right lowlevel handler */ | |
288 | n = (int)get_irq_data(irq); | |
3d9edf09 VB |
289 | while (status) { |
290 | res = ffs(status); | |
291 | n += res; | |
d8aa0251 | 292 | generic_handle_irq(n - 1); |
3d9edf09 VB |
293 | status >>= res; |
294 | } | |
295 | } | |
296 | desc->chip->unmask(irq); | |
297 | /* now it may re-trigger */ | |
298 | } | |
299 | ||
7a36071e DB |
300 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
301 | { | |
99e9e52d | 302 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e DB |
303 | |
304 | if (d->irq_base >= 0) | |
305 | return d->irq_base + offset; | |
306 | else | |
307 | return -ENODEV; | |
308 | } | |
309 | ||
310 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
311 | { | |
312 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
313 | ||
314 | /* NOTE: we assume for now that only irqs in the first gpio_chip | |
315 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). | |
316 | */ | |
317 | if (offset < soc_info->gpio_unbanked) | |
318 | return soc_info->gpio_irq + offset; | |
319 | else | |
320 | return -ENODEV; | |
321 | } | |
322 | ||
323 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) | |
324 | { | |
99e9e52d | 325 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e DB |
326 | u32 mask = (u32) get_irq_data(irq); |
327 | ||
328 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
329 | return -EINVAL; | |
330 | ||
331 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
332 | ? &g->set_falling : &g->clr_falling); | |
333 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
334 | ? &g->set_rising : &g->clr_rising); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
3d9edf09 | 339 | /* |
474dad54 DB |
340 | * NOTE: for suspend/resume, probably best to make a platform_device with |
341 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
342 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
343 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 344 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
345 | */ |
346 | ||
347 | static int __init davinci_gpio_irq_setup(void) | |
348 | { | |
349 | unsigned gpio, irq, bank; | |
350 | struct clk *clk; | |
474dad54 | 351 | u32 binten = 0; |
a994955c MG |
352 | unsigned ngpio, bank_irq; |
353 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
99e9e52d | 354 | struct davinci_gpio_regs __iomem *g; |
a994955c MG |
355 | |
356 | ngpio = soc_info->gpio_num; | |
474dad54 | 357 | |
a994955c MG |
358 | bank_irq = soc_info->gpio_irq; |
359 | if (bank_irq == 0) { | |
474dad54 DB |
360 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); |
361 | return -EINVAL; | |
362 | } | |
3d9edf09 VB |
363 | |
364 | clk = clk_get(NULL, "gpio"); | |
365 | if (IS_ERR(clk)) { | |
366 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
367 | PTR_ERR(clk)); | |
474dad54 | 368 | return PTR_ERR(clk); |
3d9edf09 | 369 | } |
3d9edf09 VB |
370 | clk_enable(clk); |
371 | ||
7a36071e DB |
372 | /* Arrange gpio_to_irq() support, handling either direct IRQs or |
373 | * banked IRQs. Having GPIOs in the first GPIO bank use direct | |
374 | * IRQs, while the others use banked IRQs, would need some setup | |
375 | * tweaks to recognize hardware which can do that. | |
376 | */ | |
377 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
378 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
379 | chips[bank].irq_base = soc_info->gpio_unbanked | |
380 | ? -EINVAL | |
381 | : (soc_info->intc_irq_num + gpio); | |
382 | } | |
383 | ||
384 | /* | |
385 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
386 | * controller only handling trigger modes. We currently assume no | |
387 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
388 | */ | |
389 | if (soc_info->gpio_unbanked) { | |
390 | static struct irq_chip gpio_irqchip_unbanked; | |
391 | ||
392 | /* pass "bank 0" GPIO IRQs to AINTC */ | |
393 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
394 | binten = BIT(0); | |
395 | ||
396 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
397 | irq = bank_irq; | |
398 | gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); | |
399 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; | |
400 | gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; | |
401 | ||
402 | /* default trigger: both edges */ | |
99e9e52d | 403 | g = gpio2regs(0); |
7a36071e DB |
404 | __raw_writel(~0, &g->set_falling); |
405 | __raw_writel(~0, &g->set_rising); | |
406 | ||
407 | /* set the direct IRQs up to use that irqchip */ | |
408 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | |
409 | set_irq_chip(irq, &gpio_irqchip_unbanked); | |
410 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | |
21ce873d | 411 | set_irq_chip_data(irq, (__force void *) g); |
7a36071e DB |
412 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; |
413 | } | |
414 | ||
415 | goto done; | |
416 | } | |
417 | ||
418 | /* | |
419 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
420 | * then chain through our own handler. | |
421 | */ | |
474dad54 DB |
422 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
423 | gpio < ngpio; | |
424 | bank++, bank_irq++) { | |
3d9edf09 VB |
425 | unsigned i; |
426 | ||
7a36071e | 427 | /* disabled by default, enabled only as needed */ |
99e9e52d | 428 | g = gpio2regs(gpio); |
3d9edf09 VB |
429 | __raw_writel(~0, &g->clr_falling); |
430 | __raw_writel(~0, &g->clr_rising); | |
431 | ||
432 | /* set up all irqs in this bank */ | |
474dad54 | 433 | set_irq_chained_handler(bank_irq, gpio_irq_handler); |
21ce873d KH |
434 | set_irq_chip_data(bank_irq, (__force void *) g); |
435 | set_irq_data(bank_irq, (void *) irq); | |
3d9edf09 | 436 | |
474dad54 | 437 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
3d9edf09 | 438 | set_irq_chip(irq, &gpio_irqchip); |
21ce873d | 439 | set_irq_chip_data(irq, (__force void *) g); |
7a36071e | 440 | set_irq_data(irq, (void *) __gpio_mask(gpio)); |
3d9edf09 VB |
441 | set_irq_handler(irq, handle_simple_irq); |
442 | set_irq_flags(irq, IRQF_VALID); | |
443 | } | |
474dad54 DB |
444 | |
445 | binten |= BIT(bank); | |
3d9edf09 VB |
446 | } |
447 | ||
7a36071e | 448 | done: |
3d9edf09 VB |
449 | /* BINTEN -- per-bank interrupt enable. genirq would also let these |
450 | * bits be set/cleared dynamically. | |
451 | */ | |
a994955c | 452 | __raw_writel(binten, soc_info->gpio_base + 0x08); |
3d9edf09 VB |
453 | |
454 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); | |
455 | ||
456 | return 0; | |
457 | } |