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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/bitops.h> | |
22 | ||
474dad54 | 23 | #include <mach/cputype.h> |
a09e64fb RK |
24 | #include <mach/irqs.h> |
25 | #include <mach/hardware.h> | |
a994955c | 26 | #include <mach/common.h> |
a09e64fb | 27 | #include <mach/gpio.h> |
3d9edf09 VB |
28 | |
29 | #include <asm/mach/irq.h> | |
30 | ||
3d9edf09 | 31 | |
dce1115b | 32 | static DEFINE_SPINLOCK(gpio_lock); |
3d9edf09 | 33 | |
dce1115b DB |
34 | struct davinci_gpio { |
35 | struct gpio_chip chip; | |
36 | struct gpio_controller *__iomem regs; | |
37 | }; | |
3d9edf09 | 38 | |
dce1115b | 39 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
3d9edf09 | 40 | |
3d9edf09 | 41 | /* create a non-inlined version */ |
474dad54 | 42 | static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) |
3d9edf09 VB |
43 | { |
44 | return __gpio_to_controller(gpio); | |
45 | } | |
46 | ||
dc756026 | 47 | static int __init davinci_gpio_irq_setup(void); |
dce1115b DB |
48 | |
49 | /*--------------------------------------------------------------------------*/ | |
50 | ||
3d9edf09 | 51 | /* |
dce1115b DB |
52 | * board setup code *MUST* set PINMUX0 and PINMUX1 as |
53 | * needed, and enable the GPIO clock. | |
3d9edf09 | 54 | */ |
dce1115b DB |
55 | |
56 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) | |
3d9edf09 | 57 | { |
dce1115b DB |
58 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
59 | struct gpio_controller *__iomem g = d->regs; | |
60 | u32 temp; | |
3d9edf09 | 61 | |
dce1115b DB |
62 | spin_lock(&gpio_lock); |
63 | temp = __raw_readl(&g->dir); | |
64 | temp |= (1 << offset); | |
65 | __raw_writel(temp, &g->dir); | |
66 | spin_unlock(&gpio_lock); | |
3d9edf09 | 67 | |
dce1115b DB |
68 | return 0; |
69 | } | |
3d9edf09 VB |
70 | |
71 | /* | |
72 | * Read the pin's value (works even if it's set up as output); | |
73 | * returns zero/nonzero. | |
74 | * | |
75 | * Note that changes are synched to the GPIO clock, so reading values back | |
76 | * right after you've set them may give old values. | |
77 | */ | |
dce1115b | 78 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 79 | { |
dce1115b DB |
80 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
81 | struct gpio_controller *__iomem g = d->regs; | |
3d9edf09 | 82 | |
dce1115b | 83 | return (1 << offset) & __raw_readl(&g->in_data); |
3d9edf09 | 84 | } |
3d9edf09 | 85 | |
dce1115b DB |
86 | static int |
87 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 88 | { |
dce1115b DB |
89 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
90 | struct gpio_controller *__iomem g = d->regs; | |
3d9edf09 | 91 | u32 temp; |
dce1115b | 92 | u32 mask = 1 << offset; |
3d9edf09 VB |
93 | |
94 | spin_lock(&gpio_lock); | |
3d9edf09 | 95 | temp = __raw_readl(&g->dir); |
dce1115b DB |
96 | temp &= ~mask; |
97 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); | |
3d9edf09 VB |
98 | __raw_writel(temp, &g->dir); |
99 | spin_unlock(&gpio_lock); | |
100 | return 0; | |
101 | } | |
3d9edf09 | 102 | |
dce1115b DB |
103 | /* |
104 | * Assuming the pin is muxed as a gpio output, set its output value. | |
105 | */ | |
106 | static void | |
107 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 108 | { |
dce1115b DB |
109 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
110 | struct gpio_controller *__iomem g = d->regs; | |
3d9edf09 | 111 | |
dce1115b DB |
112 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
113 | } | |
114 | ||
115 | static int __init davinci_gpio_setup(void) | |
116 | { | |
117 | int i, base; | |
a994955c MG |
118 | unsigned ngpio; |
119 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
dce1115b | 120 | |
a994955c MG |
121 | /* |
122 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
123 | * and "ngpio" is one more than the largest zero-based |
124 | * bit index that's valid. | |
125 | */ | |
a994955c MG |
126 | ngpio = soc_info->gpio_num; |
127 | if (ngpio == 0) { | |
474dad54 DB |
128 | pr_err("GPIO setup: how many GPIOs?\n"); |
129 | return -EINVAL; | |
130 | } | |
131 | ||
132 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) | |
133 | ngpio = DAVINCI_N_GPIO; | |
134 | ||
135 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { | |
dce1115b DB |
136 | chips[i].chip.label = "DaVinci"; |
137 | ||
138 | chips[i].chip.direction_input = davinci_direction_in; | |
139 | chips[i].chip.get = davinci_gpio_get; | |
140 | chips[i].chip.direction_output = davinci_direction_out; | |
141 | chips[i].chip.set = davinci_gpio_set; | |
142 | ||
143 | chips[i].chip.base = base; | |
474dad54 | 144 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
145 | if (chips[i].chip.ngpio > 32) |
146 | chips[i].chip.ngpio = 32; | |
147 | ||
148 | chips[i].regs = gpio2controller(base); | |
149 | ||
150 | gpiochip_add(&chips[i].chip); | |
151 | } | |
3d9edf09 | 152 | |
dc756026 | 153 | davinci_gpio_irq_setup(); |
3d9edf09 VB |
154 | return 0; |
155 | } | |
dce1115b | 156 | pure_initcall(davinci_gpio_setup); |
3d9edf09 | 157 | |
dce1115b | 158 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
159 | /* |
160 | * We expect irqs will normally be set up as input pins, but they can also be | |
161 | * used as output pins ... which is convenient for testing. | |
162 | * | |
474dad54 DB |
163 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
164 | * to their GPIOBNK0 irq, with a bit less overhead but less flexibility | |
165 | * on triggering (e.g. no edge options). We don't try to use those. | |
3d9edf09 | 166 | * |
474dad54 | 167 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
168 | * serve as EDMA event triggers. |
169 | */ | |
170 | ||
171 | static void gpio_irq_disable(unsigned irq) | |
172 | { | |
173 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
174 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | |
175 | ||
176 | __raw_writel(mask, &g->clr_falling); | |
177 | __raw_writel(mask, &g->clr_rising); | |
178 | } | |
179 | ||
180 | static void gpio_irq_enable(unsigned irq) | |
181 | { | |
182 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
183 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | |
df4aab46 | 184 | unsigned status = irq_desc[irq].status; |
3d9edf09 | 185 | |
df4aab46 DB |
186 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
187 | if (!status) | |
188 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
189 | ||
190 | if (status & IRQ_TYPE_EDGE_FALLING) | |
3d9edf09 | 191 | __raw_writel(mask, &g->set_falling); |
df4aab46 | 192 | if (status & IRQ_TYPE_EDGE_RISING) |
3d9edf09 VB |
193 | __raw_writel(mask, &g->set_rising); |
194 | } | |
195 | ||
196 | static int gpio_irq_type(unsigned irq, unsigned trigger) | |
197 | { | |
198 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
199 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | |
200 | ||
201 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
202 | return -EINVAL; | |
203 | ||
204 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
205 | irq_desc[irq].status |= trigger; | |
206 | ||
df4aab46 DB |
207 | /* don't enable the IRQ if it's currently disabled */ |
208 | if (irq_desc[irq].depth == 0) { | |
209 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
210 | ? &g->set_falling : &g->clr_falling); | |
211 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
212 | ? &g->set_rising : &g->clr_rising); | |
213 | } | |
3d9edf09 VB |
214 | return 0; |
215 | } | |
216 | ||
217 | static struct irq_chip gpio_irqchip = { | |
218 | .name = "GPIO", | |
219 | .enable = gpio_irq_enable, | |
220 | .disable = gpio_irq_disable, | |
221 | .set_type = gpio_irq_type, | |
222 | }; | |
223 | ||
224 | static void | |
225 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
226 | { | |
227 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
228 | u32 mask = 0xffff; | |
229 | ||
230 | /* we only care about one bank */ | |
231 | if (irq & 1) | |
232 | mask <<= 16; | |
233 | ||
234 | /* temporarily mask (level sensitive) parent IRQ */ | |
dc756026 | 235 | desc->chip->mask(irq); |
3d9edf09 VB |
236 | desc->chip->ack(irq); |
237 | while (1) { | |
238 | u32 status; | |
3d9edf09 VB |
239 | int n; |
240 | int res; | |
241 | ||
242 | /* ack any irqs */ | |
243 | status = __raw_readl(&g->intstat) & mask; | |
244 | if (!status) | |
245 | break; | |
246 | __raw_writel(status, &g->intstat); | |
247 | if (irq & 1) | |
248 | status >>= 16; | |
249 | ||
250 | /* now demux them to the right lowlevel handler */ | |
251 | n = (int)get_irq_data(irq); | |
3d9edf09 VB |
252 | while (status) { |
253 | res = ffs(status); | |
254 | n += res; | |
d8aa0251 | 255 | generic_handle_irq(n - 1); |
3d9edf09 VB |
256 | status >>= res; |
257 | } | |
258 | } | |
259 | desc->chip->unmask(irq); | |
260 | /* now it may re-trigger */ | |
261 | } | |
262 | ||
263 | /* | |
474dad54 DB |
264 | * NOTE: for suspend/resume, probably best to make a platform_device with |
265 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
266 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
267 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 268 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
269 | */ |
270 | ||
271 | static int __init davinci_gpio_irq_setup(void) | |
272 | { | |
273 | unsigned gpio, irq, bank; | |
274 | struct clk *clk; | |
474dad54 | 275 | u32 binten = 0; |
a994955c MG |
276 | unsigned ngpio, bank_irq; |
277 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
278 | ||
279 | ngpio = soc_info->gpio_num; | |
474dad54 | 280 | |
a994955c MG |
281 | bank_irq = soc_info->gpio_irq; |
282 | if (bank_irq == 0) { | |
474dad54 DB |
283 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); |
284 | return -EINVAL; | |
285 | } | |
3d9edf09 VB |
286 | |
287 | clk = clk_get(NULL, "gpio"); | |
288 | if (IS_ERR(clk)) { | |
289 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
290 | PTR_ERR(clk)); | |
474dad54 | 291 | return PTR_ERR(clk); |
3d9edf09 | 292 | } |
3d9edf09 VB |
293 | clk_enable(clk); |
294 | ||
474dad54 DB |
295 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
296 | gpio < ngpio; | |
297 | bank++, bank_irq++) { | |
3d9edf09 VB |
298 | struct gpio_controller *__iomem g = gpio2controller(gpio); |
299 | unsigned i; | |
300 | ||
301 | __raw_writel(~0, &g->clr_falling); | |
302 | __raw_writel(~0, &g->clr_rising); | |
303 | ||
304 | /* set up all irqs in this bank */ | |
474dad54 DB |
305 | set_irq_chained_handler(bank_irq, gpio_irq_handler); |
306 | set_irq_chip_data(bank_irq, g); | |
307 | set_irq_data(bank_irq, (void *)irq); | |
3d9edf09 | 308 | |
474dad54 | 309 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
3d9edf09 VB |
310 | set_irq_chip(irq, &gpio_irqchip); |
311 | set_irq_chip_data(irq, g); | |
312 | set_irq_handler(irq, handle_simple_irq); | |
313 | set_irq_flags(irq, IRQF_VALID); | |
314 | } | |
474dad54 DB |
315 | |
316 | binten |= BIT(bank); | |
3d9edf09 VB |
317 | } |
318 | ||
319 | /* BINTEN -- per-bank interrupt enable. genirq would also let these | |
320 | * bits be set/cleared dynamically. | |
321 | */ | |
a994955c | 322 | __raw_writel(binten, soc_info->gpio_base + 0x08); |
3d9edf09 VB |
323 | |
324 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); | |
325 | ||
326 | return 0; | |
327 | } |