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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/bitops.h> | |
22 | ||
474dad54 | 23 | #include <mach/cputype.h> |
a09e64fb RK |
24 | #include <mach/irqs.h> |
25 | #include <mach/hardware.h> | |
26 | #include <mach/gpio.h> | |
3d9edf09 VB |
27 | |
28 | #include <asm/mach/irq.h> | |
29 | ||
3d9edf09 | 30 | |
dce1115b | 31 | static DEFINE_SPINLOCK(gpio_lock); |
3d9edf09 | 32 | |
dce1115b DB |
33 | struct davinci_gpio { |
34 | struct gpio_chip chip; | |
35 | struct gpio_controller *__iomem regs; | |
36 | }; | |
3d9edf09 | 37 | |
dce1115b | 38 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
3d9edf09 | 39 | |
474dad54 | 40 | static unsigned __initdata ngpio; |
3d9edf09 VB |
41 | |
42 | /* create a non-inlined version */ | |
474dad54 | 43 | static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) |
3d9edf09 VB |
44 | { |
45 | return __gpio_to_controller(gpio); | |
46 | } | |
47 | ||
dc756026 | 48 | static int __init davinci_gpio_irq_setup(void); |
dce1115b DB |
49 | |
50 | /*--------------------------------------------------------------------------*/ | |
51 | ||
3d9edf09 | 52 | /* |
dce1115b DB |
53 | * board setup code *MUST* set PINMUX0 and PINMUX1 as |
54 | * needed, and enable the GPIO clock. | |
3d9edf09 | 55 | */ |
dce1115b DB |
56 | |
57 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) | |
3d9edf09 | 58 | { |
dce1115b DB |
59 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
60 | struct gpio_controller *__iomem g = d->regs; | |
61 | u32 temp; | |
3d9edf09 | 62 | |
dce1115b DB |
63 | spin_lock(&gpio_lock); |
64 | temp = __raw_readl(&g->dir); | |
65 | temp |= (1 << offset); | |
66 | __raw_writel(temp, &g->dir); | |
67 | spin_unlock(&gpio_lock); | |
3d9edf09 | 68 | |
dce1115b DB |
69 | return 0; |
70 | } | |
3d9edf09 VB |
71 | |
72 | /* | |
73 | * Read the pin's value (works even if it's set up as output); | |
74 | * returns zero/nonzero. | |
75 | * | |
76 | * Note that changes are synched to the GPIO clock, so reading values back | |
77 | * right after you've set them may give old values. | |
78 | */ | |
dce1115b | 79 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 80 | { |
dce1115b DB |
81 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
82 | struct gpio_controller *__iomem g = d->regs; | |
3d9edf09 | 83 | |
dce1115b | 84 | return (1 << offset) & __raw_readl(&g->in_data); |
3d9edf09 | 85 | } |
3d9edf09 | 86 | |
dce1115b DB |
87 | static int |
88 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 89 | { |
dce1115b DB |
90 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
91 | struct gpio_controller *__iomem g = d->regs; | |
3d9edf09 | 92 | u32 temp; |
dce1115b | 93 | u32 mask = 1 << offset; |
3d9edf09 VB |
94 | |
95 | spin_lock(&gpio_lock); | |
3d9edf09 | 96 | temp = __raw_readl(&g->dir); |
dce1115b DB |
97 | temp &= ~mask; |
98 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); | |
3d9edf09 VB |
99 | __raw_writel(temp, &g->dir); |
100 | spin_unlock(&gpio_lock); | |
101 | return 0; | |
102 | } | |
3d9edf09 | 103 | |
dce1115b DB |
104 | /* |
105 | * Assuming the pin is muxed as a gpio output, set its output value. | |
106 | */ | |
107 | static void | |
108 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 109 | { |
dce1115b DB |
110 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
111 | struct gpio_controller *__iomem g = d->regs; | |
3d9edf09 | 112 | |
dce1115b DB |
113 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
114 | } | |
115 | ||
116 | static int __init davinci_gpio_setup(void) | |
117 | { | |
118 | int i, base; | |
119 | ||
474dad54 DB |
120 | /* The gpio banks conceptually expose a segmented bitmap, |
121 | * and "ngpio" is one more than the largest zero-based | |
122 | * bit index that's valid. | |
123 | */ | |
124 | if (cpu_is_davinci_dm355()) { /* or dm335() */ | |
125 | ngpio = 104; | |
126 | } else if (cpu_is_davinci_dm644x()) { /* or dm337() */ | |
127 | ngpio = 71; | |
128 | } else if (cpu_is_davinci_dm646x()) { | |
129 | /* NOTE: each bank has several "reserved" bits, | |
130 | * unusable as GPIOs. Only 33 of the GPIO numbers | |
131 | * are usable, and we're not rejecting the others. | |
132 | */ | |
133 | ngpio = 43; | |
134 | } else { | |
135 | /* if cpu_is_davinci_dm643x() ngpio = 111 */ | |
136 | pr_err("GPIO setup: how many GPIOs?\n"); | |
137 | return -EINVAL; | |
138 | } | |
139 | ||
140 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) | |
141 | ngpio = DAVINCI_N_GPIO; | |
142 | ||
143 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { | |
dce1115b DB |
144 | chips[i].chip.label = "DaVinci"; |
145 | ||
146 | chips[i].chip.direction_input = davinci_direction_in; | |
147 | chips[i].chip.get = davinci_gpio_get; | |
148 | chips[i].chip.direction_output = davinci_direction_out; | |
149 | chips[i].chip.set = davinci_gpio_set; | |
150 | ||
151 | chips[i].chip.base = base; | |
474dad54 | 152 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
153 | if (chips[i].chip.ngpio > 32) |
154 | chips[i].chip.ngpio = 32; | |
155 | ||
156 | chips[i].regs = gpio2controller(base); | |
157 | ||
158 | gpiochip_add(&chips[i].chip); | |
159 | } | |
3d9edf09 | 160 | |
dc756026 | 161 | davinci_gpio_irq_setup(); |
3d9edf09 VB |
162 | return 0; |
163 | } | |
dce1115b | 164 | pure_initcall(davinci_gpio_setup); |
3d9edf09 | 165 | |
dce1115b | 166 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
167 | /* |
168 | * We expect irqs will normally be set up as input pins, but they can also be | |
169 | * used as output pins ... which is convenient for testing. | |
170 | * | |
474dad54 DB |
171 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
172 | * to their GPIOBNK0 irq, with a bit less overhead but less flexibility | |
173 | * on triggering (e.g. no edge options). We don't try to use those. | |
3d9edf09 | 174 | * |
474dad54 | 175 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
176 | * serve as EDMA event triggers. |
177 | */ | |
178 | ||
179 | static void gpio_irq_disable(unsigned irq) | |
180 | { | |
181 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
182 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | |
183 | ||
184 | __raw_writel(mask, &g->clr_falling); | |
185 | __raw_writel(mask, &g->clr_rising); | |
186 | } | |
187 | ||
188 | static void gpio_irq_enable(unsigned irq) | |
189 | { | |
190 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
191 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | |
df4aab46 | 192 | unsigned status = irq_desc[irq].status; |
3d9edf09 | 193 | |
df4aab46 DB |
194 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
195 | if (!status) | |
196 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
197 | ||
198 | if (status & IRQ_TYPE_EDGE_FALLING) | |
3d9edf09 | 199 | __raw_writel(mask, &g->set_falling); |
df4aab46 | 200 | if (status & IRQ_TYPE_EDGE_RISING) |
3d9edf09 VB |
201 | __raw_writel(mask, &g->set_rising); |
202 | } | |
203 | ||
204 | static int gpio_irq_type(unsigned irq, unsigned trigger) | |
205 | { | |
206 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
207 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | |
208 | ||
209 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
210 | return -EINVAL; | |
211 | ||
212 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
213 | irq_desc[irq].status |= trigger; | |
214 | ||
df4aab46 DB |
215 | /* don't enable the IRQ if it's currently disabled */ |
216 | if (irq_desc[irq].depth == 0) { | |
217 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
218 | ? &g->set_falling : &g->clr_falling); | |
219 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
220 | ? &g->set_rising : &g->clr_rising); | |
221 | } | |
3d9edf09 VB |
222 | return 0; |
223 | } | |
224 | ||
225 | static struct irq_chip gpio_irqchip = { | |
226 | .name = "GPIO", | |
227 | .enable = gpio_irq_enable, | |
228 | .disable = gpio_irq_disable, | |
229 | .set_type = gpio_irq_type, | |
230 | }; | |
231 | ||
232 | static void | |
233 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
234 | { | |
235 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | |
236 | u32 mask = 0xffff; | |
237 | ||
238 | /* we only care about one bank */ | |
239 | if (irq & 1) | |
240 | mask <<= 16; | |
241 | ||
242 | /* temporarily mask (level sensitive) parent IRQ */ | |
dc756026 | 243 | desc->chip->mask(irq); |
3d9edf09 VB |
244 | desc->chip->ack(irq); |
245 | while (1) { | |
246 | u32 status; | |
3d9edf09 VB |
247 | int n; |
248 | int res; | |
249 | ||
250 | /* ack any irqs */ | |
251 | status = __raw_readl(&g->intstat) & mask; | |
252 | if (!status) | |
253 | break; | |
254 | __raw_writel(status, &g->intstat); | |
255 | if (irq & 1) | |
256 | status >>= 16; | |
257 | ||
258 | /* now demux them to the right lowlevel handler */ | |
259 | n = (int)get_irq_data(irq); | |
3d9edf09 VB |
260 | while (status) { |
261 | res = ffs(status); | |
262 | n += res; | |
d8aa0251 | 263 | generic_handle_irq(n - 1); |
3d9edf09 VB |
264 | status >>= res; |
265 | } | |
266 | } | |
267 | desc->chip->unmask(irq); | |
268 | /* now it may re-trigger */ | |
269 | } | |
270 | ||
271 | /* | |
474dad54 DB |
272 | * NOTE: for suspend/resume, probably best to make a platform_device with |
273 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
274 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
275 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 276 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
277 | */ |
278 | ||
279 | static int __init davinci_gpio_irq_setup(void) | |
280 | { | |
281 | unsigned gpio, irq, bank; | |
474dad54 | 282 | unsigned bank_irq; |
3d9edf09 | 283 | struct clk *clk; |
474dad54 DB |
284 | u32 binten = 0; |
285 | ||
286 | if (cpu_is_davinci_dm355()) { /* or dm335() */ | |
287 | bank_irq = IRQ_DM355_GPIOBNK0; | |
288 | } else if (cpu_is_davinci_dm644x()) { | |
289 | bank_irq = IRQ_GPIOBNK0; | |
290 | } else if (cpu_is_davinci_dm646x()) { | |
291 | bank_irq = IRQ_DM646X_GPIOBNK0; | |
292 | } else { | |
293 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); | |
294 | return -EINVAL; | |
295 | } | |
3d9edf09 VB |
296 | |
297 | clk = clk_get(NULL, "gpio"); | |
298 | if (IS_ERR(clk)) { | |
299 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
300 | PTR_ERR(clk)); | |
474dad54 | 301 | return PTR_ERR(clk); |
3d9edf09 | 302 | } |
3d9edf09 VB |
303 | clk_enable(clk); |
304 | ||
474dad54 DB |
305 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
306 | gpio < ngpio; | |
307 | bank++, bank_irq++) { | |
3d9edf09 VB |
308 | struct gpio_controller *__iomem g = gpio2controller(gpio); |
309 | unsigned i; | |
310 | ||
311 | __raw_writel(~0, &g->clr_falling); | |
312 | __raw_writel(~0, &g->clr_rising); | |
313 | ||
314 | /* set up all irqs in this bank */ | |
474dad54 DB |
315 | set_irq_chained_handler(bank_irq, gpio_irq_handler); |
316 | set_irq_chip_data(bank_irq, g); | |
317 | set_irq_data(bank_irq, (void *)irq); | |
3d9edf09 | 318 | |
474dad54 | 319 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
3d9edf09 VB |
320 | set_irq_chip(irq, &gpio_irqchip); |
321 | set_irq_chip_data(irq, g); | |
322 | set_irq_handler(irq, handle_simple_irq); | |
323 | set_irq_flags(irq, IRQF_VALID); | |
324 | } | |
474dad54 DB |
325 | |
326 | binten |= BIT(bank); | |
3d9edf09 VB |
327 | } |
328 | ||
329 | /* BINTEN -- per-bank interrupt enable. genirq would also let these | |
330 | * bits be set/cleared dynamically. | |
331 | */ | |
474dad54 | 332 | __raw_writel(binten, (void *__iomem) |
3d9edf09 VB |
333 | IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); |
334 | ||
335 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); | |
336 | ||
337 | return 0; | |
338 | } |