Commit | Line | Data |
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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
3d9edf09 | 18 | |
a09e64fb | 19 | #include <mach/gpio.h> |
3d9edf09 VB |
20 | |
21 | #include <asm/mach/irq.h> | |
22 | ||
dce1115b | 23 | static DEFINE_SPINLOCK(gpio_lock); |
3d9edf09 | 24 | |
dce1115b DB |
25 | struct davinci_gpio { |
26 | struct gpio_chip chip; | |
28552c2e | 27 | struct gpio_controller __iomem *regs; |
7a36071e | 28 | int irq_base; |
dce1115b | 29 | }; |
3d9edf09 | 30 | |
dce1115b | 31 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
3d9edf09 | 32 | |
3d9edf09 | 33 | /* create a non-inlined version */ |
28552c2e | 34 | static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio) |
3d9edf09 VB |
35 | { |
36 | return __gpio_to_controller(gpio); | |
37 | } | |
38 | ||
21ce873d KH |
39 | static inline struct gpio_controller __iomem *irq2controller(int irq) |
40 | { | |
41 | struct gpio_controller __iomem *g; | |
42 | ||
43 | g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq); | |
44 | ||
45 | return g; | |
46 | } | |
47 | ||
dc756026 | 48 | static int __init davinci_gpio_irq_setup(void); |
dce1115b DB |
49 | |
50 | /*--------------------------------------------------------------------------*/ | |
51 | ||
3d9edf09 | 52 | /* |
dce1115b DB |
53 | * board setup code *MUST* set PINMUX0 and PINMUX1 as |
54 | * needed, and enable the GPIO clock. | |
3d9edf09 | 55 | */ |
dce1115b DB |
56 | |
57 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) | |
3d9edf09 | 58 | { |
dce1115b | 59 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
28552c2e | 60 | struct gpio_controller __iomem *g = d->regs; |
dce1115b | 61 | u32 temp; |
3d9edf09 | 62 | |
dce1115b DB |
63 | spin_lock(&gpio_lock); |
64 | temp = __raw_readl(&g->dir); | |
65 | temp |= (1 << offset); | |
66 | __raw_writel(temp, &g->dir); | |
67 | spin_unlock(&gpio_lock); | |
3d9edf09 | 68 | |
dce1115b DB |
69 | return 0; |
70 | } | |
3d9edf09 VB |
71 | |
72 | /* | |
73 | * Read the pin's value (works even if it's set up as output); | |
74 | * returns zero/nonzero. | |
75 | * | |
76 | * Note that changes are synched to the GPIO clock, so reading values back | |
77 | * right after you've set them may give old values. | |
78 | */ | |
dce1115b | 79 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 80 | { |
dce1115b | 81 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
28552c2e | 82 | struct gpio_controller __iomem *g = d->regs; |
3d9edf09 | 83 | |
dce1115b | 84 | return (1 << offset) & __raw_readl(&g->in_data); |
3d9edf09 | 85 | } |
3d9edf09 | 86 | |
dce1115b DB |
87 | static int |
88 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 89 | { |
dce1115b | 90 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
28552c2e | 91 | struct gpio_controller __iomem *g = d->regs; |
3d9edf09 | 92 | u32 temp; |
dce1115b | 93 | u32 mask = 1 << offset; |
3d9edf09 VB |
94 | |
95 | spin_lock(&gpio_lock); | |
3d9edf09 | 96 | temp = __raw_readl(&g->dir); |
dce1115b DB |
97 | temp &= ~mask; |
98 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); | |
3d9edf09 VB |
99 | __raw_writel(temp, &g->dir); |
100 | spin_unlock(&gpio_lock); | |
101 | return 0; | |
102 | } | |
3d9edf09 | 103 | |
dce1115b DB |
104 | /* |
105 | * Assuming the pin is muxed as a gpio output, set its output value. | |
106 | */ | |
107 | static void | |
108 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 109 | { |
dce1115b | 110 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
28552c2e | 111 | struct gpio_controller __iomem *g = d->regs; |
3d9edf09 | 112 | |
dce1115b DB |
113 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
114 | } | |
115 | ||
116 | static int __init davinci_gpio_setup(void) | |
117 | { | |
118 | int i, base; | |
a994955c MG |
119 | unsigned ngpio; |
120 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
dce1115b | 121 | |
a994955c MG |
122 | /* |
123 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
124 | * and "ngpio" is one more than the largest zero-based |
125 | * bit index that's valid. | |
126 | */ | |
a994955c MG |
127 | ngpio = soc_info->gpio_num; |
128 | if (ngpio == 0) { | |
474dad54 DB |
129 | pr_err("GPIO setup: how many GPIOs?\n"); |
130 | return -EINVAL; | |
131 | } | |
132 | ||
133 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) | |
134 | ngpio = DAVINCI_N_GPIO; | |
135 | ||
136 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { | |
dce1115b DB |
137 | chips[i].chip.label = "DaVinci"; |
138 | ||
139 | chips[i].chip.direction_input = davinci_direction_in; | |
140 | chips[i].chip.get = davinci_gpio_get; | |
141 | chips[i].chip.direction_output = davinci_direction_out; | |
142 | chips[i].chip.set = davinci_gpio_set; | |
143 | ||
144 | chips[i].chip.base = base; | |
474dad54 | 145 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
146 | if (chips[i].chip.ngpio > 32) |
147 | chips[i].chip.ngpio = 32; | |
148 | ||
149 | chips[i].regs = gpio2controller(base); | |
150 | ||
151 | gpiochip_add(&chips[i].chip); | |
152 | } | |
3d9edf09 | 153 | |
dc756026 | 154 | davinci_gpio_irq_setup(); |
3d9edf09 VB |
155 | return 0; |
156 | } | |
dce1115b | 157 | pure_initcall(davinci_gpio_setup); |
3d9edf09 | 158 | |
dce1115b | 159 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
160 | /* |
161 | * We expect irqs will normally be set up as input pins, but they can also be | |
162 | * used as output pins ... which is convenient for testing. | |
163 | * | |
474dad54 | 164 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 165 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 166 | * |
474dad54 | 167 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
168 | * serve as EDMA event triggers. |
169 | */ | |
170 | ||
171 | static void gpio_irq_disable(unsigned irq) | |
172 | { | |
21ce873d | 173 | struct gpio_controller __iomem *g = irq2controller(irq); |
7a36071e | 174 | u32 mask = (u32) get_irq_data(irq); |
3d9edf09 VB |
175 | |
176 | __raw_writel(mask, &g->clr_falling); | |
177 | __raw_writel(mask, &g->clr_rising); | |
178 | } | |
179 | ||
180 | static void gpio_irq_enable(unsigned irq) | |
181 | { | |
21ce873d | 182 | struct gpio_controller __iomem *g = irq2controller(irq); |
7a36071e | 183 | u32 mask = (u32) get_irq_data(irq); |
df4aab46 | 184 | unsigned status = irq_desc[irq].status; |
3d9edf09 | 185 | |
df4aab46 DB |
186 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
187 | if (!status) | |
188 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
189 | ||
190 | if (status & IRQ_TYPE_EDGE_FALLING) | |
3d9edf09 | 191 | __raw_writel(mask, &g->set_falling); |
df4aab46 | 192 | if (status & IRQ_TYPE_EDGE_RISING) |
3d9edf09 VB |
193 | __raw_writel(mask, &g->set_rising); |
194 | } | |
195 | ||
196 | static int gpio_irq_type(unsigned irq, unsigned trigger) | |
197 | { | |
21ce873d | 198 | struct gpio_controller __iomem *g = irq2controller(irq); |
7a36071e | 199 | u32 mask = (u32) get_irq_data(irq); |
3d9edf09 VB |
200 | |
201 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
202 | return -EINVAL; | |
203 | ||
204 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
205 | irq_desc[irq].status |= trigger; | |
206 | ||
df4aab46 DB |
207 | /* don't enable the IRQ if it's currently disabled */ |
208 | if (irq_desc[irq].depth == 0) { | |
209 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
210 | ? &g->set_falling : &g->clr_falling); | |
211 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
212 | ? &g->set_rising : &g->clr_rising); | |
213 | } | |
3d9edf09 VB |
214 | return 0; |
215 | } | |
216 | ||
217 | static struct irq_chip gpio_irqchip = { | |
218 | .name = "GPIO", | |
219 | .enable = gpio_irq_enable, | |
220 | .disable = gpio_irq_disable, | |
221 | .set_type = gpio_irq_type, | |
222 | }; | |
223 | ||
224 | static void | |
225 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
226 | { | |
21ce873d | 227 | struct gpio_controller __iomem *g = irq2controller(irq); |
3d9edf09 VB |
228 | u32 mask = 0xffff; |
229 | ||
230 | /* we only care about one bank */ | |
231 | if (irq & 1) | |
232 | mask <<= 16; | |
233 | ||
234 | /* temporarily mask (level sensitive) parent IRQ */ | |
dc756026 | 235 | desc->chip->mask(irq); |
3d9edf09 VB |
236 | desc->chip->ack(irq); |
237 | while (1) { | |
238 | u32 status; | |
3d9edf09 VB |
239 | int n; |
240 | int res; | |
241 | ||
242 | /* ack any irqs */ | |
243 | status = __raw_readl(&g->intstat) & mask; | |
244 | if (!status) | |
245 | break; | |
246 | __raw_writel(status, &g->intstat); | |
247 | if (irq & 1) | |
248 | status >>= 16; | |
249 | ||
250 | /* now demux them to the right lowlevel handler */ | |
251 | n = (int)get_irq_data(irq); | |
3d9edf09 VB |
252 | while (status) { |
253 | res = ffs(status); | |
254 | n += res; | |
d8aa0251 | 255 | generic_handle_irq(n - 1); |
3d9edf09 VB |
256 | status >>= res; |
257 | } | |
258 | } | |
259 | desc->chip->unmask(irq); | |
260 | /* now it may re-trigger */ | |
261 | } | |
262 | ||
7a36071e DB |
263 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
264 | { | |
265 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); | |
266 | ||
267 | if (d->irq_base >= 0) | |
268 | return d->irq_base + offset; | |
269 | else | |
270 | return -ENODEV; | |
271 | } | |
272 | ||
273 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
274 | { | |
275 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
276 | ||
277 | /* NOTE: we assume for now that only irqs in the first gpio_chip | |
278 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). | |
279 | */ | |
280 | if (offset < soc_info->gpio_unbanked) | |
281 | return soc_info->gpio_irq + offset; | |
282 | else | |
283 | return -ENODEV; | |
284 | } | |
285 | ||
286 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) | |
287 | { | |
21ce873d | 288 | struct gpio_controller __iomem *g = irq2controller(irq); |
7a36071e DB |
289 | u32 mask = (u32) get_irq_data(irq); |
290 | ||
291 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
292 | return -EINVAL; | |
293 | ||
294 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
295 | ? &g->set_falling : &g->clr_falling); | |
296 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
297 | ? &g->set_rising : &g->clr_rising); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
3d9edf09 | 302 | /* |
474dad54 DB |
303 | * NOTE: for suspend/resume, probably best to make a platform_device with |
304 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
305 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
306 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 307 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
308 | */ |
309 | ||
310 | static int __init davinci_gpio_irq_setup(void) | |
311 | { | |
312 | unsigned gpio, irq, bank; | |
313 | struct clk *clk; | |
474dad54 | 314 | u32 binten = 0; |
a994955c MG |
315 | unsigned ngpio, bank_irq; |
316 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
28552c2e | 317 | struct gpio_controller __iomem *g; |
a994955c MG |
318 | |
319 | ngpio = soc_info->gpio_num; | |
474dad54 | 320 | |
a994955c MG |
321 | bank_irq = soc_info->gpio_irq; |
322 | if (bank_irq == 0) { | |
474dad54 DB |
323 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); |
324 | return -EINVAL; | |
325 | } | |
3d9edf09 VB |
326 | |
327 | clk = clk_get(NULL, "gpio"); | |
328 | if (IS_ERR(clk)) { | |
329 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
330 | PTR_ERR(clk)); | |
474dad54 | 331 | return PTR_ERR(clk); |
3d9edf09 | 332 | } |
3d9edf09 VB |
333 | clk_enable(clk); |
334 | ||
7a36071e DB |
335 | /* Arrange gpio_to_irq() support, handling either direct IRQs or |
336 | * banked IRQs. Having GPIOs in the first GPIO bank use direct | |
337 | * IRQs, while the others use banked IRQs, would need some setup | |
338 | * tweaks to recognize hardware which can do that. | |
339 | */ | |
340 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
341 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
342 | chips[bank].irq_base = soc_info->gpio_unbanked | |
343 | ? -EINVAL | |
344 | : (soc_info->intc_irq_num + gpio); | |
345 | } | |
346 | ||
347 | /* | |
348 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
349 | * controller only handling trigger modes. We currently assume no | |
350 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
351 | */ | |
352 | if (soc_info->gpio_unbanked) { | |
353 | static struct irq_chip gpio_irqchip_unbanked; | |
354 | ||
355 | /* pass "bank 0" GPIO IRQs to AINTC */ | |
356 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
357 | binten = BIT(0); | |
358 | ||
359 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
360 | irq = bank_irq; | |
361 | gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); | |
362 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; | |
363 | gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; | |
364 | ||
365 | /* default trigger: both edges */ | |
366 | g = gpio2controller(0); | |
367 | __raw_writel(~0, &g->set_falling); | |
368 | __raw_writel(~0, &g->set_rising); | |
369 | ||
370 | /* set the direct IRQs up to use that irqchip */ | |
371 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | |
372 | set_irq_chip(irq, &gpio_irqchip_unbanked); | |
373 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | |
21ce873d | 374 | set_irq_chip_data(irq, (__force void *) g); |
7a36071e DB |
375 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; |
376 | } | |
377 | ||
378 | goto done; | |
379 | } | |
380 | ||
381 | /* | |
382 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
383 | * then chain through our own handler. | |
384 | */ | |
474dad54 DB |
385 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
386 | gpio < ngpio; | |
387 | bank++, bank_irq++) { | |
3d9edf09 VB |
388 | unsigned i; |
389 | ||
7a36071e DB |
390 | /* disabled by default, enabled only as needed */ |
391 | g = gpio2controller(gpio); | |
3d9edf09 VB |
392 | __raw_writel(~0, &g->clr_falling); |
393 | __raw_writel(~0, &g->clr_rising); | |
394 | ||
395 | /* set up all irqs in this bank */ | |
474dad54 | 396 | set_irq_chained_handler(bank_irq, gpio_irq_handler); |
21ce873d KH |
397 | set_irq_chip_data(bank_irq, (__force void *) g); |
398 | set_irq_data(bank_irq, (void *) irq); | |
3d9edf09 | 399 | |
474dad54 | 400 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
3d9edf09 | 401 | set_irq_chip(irq, &gpio_irqchip); |
21ce873d | 402 | set_irq_chip_data(irq, (__force void *) g); |
7a36071e | 403 | set_irq_data(irq, (void *) __gpio_mask(gpio)); |
3d9edf09 VB |
404 | set_irq_handler(irq, handle_simple_irq); |
405 | set_irq_flags(irq, IRQF_VALID); | |
406 | } | |
474dad54 DB |
407 | |
408 | binten |= BIT(bank); | |
3d9edf09 VB |
409 | } |
410 | ||
7a36071e | 411 | done: |
3d9edf09 VB |
412 | /* BINTEN -- per-bank interrupt enable. genirq would also let these |
413 | * bits be set/cleared dynamically. | |
414 | */ | |
a994955c | 415 | __raw_writel(binten, soc_info->gpio_base + 0x08); |
3d9edf09 VB |
416 | |
417 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); | |
418 | ||
419 | return 0; | |
420 | } |