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clk: Remove io.h from clk-provider.h
[linux-block.git] / arch / arm / mach-davinci / dm646x.c
CommitLineData
e38d92fd
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
81df7d85
DL		 11
12#include <linux/clk-provider.h>
13#include <linux/clk/davinci.h>
14#include <linux/clkdev.h>
b7f080cf 15#include <linux/dma-mapping.h>
2137d54d 16#include <linux/dmaengine.h>
e38d92fd 17#include <linux/init.h>
62e59c4e 18#include <linux/io.h>
fd0f4275 19#include <linux/irqchip/irq-davinci-aintc.h>
3ad7a42d 20#include <linux/platform_data/edma.h>
9cc1515c 21#include <linux/platform_data/gpio-davinci.h>
81df7d85
DL		 22#include <linux/platform_device.h>
23#include <linux/serial_8250.h>
e38d92fd 24
79c3c0b7
MG		 25#include <asm/mach/map.h>
26
81df7d85 27#include <mach/common.h>
e38d92fd 28#include <mach/cputype.h>
e38d92fd 29#include <mach/mux.h>
65e866a9 30#include <mach/serial.h>
81df7d85 31#include <mach/time.h>
e38d92fd 32
81df7d85 33#include "asp.h"
39c6d2d1 34#include "davinci.h"
544ca0b0 35#include "irqs.h"
e38d92fd 36#include "mux.h"
81df7d85 37
85609c1c 38#define DAVINCI_VPIF_BASE (0x01C12000)
85609c1c
MK		 39
40#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
41 BIT_MASK(0))
42#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
43 BIT_MASK(8))
44
3d091406
MH		 45#define DM646X_EMAC_BASE 0x01c80000
46#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
47#define DM646X_EMAC_CNTRL_OFFSET 0x0000
48#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
49#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
50#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
51
972412b6
MG		 52static struct emac_platform_data dm646x_emac_pdata = {
53 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
54 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
55 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 56 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
57 .version = EMAC_VERSION_2,
58};
59
ac7b75b5
KH		 60static struct resource dm646x_emac_resources[] = {
61 {
62 .start = DM646X_EMAC_BASE,
d22960c8 63 .end = DM646X_EMAC_BASE + SZ_16K - 1,
ac7b75b5
KH		 64 .flags = IORESOURCE_MEM,
65 },
66 {
a98ca73e
BG		 67 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
68 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
ac7b75b5
KH		 69 .flags = IORESOURCE_IRQ,
70 },
71 {
a98ca73e
BG		 72 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
73 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
ac7b75b5
KH		 74 .flags = IORESOURCE_IRQ,
75 },
76 {
a98ca73e
BG		 77 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
78 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
ac7b75b5
KH		 79 .flags = IORESOURCE_IRQ,
80 },
81 {
a98ca73e
BG		 82 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
83 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
ac7b75b5
KH		 84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct platform_device dm646x_emac_device = {
89 .name = "davinci_emac",
90 .id = 1,
972412b6
MG		 91 .dev = {
92 .platform_data = &dm646x_emac_pdata,
93 },
ac7b75b5
KH		 94 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
95 .resource = dm646x_emac_resources,
96};
97
d22960c8
CC		 98static struct resource dm646x_mdio_resources[] = {
99 {
100 .start = DM646X_EMAC_MDIO_BASE,
101 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
102 .flags = IORESOURCE_MEM,
103 },
104};
105
106static struct platform_device dm646x_mdio_device = {
107 .name = "davinci_mdio",
108 .id = 0,
109 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
110 .resource = dm646x_mdio_resources,
111};
112
e38d92fd
KH		 113/*
114 * Device specific mux setup
115 *
116 * soc description mux mode mode mux dbg
117 * reg offset mask mode
118 */
119static const struct mux_config dm646x_pins[] = {
0e585952 120#ifdef CONFIG_DAVINCI_MUX
3e25d5f4 121MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
e38d92fd
KH		 122
123MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
124
125MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
126
127MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
128
129MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
130
131MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
132
133MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
134
135MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
136
137MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
138
139MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
140
141MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
142
143MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
144
145MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
146
147MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952 148#endif
e38d92fd
KH		 149};
150
673dd36f
MG		 151static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
152 [IRQ_DM646X_VP_VERTINT0] = 7,
153 [IRQ_DM646X_VP_VERTINT1] = 7,
154 [IRQ_DM646X_VP_VERTINT2] = 7,
155 [IRQ_DM646X_VP_VERTINT3] = 7,
156 [IRQ_DM646X_VP_ERRINT] = 7,
157 [IRQ_DM646X_RESERVED_1] = 7,
158 [IRQ_DM646X_RESERVED_2] = 7,
159 [IRQ_DM646X_WDINT] = 7,
160 [IRQ_DM646X_CRGENINT0] = 7,
161 [IRQ_DM646X_CRGENINT1] = 7,
162 [IRQ_DM646X_TSIFINT0] = 7,
163 [IRQ_DM646X_TSIFINT1] = 7,
164 [IRQ_DM646X_VDCEINT] = 7,
165 [IRQ_DM646X_USBINT] = 7,
166 [IRQ_DM646X_USBDMAINT] = 7,
167 [IRQ_DM646X_PCIINT] = 7,
168 [IRQ_CCINT0] = 7, /* dma */
169 [IRQ_CCERRINT] = 7, /* dma */
170 [IRQ_TCERRINT0] = 7, /* dma */
171 [IRQ_TCERRINT] = 7, /* dma */
172 [IRQ_DM646X_TCERRINT2] = 7,
173 [IRQ_DM646X_TCERRINT3] = 7,
174 [IRQ_DM646X_IDE] = 7,
175 [IRQ_DM646X_HPIINT] = 7,
176 [IRQ_DM646X_EMACRXTHINT] = 7,
177 [IRQ_DM646X_EMACRXINT] = 7,
178 [IRQ_DM646X_EMACTXINT] = 7,
179 [IRQ_DM646X_EMACMISCINT] = 7,
180 [IRQ_DM646X_MCASP0TXINT] = 7,
181 [IRQ_DM646X_MCASP0RXINT] = 7,
673dd36f 182 [IRQ_DM646X_RESERVED_3] = 7,
73d4337e
SN		 183 [IRQ_DM646X_MCASP1TXINT] = 7,
184 [IRQ_TINT0_TINT12] = 7, /* clockevent */
673dd36f
MG		 185 [IRQ_TINT0_TINT34] = 7, /* clocksource */
186 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
187 [IRQ_TINT1_TINT34] = 7, /* system tick */
188 [IRQ_PWMINT0] = 7,
189 [IRQ_PWMINT1] = 7,
190 [IRQ_DM646X_VLQINT] = 7,
191 [IRQ_I2C] = 7,
192 [IRQ_UARTINT0] = 7,
193 [IRQ_UARTINT1] = 7,
194 [IRQ_DM646X_UARTINT2] = 7,
195 [IRQ_DM646X_SPINT0] = 7,
196 [IRQ_DM646X_SPINT1] = 7,
197 [IRQ_DM646X_DSP2ARMINT] = 7,
198 [IRQ_DM646X_RESERVED_4] = 7,
199 [IRQ_DM646X_PSCINT] = 7,
200 [IRQ_DM646X_GPIO0] = 7,
201 [IRQ_DM646X_GPIO1] = 7,
202 [IRQ_DM646X_GPIO2] = 7,
203 [IRQ_DM646X_GPIO3] = 7,
204 [IRQ_DM646X_GPIO4] = 7,
205 [IRQ_DM646X_GPIO5] = 7,
206 [IRQ_DM646X_GPIO6] = 7,
207 [IRQ_DM646X_GPIO7] = 7,
208 [IRQ_DM646X_GPIOBNK0] = 7,
209 [IRQ_DM646X_GPIOBNK1] = 7,
210 [IRQ_DM646X_GPIOBNK2] = 7,
211 [IRQ_DM646X_DDRINT] = 7,
212 [IRQ_DM646X_AEMIFINT] = 7,
213 [IRQ_COMMTX] = 7,
214 [IRQ_COMMRX] = 7,
215 [IRQ_EMUINT] = 7,
216};
217
e38d92fd
KH		 218/*----------------------------------------------------------------------*/
219
60902a2c 220/* Four Transfer Controllers on DM646x */
d4cb7f40 221static s8 dm646x_queue_priority_mapping[][2] = {
60902a2c
SR		 222 /* {event queue no, Priority} */
223 {0, 4},
224 {1, 0},
225 {2, 5},
226 {3, 1},
227 {-1, -1},
228};
229
2137d54d
PU		 230static const struct dma_slave_map dm646x_edma_map[] = {
231 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
232 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
233 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
234 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
235 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
236};
237
d4cb7f40 238static struct edma_soc_info dm646x_edma_pdata = {
bc3ac9f3 239 .queue_priority_mapping = dm646x_queue_priority_mapping,
f23fe857 240 .default_queue = EVENTQ_1,
2137d54d
PU		 241 .slave_map = dm646x_edma_map,
242 .slavecnt = ARRAY_SIZE(dm646x_edma_map),
bc3ac9f3
SN		 243};
244
e38d92fd
KH		 245static struct resource edma_resources[] = {
246 {
d4cb7f40 247 .name = "edma3_cc",
e38d92fd
KH		 248 .start = 0x01c00000,
249 .end = 0x01c00000 + SZ_64K - 1,
250 .flags = IORESOURCE_MEM,
251 },
252 {
d4cb7f40 253 .name = "edma3_tc0",
e38d92fd
KH		 254 .start = 0x01c10000,
255 .end = 0x01c10000 + SZ_1K - 1,
256 .flags = IORESOURCE_MEM,
257 },
258 {
d4cb7f40 259 .name = "edma3_tc1",
e38d92fd
KH		 260 .start = 0x01c10400,
261 .end = 0x01c10400 + SZ_1K - 1,
262 .flags = IORESOURCE_MEM,
263 },
264 {
d4cb7f40 265 .name = "edma3_tc2",
e38d92fd
KH		 266 .start = 0x01c10800,
267 .end = 0x01c10800 + SZ_1K - 1,
268 .flags = IORESOURCE_MEM,
269 },
270 {
d4cb7f40 271 .name = "edma3_tc3",
e38d92fd
KH		 272 .start = 0x01c10c00,
273 .end = 0x01c10c00 + SZ_1K - 1,
274 .flags = IORESOURCE_MEM,
275 },
276 {
d4cb7f40 277 .name = "edma3_ccint",
a98ca73e 278 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
e38d92fd
KH		 279 .flags = IORESOURCE_IRQ,
280 },
281 {
d4cb7f40 282 .name = "edma3_ccerrint",
a98ca73e 283 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
e38d92fd
KH		 284 .flags = IORESOURCE_IRQ,
285 },
286 /* not using TC*_ERR */
287};
288
7ab388e8
PU		 289static const struct platform_device_info dm646x_edma_device __initconst = {
290 .name = "edma",
291 .id = 0,
cef5b0da 292 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 293 .res = edma_resources,
294 .num_res = ARRAY_SIZE(edma_resources),
295 .data = &dm646x_edma_pdata,
296 .size_data = sizeof(dm646x_edma_pdata),
e38d92fd
KH		 297};
298
25acf553
C		 299static struct resource dm646x_mcasp0_resources[] = {
300 {
ee880dbd 301 .name = "mpu",
25acf553
C		 302 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
303 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
304 .flags = IORESOURCE_MEM,
305 },
25acf553 306 {
256b20a5 307 .name = "tx",
25acf553
C		 308 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
309 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
310 .flags = IORESOURCE_DMA,
311 },
312 {
256b20a5 313 .name = "rx",
25acf553
C		 314 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
315 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
316 .flags = IORESOURCE_DMA,
317 },
6cfdf55b
PU		 318 {
319 .name = "tx",
a98ca73e 320 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
6cfdf55b
PU		 321 .flags = IORESOURCE_IRQ,
322 },
323 {
324 .name = "rx",
a98ca73e 325 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
6cfdf55b
PU		 326 .flags = IORESOURCE_IRQ,
327 },
25acf553
C		 328};
329
256b20a5 330/* DIT mode only, rx is not supported */
25acf553
C		 331static struct resource dm646x_mcasp1_resources[] = {
332 {
ee880dbd 333 .name = "mpu",
25acf553
C		 334 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
335 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
336 .flags = IORESOURCE_MEM,
337 },
25acf553 338 {
256b20a5 339 .name = "tx",
25acf553
C		 340 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
341 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
342 .flags = IORESOURCE_DMA,
343 },
6cfdf55b
PU		 344 {
345 .name = "tx",
a98ca73e 346 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
6cfdf55b
PU		 347 .flags = IORESOURCE_IRQ,
348 },
25acf553
C		 349};
350
351static struct platform_device dm646x_mcasp0_device = {
352 .name = "davinci-mcasp",
353 .id = 0,
354 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
355 .resource = dm646x_mcasp0_resources,
356};
357
358static struct platform_device dm646x_mcasp1_device = {
359 .name = "davinci-mcasp",
360 .id = 1,
361 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
362 .resource = dm646x_mcasp1_resources,
363};
364
365static struct platform_device dm646x_dit_device = {
366 .name = "spdif-dit",
367 .id = -1,
368};
369
85609c1c
MK		 370static u64 vpif_dma_mask = DMA_BIT_MASK(32);
371
372static struct resource vpif_resource[] = {
373 {
374 .start = DAVINCI_VPIF_BASE,
375 .end = DAVINCI_VPIF_BASE + 0x03ff,
376 .flags = IORESOURCE_MEM,
377 }
378};
379
380static struct platform_device vpif_dev = {
381 .name = "vpif",
382 .id = -1,
383 .dev = {
384 .dma_mask = &vpif_dma_mask,
385 .coherent_dma_mask = DMA_BIT_MASK(32),
386 },
387 .resource = vpif_resource,
388 .num_resources = ARRAY_SIZE(vpif_resource),
389};
390
391static struct resource vpif_display_resource[] = {
392 {
a98ca73e
BG		 393 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
394 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
85609c1c
MK		 395 .flags = IORESOURCE_IRQ,
396 },
397 {
a98ca73e
BG		 398 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
399 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
85609c1c
MK		 400 .flags = IORESOURCE_IRQ,
401 },
402};
403
404static struct platform_device vpif_display_dev = {
405 .name = "vpif_display",
406 .id = -1,
407 .dev = {
408 .dma_mask = &vpif_dma_mask,
409 .coherent_dma_mask = DMA_BIT_MASK(32),
410 },
411 .resource = vpif_display_resource,
412 .num_resources = ARRAY_SIZE(vpif_display_resource),
413};
414
415static struct resource vpif_capture_resource[] = {
416 {
a98ca73e
BG		 417 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
418 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
85609c1c
MK		 419 .flags = IORESOURCE_IRQ,
420 },
421 {
a98ca73e
BG		 422 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
423 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
85609c1c
MK		 424 .flags = IORESOURCE_IRQ,
425 },
426};
427
428static struct platform_device vpif_capture_dev = {
429 .name = "vpif_capture",
430 .id = -1,
431 .dev = {
432 .dma_mask = &vpif_dma_mask,
433 .coherent_dma_mask = DMA_BIT_MASK(32),
434 },
435 .resource = vpif_capture_resource,
436 .num_resources = ARRAY_SIZE(vpif_capture_resource),
437};
438
9cc1515c
PA		 439static struct resource dm646x_gpio_resources[] = {
440 { /* registers */
441 .start = DAVINCI_GPIO_BASE,
442 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
443 .flags = IORESOURCE_MEM,
444 },
445 { /* interrupt */
a98ca73e
BG		 446 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
447 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
2c9c8349
BG		 448 .flags = IORESOURCE_IRQ,
449 },
450 {
a98ca73e
BG		 451 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
452 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
2c9c8349
BG		 453 .flags = IORESOURCE_IRQ,
454 },
455 {
a98ca73e
BG		 456 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
457 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
9cc1515c
PA		 458 .flags = IORESOURCE_IRQ,
459 },
460};
461
462static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
fb9e7f0b
BG		 463 .no_auto_base = true,
464 .base = 0,
9cc1515c 465 .ngpio = 43,
9cc1515c
PA		 466};
467
468int __init dm646x_gpio_register(void)
469{
470 return davinci_gpio_register(dm646x_gpio_resources,
e462f1f5 471 ARRAY_SIZE(dm646x_gpio_resources),
9cc1515c
PA		 472 &dm646x_gpio_platform_data);
473}
e38d92fd
KH		 474/*----------------------------------------------------------------------*/
475
79c3c0b7
MG		 476static struct map_desc dm646x_io_desc[] = {
477 {
478 .virtual = IO_VIRT,
479 .pfn = __phys_to_pfn(IO_PHYS),
480 .length = IO_SIZE,
481 .type = MT_DEVICE
482 },
483};
484
b9ab1279
MG		 485/* Contents of JTAG ID register used to identify exact cpu type */
486static struct davinci_id dm646x_ids[] = {
487 {
488 .variant = 0x0,
489 .part_no = 0xb770,
490 .manufacturer = 0x017,
491 .cpu_id = DAVINCI_CPU_ID_DM6467,
f63dd12d
HP		 492 .name = "dm6467_rev1.x",
493 },
494 {
495 .variant = 0x1,
496 .part_no = 0xb770,
497 .manufacturer = 0x017,
498 .cpu_id = DAVINCI_CPU_ID_DM6467,
499 .name = "dm6467_rev3.x",
b9ab1279
MG		 500 },
501};
502
f64691b3
MG		 503/*
504 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
505 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
506 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
507 * T1_TOP: Timer 1, top : <unused>
508 */
28552c2e 509static struct davinci_timer_info dm646x_timer_info = {
f64691b3
MG		 510 .timers = davinci_timer_instance,
511 .clockevent_id = T0_BOT,
512 .clocksource_id = T0_TOP,
513};
514
19955c3d 515static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
65e866a9
MG		 516 {
517 .mapbase = DAVINCI_UART0_BASE,
a98ca73e 518 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
65e866a9
MG		 519 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
520 UPF_IOREMAP,
521 .iotype = UPIO_MEM32,
522 .regshift = 2,
523 },
19955c3d
MP		 524 {
525 .flags = 0,
526 }
527};
528static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
65e866a9
MG		 529 {
530 .mapbase = DAVINCI_UART1_BASE,
a98ca73e 531 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
65e866a9
MG		 532 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
533 UPF_IOREMAP,
534 .iotype = UPIO_MEM32,
535 .regshift = 2,
536 },
19955c3d
MP		 537 {
538 .flags = 0,
539 }
540};
541static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
65e866a9
MG		 542 {
543 .mapbase = DAVINCI_UART2_BASE,
a98ca73e 544 .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
65e866a9
MG		 545 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
546 UPF_IOREMAP,
547 .iotype = UPIO_MEM32,
548 .regshift = 2,
549 },
550 {
19955c3d
MP		 551 .flags = 0,
552 }
65e866a9
MG		 553};
554
fcf7157b 555struct platform_device dm646x_serial_device[] = {
19955c3d
MP		 556 {
557 .name = "serial8250",
558 .id = PLAT8250_DEV_PLATFORM,
559 .dev = {
560 .platform_data = dm646x_serial0_platform_data,
561 }
562 },
563 {
564 .name = "serial8250",
565 .id = PLAT8250_DEV_PLATFORM1,
566 .dev = {
567 .platform_data = dm646x_serial1_platform_data,
568 }
65e866a9 569 },
19955c3d
MP		 570 {
571 .name = "serial8250",
572 .id = PLAT8250_DEV_PLATFORM2,
573 .dev = {
574 .platform_data = dm646x_serial2_platform_data,
575 }
576 },
577 {
578 }
65e866a9
MG		 579};
580
ab41910d 581static const struct davinci_soc_info davinci_soc_info_dm646x = {
79c3c0b7
MG		 582 .io_desc = dm646x_io_desc,
583 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
3347db83 584 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 585 .ids = dm646x_ids,
586 .ids_num = ARRAY_SIZE(dm646x_ids),
779b0d53 587 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 588 .pinmux_pins = dm646x_pins,
589 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
f64691b3 590 .timer_info = &dm646x_timer_info,
972412b6 591 .emac_pdata = &dm646x_emac_pdata,
0d04eb47
DB		 592 .sram_dma = 0x10010000,
593 .sram_len = SZ_32K,
79c3c0b7
MG		 594};
595
25acf553
C		 596void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
597{
598 dm646x_mcasp0_device.dev.platform_data = pdata;
599 platform_device_register(&dm646x_mcasp0_device);
600}
601
602void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
603{
604 dm646x_mcasp1_device.dev.platform_data = pdata;
605 platform_device_register(&dm646x_mcasp1_device);
606 platform_device_register(&dm646x_dit_device);
607}
608
85609c1c
MK		 609void dm646x_setup_vpif(struct vpif_display_config *display_config,
610 struct vpif_capture_config *capture_config)
611{
612 unsigned int value;
85609c1c 613
5cfb19ac 614 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
85609c1c 615 value &= ~VSCLKDIS_MASK;
5cfb19ac 616 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
85609c1c 617
5cfb19ac 618 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
85609c1c 619 value &= ~VDD3P3V_VID_MASK;
5cfb19ac 620 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
85609c1c
MK		 621
622 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
623 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
624 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
625 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
626
627 vpif_display_dev.dev.platform_data = display_config;
628 vpif_capture_dev.dev.platform_data = capture_config;
629 platform_device_register(&vpif_dev);
630 platform_device_register(&vpif_display_dev);
631 platform_device_register(&vpif_capture_dev);
632}
633
cce3dddb
RS		 634int __init dm646x_init_edma(struct edma_rsv_info *rsv)
635{
7ab388e8
PU		 636 struct platform_device *edma_pdev;
637
d4cb7f40 638 dm646x_edma_pdata.rsv = rsv;
cce3dddb 639
7ab388e8 640 edma_pdev = platform_device_register_full(&dm646x_edma_device);
a8bc4f0a 641 return PTR_ERR_OR_ZERO(edma_pdev);
cce3dddb
RS		 642}
643
e38d92fd
KH		 644void __init dm646x_init(void)
645{
79c3c0b7 646 davinci_common_init(&davinci_soc_info_dm646x);
5cfb19ac 647 davinci_map_sysmod();
96c08173
DL		 648}
649
650void __init dm646x_init_time(unsigned long ref_clk_rate,
651 unsigned long aux_clkin_rate)
652{
81df7d85
DL		 653 void __iomem *pll1, *psc;
654 struct clk *clk;
655
656 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
657 clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
658
659 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
660 dm646x_pll1_init(NULL, pll1, NULL);
661
662 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
663 dm646x_psc_init(NULL, psc);
664
665 clk = clk_get(NULL, "timer0");
666
667 davinci_timer_init(clk);
81df7d85
DL		 668}
669
670static struct resource dm646x_pll2_resources[] = {
671 {
672 .start = DAVINCI_PLL2_BASE,
673 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
674 .flags = IORESOURCE_MEM,
675 },
676};
677
678static struct platform_device dm646x_pll2_device = {
679 .name = "dm646x-pll2",
680 .id = -1,
681 .resource = dm646x_pll2_resources,
682 .num_resources = ARRAY_SIZE(dm646x_pll2_resources),
683};
684
685void __init dm646x_register_clocks(void)
686{
687 /* PLL1 and PSC are registered in dm646x_init_time() */
688 platform_device_register(&dm646x_pll2_device);
e38d92fd
KH		 689}
690
fd0f4275
BG		 691static const struct davinci_aintc_config dm646x_aintc_config = {
692 .reg = {
693 .start = DAVINCI_ARM_INTC_BASE,
694 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
695 .flags = IORESOURCE_MEM,
696 },
697 .num_irqs = 64,
698 .prios = dm646x_default_priorities,
699};
700
de4f82a2
BG		 701void __init dm646x_init_irq(void)
702{
06a28716 703 davinci_aintc_init(&dm646x_aintc_config);
de4f82a2
BG		 704}
705
e38d92fd
KH		 706static int __init dm646x_init_devices(void)
707{
1233090c
SN		 708 int ret = 0;
709
e38d92fd
KH		 710 if (!cpu_is_davinci_dm646x())
711 return 0;
712
d22960c8 713 platform_device_register(&dm646x_mdio_device);
972412b6 714 platform_device_register(&dm646x_emac_device);
d22960c8 715
1233090c
SN		 716 ret = davinci_init_wdt();
717 if (ret)
718 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
719
720 return ret;
e38d92fd
KH		 721}
722postcore_initcall(dm646x_init_devices);
Linux 6.x block layer and io_uring tree(s)