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e38d92fd KH |
1 | /* |
2 | * TI DaVinci DM644x chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
e38d92fd KH |
11 | #include <linux/init.h> |
12 | #include <linux/clk.h> | |
65e866a9 | 13 | #include <linux/serial_8250.h> |
e38d92fd | 14 | #include <linux/platform_device.h> |
a994955c | 15 | #include <linux/gpio.h> |
e38d92fd | 16 | |
79c3c0b7 MG |
17 | #include <asm/mach/map.h> |
18 | ||
e38d92fd | 19 | #include <mach/dm646x.h> |
e38d92fd KH |
20 | #include <mach/cputype.h> |
21 | #include <mach/edma.h> | |
22 | #include <mach/irqs.h> | |
23 | #include <mach/psc.h> | |
24 | #include <mach/mux.h> | |
f64691b3 | 25 | #include <mach/time.h> |
65e866a9 | 26 | #include <mach/serial.h> |
79c3c0b7 | 27 | #include <mach/common.h> |
25acf553 | 28 | #include <mach/asp.h> |
e38d92fd KH |
29 | |
30 | #include "clock.h" | |
31 | #include "mux.h" | |
32 | ||
85609c1c MK |
33 | #define DAVINCI_VPIF_BASE (0x01C12000) |
34 | #define VDD3P3V_PWDN_OFFSET (0x48) | |
35 | #define VSCLKDIS_OFFSET (0x6C) | |
36 | ||
37 | #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ | |
38 | BIT_MASK(0)) | |
39 | #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ | |
40 | BIT_MASK(8)) | |
41 | ||
e38d92fd KH |
42 | /* |
43 | * Device specific clocks | |
44 | */ | |
e38d92fd KH |
45 | #define DM646X_AUX_FREQ 24000000 |
46 | ||
47 | static struct pll_data pll1_data = { | |
48 | .num = 1, | |
49 | .phys_base = DAVINCI_PLL1_BASE, | |
50 | }; | |
51 | ||
52 | static struct pll_data pll2_data = { | |
53 | .num = 2, | |
54 | .phys_base = DAVINCI_PLL2_BASE, | |
55 | }; | |
56 | ||
57 | static struct clk ref_clk = { | |
58 | .name = "ref_clk", | |
e38d92fd KH |
59 | }; |
60 | ||
61 | static struct clk aux_clkin = { | |
62 | .name = "aux_clkin", | |
63 | .rate = DM646X_AUX_FREQ, | |
64 | }; | |
65 | ||
66 | static struct clk pll1_clk = { | |
67 | .name = "pll1", | |
68 | .parent = &ref_clk, | |
69 | .pll_data = &pll1_data, | |
70 | .flags = CLK_PLL, | |
71 | }; | |
72 | ||
73 | static struct clk pll1_sysclk1 = { | |
74 | .name = "pll1_sysclk1", | |
75 | .parent = &pll1_clk, | |
76 | .flags = CLK_PLL, | |
77 | .div_reg = PLLDIV1, | |
78 | }; | |
79 | ||
80 | static struct clk pll1_sysclk2 = { | |
81 | .name = "pll1_sysclk2", | |
82 | .parent = &pll1_clk, | |
83 | .flags = CLK_PLL, | |
84 | .div_reg = PLLDIV2, | |
85 | }; | |
86 | ||
87 | static struct clk pll1_sysclk3 = { | |
88 | .name = "pll1_sysclk3", | |
89 | .parent = &pll1_clk, | |
90 | .flags = CLK_PLL, | |
91 | .div_reg = PLLDIV3, | |
92 | }; | |
93 | ||
94 | static struct clk pll1_sysclk4 = { | |
95 | .name = "pll1_sysclk4", | |
96 | .parent = &pll1_clk, | |
97 | .flags = CLK_PLL, | |
98 | .div_reg = PLLDIV4, | |
99 | }; | |
100 | ||
101 | static struct clk pll1_sysclk5 = { | |
102 | .name = "pll1_sysclk5", | |
103 | .parent = &pll1_clk, | |
104 | .flags = CLK_PLL, | |
105 | .div_reg = PLLDIV5, | |
106 | }; | |
107 | ||
108 | static struct clk pll1_sysclk6 = { | |
109 | .name = "pll1_sysclk6", | |
110 | .parent = &pll1_clk, | |
111 | .flags = CLK_PLL, | |
112 | .div_reg = PLLDIV6, | |
113 | }; | |
114 | ||
115 | static struct clk pll1_sysclk8 = { | |
116 | .name = "pll1_sysclk8", | |
117 | .parent = &pll1_clk, | |
118 | .flags = CLK_PLL, | |
119 | .div_reg = PLLDIV8, | |
120 | }; | |
121 | ||
122 | static struct clk pll1_sysclk9 = { | |
123 | .name = "pll1_sysclk9", | |
124 | .parent = &pll1_clk, | |
125 | .flags = CLK_PLL, | |
126 | .div_reg = PLLDIV9, | |
127 | }; | |
128 | ||
129 | static struct clk pll1_sysclkbp = { | |
130 | .name = "pll1_sysclkbp", | |
131 | .parent = &pll1_clk, | |
132 | .flags = CLK_PLL | PRE_PLL, | |
133 | .div_reg = BPDIV, | |
134 | }; | |
135 | ||
136 | static struct clk pll1_aux_clk = { | |
137 | .name = "pll1_aux_clk", | |
138 | .parent = &pll1_clk, | |
139 | .flags = CLK_PLL | PRE_PLL, | |
140 | }; | |
141 | ||
142 | static struct clk pll2_clk = { | |
143 | .name = "pll2_clk", | |
144 | .parent = &ref_clk, | |
145 | .pll_data = &pll2_data, | |
146 | .flags = CLK_PLL, | |
147 | }; | |
148 | ||
149 | static struct clk pll2_sysclk1 = { | |
150 | .name = "pll2_sysclk1", | |
151 | .parent = &pll2_clk, | |
152 | .flags = CLK_PLL, | |
153 | .div_reg = PLLDIV1, | |
154 | }; | |
155 | ||
156 | static struct clk dsp_clk = { | |
157 | .name = "dsp", | |
158 | .parent = &pll1_sysclk1, | |
159 | .lpsc = DM646X_LPSC_C64X_CPU, | |
160 | .flags = PSC_DSP, | |
161 | .usecount = 1, /* REVISIT how to disable? */ | |
162 | }; | |
163 | ||
164 | static struct clk arm_clk = { | |
165 | .name = "arm", | |
166 | .parent = &pll1_sysclk2, | |
167 | .lpsc = DM646X_LPSC_ARM, | |
168 | .flags = ALWAYS_ENABLED, | |
169 | }; | |
170 | ||
2bcb613a SR |
171 | static struct clk edma_cc_clk = { |
172 | .name = "edma_cc", | |
173 | .parent = &pll1_sysclk2, | |
174 | .lpsc = DM646X_LPSC_TPCC, | |
175 | .flags = ALWAYS_ENABLED, | |
176 | }; | |
177 | ||
178 | static struct clk edma_tc0_clk = { | |
179 | .name = "edma_tc0", | |
180 | .parent = &pll1_sysclk2, | |
181 | .lpsc = DM646X_LPSC_TPTC0, | |
182 | .flags = ALWAYS_ENABLED, | |
183 | }; | |
184 | ||
185 | static struct clk edma_tc1_clk = { | |
186 | .name = "edma_tc1", | |
187 | .parent = &pll1_sysclk2, | |
188 | .lpsc = DM646X_LPSC_TPTC1, | |
189 | .flags = ALWAYS_ENABLED, | |
190 | }; | |
191 | ||
192 | static struct clk edma_tc2_clk = { | |
193 | .name = "edma_tc2", | |
194 | .parent = &pll1_sysclk2, | |
195 | .lpsc = DM646X_LPSC_TPTC2, | |
196 | .flags = ALWAYS_ENABLED, | |
197 | }; | |
198 | ||
199 | static struct clk edma_tc3_clk = { | |
200 | .name = "edma_tc3", | |
201 | .parent = &pll1_sysclk2, | |
202 | .lpsc = DM646X_LPSC_TPTC3, | |
203 | .flags = ALWAYS_ENABLED, | |
204 | }; | |
205 | ||
e38d92fd KH |
206 | static struct clk uart0_clk = { |
207 | .name = "uart0", | |
208 | .parent = &aux_clkin, | |
209 | .lpsc = DM646X_LPSC_UART0, | |
210 | }; | |
211 | ||
212 | static struct clk uart1_clk = { | |
213 | .name = "uart1", | |
214 | .parent = &aux_clkin, | |
215 | .lpsc = DM646X_LPSC_UART1, | |
216 | }; | |
217 | ||
218 | static struct clk uart2_clk = { | |
219 | .name = "uart2", | |
220 | .parent = &aux_clkin, | |
221 | .lpsc = DM646X_LPSC_UART2, | |
222 | }; | |
223 | ||
224 | static struct clk i2c_clk = { | |
225 | .name = "I2CCLK", | |
226 | .parent = &pll1_sysclk3, | |
227 | .lpsc = DM646X_LPSC_I2C, | |
228 | }; | |
229 | ||
230 | static struct clk gpio_clk = { | |
231 | .name = "gpio", | |
232 | .parent = &pll1_sysclk3, | |
233 | .lpsc = DM646X_LPSC_GPIO, | |
234 | }; | |
235 | ||
75d0fa70 C |
236 | static struct clk mcasp0_clk = { |
237 | .name = "mcasp0", | |
238 | .parent = &pll1_sysclk3, | |
239 | .lpsc = DM646X_LPSC_McASP0, | |
240 | }; | |
241 | ||
242 | static struct clk mcasp1_clk = { | |
243 | .name = "mcasp1", | |
244 | .parent = &pll1_sysclk3, | |
245 | .lpsc = DM646X_LPSC_McASP1, | |
246 | }; | |
247 | ||
e38d92fd KH |
248 | static struct clk aemif_clk = { |
249 | .name = "aemif", | |
250 | .parent = &pll1_sysclk3, | |
251 | .lpsc = DM646X_LPSC_AEMIF, | |
252 | .flags = ALWAYS_ENABLED, | |
253 | }; | |
254 | ||
255 | static struct clk emac_clk = { | |
256 | .name = "emac", | |
257 | .parent = &pll1_sysclk3, | |
258 | .lpsc = DM646X_LPSC_EMAC, | |
259 | }; | |
260 | ||
261 | static struct clk pwm0_clk = { | |
262 | .name = "pwm0", | |
263 | .parent = &pll1_sysclk3, | |
264 | .lpsc = DM646X_LPSC_PWM0, | |
265 | .usecount = 1, /* REVIST: disabling hangs system */ | |
266 | }; | |
267 | ||
268 | static struct clk pwm1_clk = { | |
269 | .name = "pwm1", | |
270 | .parent = &pll1_sysclk3, | |
271 | .lpsc = DM646X_LPSC_PWM1, | |
272 | .usecount = 1, /* REVIST: disabling hangs system */ | |
273 | }; | |
274 | ||
275 | static struct clk timer0_clk = { | |
276 | .name = "timer0", | |
277 | .parent = &pll1_sysclk3, | |
278 | .lpsc = DM646X_LPSC_TIMER0, | |
279 | }; | |
280 | ||
281 | static struct clk timer1_clk = { | |
282 | .name = "timer1", | |
283 | .parent = &pll1_sysclk3, | |
284 | .lpsc = DM646X_LPSC_TIMER1, | |
285 | }; | |
286 | ||
287 | static struct clk timer2_clk = { | |
288 | .name = "timer2", | |
289 | .parent = &pll1_sysclk3, | |
290 | .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ | |
291 | }; | |
292 | ||
3e25d5f4 HP |
293 | |
294 | static struct clk ide_clk = { | |
295 | .name = "ide", | |
296 | .parent = &pll1_sysclk4, | |
297 | .lpsc = DAVINCI_LPSC_ATA, | |
298 | }; | |
299 | ||
e38d92fd KH |
300 | static struct clk vpif0_clk = { |
301 | .name = "vpif0", | |
302 | .parent = &ref_clk, | |
303 | .lpsc = DM646X_LPSC_VPSSMSTR, | |
304 | .flags = ALWAYS_ENABLED, | |
305 | }; | |
306 | ||
307 | static struct clk vpif1_clk = { | |
308 | .name = "vpif1", | |
309 | .parent = &ref_clk, | |
310 | .lpsc = DM646X_LPSC_VPSSSLV, | |
311 | .flags = ALWAYS_ENABLED, | |
312 | }; | |
313 | ||
28552c2e | 314 | static struct clk_lookup dm646x_clks[] = { |
e38d92fd KH |
315 | CLK(NULL, "ref", &ref_clk), |
316 | CLK(NULL, "aux", &aux_clkin), | |
317 | CLK(NULL, "pll1", &pll1_clk), | |
318 | CLK(NULL, "pll1_sysclk", &pll1_sysclk1), | |
319 | CLK(NULL, "pll1_sysclk", &pll1_sysclk2), | |
320 | CLK(NULL, "pll1_sysclk", &pll1_sysclk3), | |
321 | CLK(NULL, "pll1_sysclk", &pll1_sysclk4), | |
322 | CLK(NULL, "pll1_sysclk", &pll1_sysclk5), | |
323 | CLK(NULL, "pll1_sysclk", &pll1_sysclk6), | |
324 | CLK(NULL, "pll1_sysclk", &pll1_sysclk8), | |
325 | CLK(NULL, "pll1_sysclk", &pll1_sysclk9), | |
326 | CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), | |
327 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
328 | CLK(NULL, "pll2", &pll2_clk), | |
329 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | |
330 | CLK(NULL, "dsp", &dsp_clk), | |
331 | CLK(NULL, "arm", &arm_clk), | |
2bcb613a SR |
332 | CLK(NULL, "edma_cc", &edma_cc_clk), |
333 | CLK(NULL, "edma_tc0", &edma_tc0_clk), | |
334 | CLK(NULL, "edma_tc1", &edma_tc1_clk), | |
335 | CLK(NULL, "edma_tc2", &edma_tc2_clk), | |
336 | CLK(NULL, "edma_tc3", &edma_tc3_clk), | |
e38d92fd KH |
337 | CLK(NULL, "uart0", &uart0_clk), |
338 | CLK(NULL, "uart1", &uart1_clk), | |
339 | CLK(NULL, "uart2", &uart2_clk), | |
340 | CLK("i2c_davinci.1", NULL, &i2c_clk), | |
341 | CLK(NULL, "gpio", &gpio_clk), | |
61aa0732 KH |
342 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), |
343 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), | |
e38d92fd KH |
344 | CLK(NULL, "aemif", &aemif_clk), |
345 | CLK("davinci_emac.1", NULL, &emac_clk), | |
346 | CLK(NULL, "pwm0", &pwm0_clk), | |
347 | CLK(NULL, "pwm1", &pwm1_clk), | |
348 | CLK(NULL, "timer0", &timer0_clk), | |
349 | CLK(NULL, "timer1", &timer1_clk), | |
350 | CLK("watchdog", NULL, &timer2_clk), | |
3e25d5f4 | 351 | CLK("palm_bk3710", NULL, &ide_clk), |
e38d92fd KH |
352 | CLK(NULL, "vpif0", &vpif0_clk), |
353 | CLK(NULL, "vpif1", &vpif1_clk), | |
354 | CLK(NULL, NULL, NULL), | |
355 | }; | |
356 | ||
972412b6 MG |
357 | static struct emac_platform_data dm646x_emac_pdata = { |
358 | .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, | |
359 | .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, | |
360 | .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, | |
361 | .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, | |
362 | .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, | |
363 | .version = EMAC_VERSION_2, | |
364 | }; | |
365 | ||
ac7b75b5 KH |
366 | static struct resource dm646x_emac_resources[] = { |
367 | { | |
368 | .start = DM646X_EMAC_BASE, | |
369 | .end = DM646X_EMAC_BASE + 0x47ff, | |
370 | .flags = IORESOURCE_MEM, | |
371 | }, | |
372 | { | |
373 | .start = IRQ_DM646X_EMACRXTHINT, | |
374 | .end = IRQ_DM646X_EMACRXTHINT, | |
375 | .flags = IORESOURCE_IRQ, | |
376 | }, | |
377 | { | |
378 | .start = IRQ_DM646X_EMACRXINT, | |
379 | .end = IRQ_DM646X_EMACRXINT, | |
380 | .flags = IORESOURCE_IRQ, | |
381 | }, | |
382 | { | |
383 | .start = IRQ_DM646X_EMACTXINT, | |
384 | .end = IRQ_DM646X_EMACTXINT, | |
385 | .flags = IORESOURCE_IRQ, | |
386 | }, | |
387 | { | |
388 | .start = IRQ_DM646X_EMACMISCINT, | |
389 | .end = IRQ_DM646X_EMACMISCINT, | |
390 | .flags = IORESOURCE_IRQ, | |
391 | }, | |
392 | }; | |
393 | ||
394 | static struct platform_device dm646x_emac_device = { | |
395 | .name = "davinci_emac", | |
396 | .id = 1, | |
972412b6 MG |
397 | .dev = { |
398 | .platform_data = &dm646x_emac_pdata, | |
399 | }, | |
ac7b75b5 KH |
400 | .num_resources = ARRAY_SIZE(dm646x_emac_resources), |
401 | .resource = dm646x_emac_resources, | |
402 | }; | |
403 | ||
e38d92fd KH |
404 | /* |
405 | * Device specific mux setup | |
406 | * | |
407 | * soc description mux mode mode mux dbg | |
408 | * reg offset mask mode | |
409 | */ | |
410 | static const struct mux_config dm646x_pins[] = { | |
0e585952 | 411 | #ifdef CONFIG_DAVINCI_MUX |
3e25d5f4 | 412 | MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) |
e38d92fd KH |
413 | |
414 | MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) | |
415 | ||
416 | MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) | |
417 | ||
418 | MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) | |
419 | ||
420 | MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) | |
421 | ||
422 | MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) | |
423 | ||
424 | MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) | |
425 | ||
426 | MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) | |
427 | ||
428 | MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) | |
429 | ||
430 | MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) | |
431 | ||
432 | MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) | |
433 | ||
434 | MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) | |
435 | ||
436 | MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) | |
437 | ||
438 | MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) | |
0e585952 | 439 | #endif |
e38d92fd KH |
440 | }; |
441 | ||
673dd36f MG |
442 | static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { |
443 | [IRQ_DM646X_VP_VERTINT0] = 7, | |
444 | [IRQ_DM646X_VP_VERTINT1] = 7, | |
445 | [IRQ_DM646X_VP_VERTINT2] = 7, | |
446 | [IRQ_DM646X_VP_VERTINT3] = 7, | |
447 | [IRQ_DM646X_VP_ERRINT] = 7, | |
448 | [IRQ_DM646X_RESERVED_1] = 7, | |
449 | [IRQ_DM646X_RESERVED_2] = 7, | |
450 | [IRQ_DM646X_WDINT] = 7, | |
451 | [IRQ_DM646X_CRGENINT0] = 7, | |
452 | [IRQ_DM646X_CRGENINT1] = 7, | |
453 | [IRQ_DM646X_TSIFINT0] = 7, | |
454 | [IRQ_DM646X_TSIFINT1] = 7, | |
455 | [IRQ_DM646X_VDCEINT] = 7, | |
456 | [IRQ_DM646X_USBINT] = 7, | |
457 | [IRQ_DM646X_USBDMAINT] = 7, | |
458 | [IRQ_DM646X_PCIINT] = 7, | |
459 | [IRQ_CCINT0] = 7, /* dma */ | |
460 | [IRQ_CCERRINT] = 7, /* dma */ | |
461 | [IRQ_TCERRINT0] = 7, /* dma */ | |
462 | [IRQ_TCERRINT] = 7, /* dma */ | |
463 | [IRQ_DM646X_TCERRINT2] = 7, | |
464 | [IRQ_DM646X_TCERRINT3] = 7, | |
465 | [IRQ_DM646X_IDE] = 7, | |
466 | [IRQ_DM646X_HPIINT] = 7, | |
467 | [IRQ_DM646X_EMACRXTHINT] = 7, | |
468 | [IRQ_DM646X_EMACRXINT] = 7, | |
469 | [IRQ_DM646X_EMACTXINT] = 7, | |
470 | [IRQ_DM646X_EMACMISCINT] = 7, | |
471 | [IRQ_DM646X_MCASP0TXINT] = 7, | |
472 | [IRQ_DM646X_MCASP0RXINT] = 7, | |
473 | [IRQ_AEMIFINT] = 7, | |
474 | [IRQ_DM646X_RESERVED_3] = 7, | |
475 | [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ | |
476 | [IRQ_TINT0_TINT34] = 7, /* clocksource */ | |
477 | [IRQ_TINT1_TINT12] = 7, /* DSP timer */ | |
478 | [IRQ_TINT1_TINT34] = 7, /* system tick */ | |
479 | [IRQ_PWMINT0] = 7, | |
480 | [IRQ_PWMINT1] = 7, | |
481 | [IRQ_DM646X_VLQINT] = 7, | |
482 | [IRQ_I2C] = 7, | |
483 | [IRQ_UARTINT0] = 7, | |
484 | [IRQ_UARTINT1] = 7, | |
485 | [IRQ_DM646X_UARTINT2] = 7, | |
486 | [IRQ_DM646X_SPINT0] = 7, | |
487 | [IRQ_DM646X_SPINT1] = 7, | |
488 | [IRQ_DM646X_DSP2ARMINT] = 7, | |
489 | [IRQ_DM646X_RESERVED_4] = 7, | |
490 | [IRQ_DM646X_PSCINT] = 7, | |
491 | [IRQ_DM646X_GPIO0] = 7, | |
492 | [IRQ_DM646X_GPIO1] = 7, | |
493 | [IRQ_DM646X_GPIO2] = 7, | |
494 | [IRQ_DM646X_GPIO3] = 7, | |
495 | [IRQ_DM646X_GPIO4] = 7, | |
496 | [IRQ_DM646X_GPIO5] = 7, | |
497 | [IRQ_DM646X_GPIO6] = 7, | |
498 | [IRQ_DM646X_GPIO7] = 7, | |
499 | [IRQ_DM646X_GPIOBNK0] = 7, | |
500 | [IRQ_DM646X_GPIOBNK1] = 7, | |
501 | [IRQ_DM646X_GPIOBNK2] = 7, | |
502 | [IRQ_DM646X_DDRINT] = 7, | |
503 | [IRQ_DM646X_AEMIFINT] = 7, | |
504 | [IRQ_COMMTX] = 7, | |
505 | [IRQ_COMMRX] = 7, | |
506 | [IRQ_EMUINT] = 7, | |
507 | }; | |
508 | ||
e38d92fd KH |
509 | /*----------------------------------------------------------------------*/ |
510 | ||
60902a2c SR |
511 | /* Four Transfer Controllers on DM646x */ |
512 | static const s8 | |
513 | dm646x_queue_tc_mapping[][2] = { | |
514 | /* {event queue no, TC no} */ | |
515 | {0, 0}, | |
516 | {1, 1}, | |
517 | {2, 2}, | |
518 | {3, 3}, | |
519 | {-1, -1}, | |
520 | }; | |
521 | ||
522 | static const s8 | |
523 | dm646x_queue_priority_mapping[][2] = { | |
524 | /* {event queue no, Priority} */ | |
525 | {0, 4}, | |
526 | {1, 0}, | |
527 | {2, 5}, | |
528 | {3, 1}, | |
529 | {-1, -1}, | |
530 | }; | |
531 | ||
532 | static struct edma_soc_info dm646x_edma_info[] = { | |
533 | { | |
534 | .n_channel = 64, | |
535 | .n_region = 6, /* 0-1, 4-7 */ | |
536 | .n_slot = 512, | |
537 | .n_tc = 4, | |
538 | .n_cc = 1, | |
60902a2c SR |
539 | .queue_tc_mapping = dm646x_queue_tc_mapping, |
540 | .queue_priority_mapping = dm646x_queue_priority_mapping, | |
541 | }, | |
e38d92fd KH |
542 | }; |
543 | ||
544 | static struct resource edma_resources[] = { | |
545 | { | |
60902a2c | 546 | .name = "edma_cc0", |
e38d92fd KH |
547 | .start = 0x01c00000, |
548 | .end = 0x01c00000 + SZ_64K - 1, | |
549 | .flags = IORESOURCE_MEM, | |
550 | }, | |
551 | { | |
552 | .name = "edma_tc0", | |
553 | .start = 0x01c10000, | |
554 | .end = 0x01c10000 + SZ_1K - 1, | |
555 | .flags = IORESOURCE_MEM, | |
556 | }, | |
557 | { | |
558 | .name = "edma_tc1", | |
559 | .start = 0x01c10400, | |
560 | .end = 0x01c10400 + SZ_1K - 1, | |
561 | .flags = IORESOURCE_MEM, | |
562 | }, | |
563 | { | |
564 | .name = "edma_tc2", | |
565 | .start = 0x01c10800, | |
566 | .end = 0x01c10800 + SZ_1K - 1, | |
567 | .flags = IORESOURCE_MEM, | |
568 | }, | |
569 | { | |
570 | .name = "edma_tc3", | |
571 | .start = 0x01c10c00, | |
572 | .end = 0x01c10c00 + SZ_1K - 1, | |
573 | .flags = IORESOURCE_MEM, | |
574 | }, | |
575 | { | |
60902a2c | 576 | .name = "edma0", |
e38d92fd KH |
577 | .start = IRQ_CCINT0, |
578 | .flags = IORESOURCE_IRQ, | |
579 | }, | |
580 | { | |
60902a2c | 581 | .name = "edma0_err", |
e38d92fd KH |
582 | .start = IRQ_CCERRINT, |
583 | .flags = IORESOURCE_IRQ, | |
584 | }, | |
585 | /* not using TC*_ERR */ | |
586 | }; | |
587 | ||
588 | static struct platform_device dm646x_edma_device = { | |
589 | .name = "edma", | |
60902a2c SR |
590 | .id = 0, |
591 | .dev.platform_data = dm646x_edma_info, | |
e38d92fd KH |
592 | .num_resources = ARRAY_SIZE(edma_resources), |
593 | .resource = edma_resources, | |
594 | }; | |
595 | ||
25acf553 C |
596 | static struct resource dm646x_mcasp0_resources[] = { |
597 | { | |
598 | .name = "mcasp0", | |
599 | .start = DAVINCI_DM646X_MCASP0_REG_BASE, | |
600 | .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, | |
601 | .flags = IORESOURCE_MEM, | |
602 | }, | |
603 | /* first TX, then RX */ | |
604 | { | |
605 | .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, | |
606 | .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, | |
607 | .flags = IORESOURCE_DMA, | |
608 | }, | |
609 | { | |
610 | .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, | |
611 | .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, | |
612 | .flags = IORESOURCE_DMA, | |
613 | }, | |
614 | }; | |
615 | ||
616 | static struct resource dm646x_mcasp1_resources[] = { | |
617 | { | |
618 | .name = "mcasp1", | |
619 | .start = DAVINCI_DM646X_MCASP1_REG_BASE, | |
620 | .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, | |
621 | .flags = IORESOURCE_MEM, | |
622 | }, | |
623 | /* DIT mode, only TX event */ | |
624 | { | |
625 | .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, | |
626 | .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, | |
627 | .flags = IORESOURCE_DMA, | |
628 | }, | |
629 | /* DIT mode, dummy entry */ | |
630 | { | |
631 | .start = -1, | |
632 | .end = -1, | |
633 | .flags = IORESOURCE_DMA, | |
634 | }, | |
635 | }; | |
636 | ||
637 | static struct platform_device dm646x_mcasp0_device = { | |
638 | .name = "davinci-mcasp", | |
639 | .id = 0, | |
640 | .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), | |
641 | .resource = dm646x_mcasp0_resources, | |
642 | }; | |
643 | ||
644 | static struct platform_device dm646x_mcasp1_device = { | |
645 | .name = "davinci-mcasp", | |
646 | .id = 1, | |
647 | .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), | |
648 | .resource = dm646x_mcasp1_resources, | |
649 | }; | |
650 | ||
651 | static struct platform_device dm646x_dit_device = { | |
652 | .name = "spdif-dit", | |
653 | .id = -1, | |
654 | }; | |
655 | ||
85609c1c MK |
656 | static u64 vpif_dma_mask = DMA_BIT_MASK(32); |
657 | ||
658 | static struct resource vpif_resource[] = { | |
659 | { | |
660 | .start = DAVINCI_VPIF_BASE, | |
661 | .end = DAVINCI_VPIF_BASE + 0x03ff, | |
662 | .flags = IORESOURCE_MEM, | |
663 | } | |
664 | }; | |
665 | ||
666 | static struct platform_device vpif_dev = { | |
667 | .name = "vpif", | |
668 | .id = -1, | |
669 | .dev = { | |
670 | .dma_mask = &vpif_dma_mask, | |
671 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
672 | }, | |
673 | .resource = vpif_resource, | |
674 | .num_resources = ARRAY_SIZE(vpif_resource), | |
675 | }; | |
676 | ||
677 | static struct resource vpif_display_resource[] = { | |
678 | { | |
679 | .start = IRQ_DM646X_VP_VERTINT2, | |
680 | .end = IRQ_DM646X_VP_VERTINT2, | |
681 | .flags = IORESOURCE_IRQ, | |
682 | }, | |
683 | { | |
684 | .start = IRQ_DM646X_VP_VERTINT3, | |
685 | .end = IRQ_DM646X_VP_VERTINT3, | |
686 | .flags = IORESOURCE_IRQ, | |
687 | }, | |
688 | }; | |
689 | ||
690 | static struct platform_device vpif_display_dev = { | |
691 | .name = "vpif_display", | |
692 | .id = -1, | |
693 | .dev = { | |
694 | .dma_mask = &vpif_dma_mask, | |
695 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
696 | }, | |
697 | .resource = vpif_display_resource, | |
698 | .num_resources = ARRAY_SIZE(vpif_display_resource), | |
699 | }; | |
700 | ||
701 | static struct resource vpif_capture_resource[] = { | |
702 | { | |
703 | .start = IRQ_DM646X_VP_VERTINT0, | |
704 | .end = IRQ_DM646X_VP_VERTINT0, | |
705 | .flags = IORESOURCE_IRQ, | |
706 | }, | |
707 | { | |
708 | .start = IRQ_DM646X_VP_VERTINT1, | |
709 | .end = IRQ_DM646X_VP_VERTINT1, | |
710 | .flags = IORESOURCE_IRQ, | |
711 | }, | |
712 | }; | |
713 | ||
714 | static struct platform_device vpif_capture_dev = { | |
715 | .name = "vpif_capture", | |
716 | .id = -1, | |
717 | .dev = { | |
718 | .dma_mask = &vpif_dma_mask, | |
719 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
720 | }, | |
721 | .resource = vpif_capture_resource, | |
722 | .num_resources = ARRAY_SIZE(vpif_capture_resource), | |
723 | }; | |
724 | ||
e38d92fd KH |
725 | /*----------------------------------------------------------------------*/ |
726 | ||
79c3c0b7 MG |
727 | static struct map_desc dm646x_io_desc[] = { |
728 | { | |
729 | .virtual = IO_VIRT, | |
730 | .pfn = __phys_to_pfn(IO_PHYS), | |
731 | .length = IO_SIZE, | |
732 | .type = MT_DEVICE | |
733 | }, | |
0d04eb47 DB |
734 | { |
735 | .virtual = SRAM_VIRT, | |
736 | .pfn = __phys_to_pfn(0x00010000), | |
737 | .length = SZ_32K, | |
738 | /* MT_MEMORY_NONCACHED requires supersection alignment */ | |
739 | .type = MT_DEVICE, | |
740 | }, | |
79c3c0b7 MG |
741 | }; |
742 | ||
b9ab1279 MG |
743 | /* Contents of JTAG ID register used to identify exact cpu type */ |
744 | static struct davinci_id dm646x_ids[] = { | |
745 | { | |
746 | .variant = 0x0, | |
747 | .part_no = 0xb770, | |
748 | .manufacturer = 0x017, | |
749 | .cpu_id = DAVINCI_CPU_ID_DM6467, | |
f63dd12d HP |
750 | .name = "dm6467_rev1.x", |
751 | }, | |
752 | { | |
753 | .variant = 0x1, | |
754 | .part_no = 0xb770, | |
755 | .manufacturer = 0x017, | |
756 | .cpu_id = DAVINCI_CPU_ID_DM6467, | |
757 | .name = "dm6467_rev3.x", | |
b9ab1279 MG |
758 | }, |
759 | }; | |
760 | ||
e4c822c7 | 761 | static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; |
d81d188c | 762 | |
f64691b3 MG |
763 | /* |
764 | * T0_BOT: Timer 0, bottom: clockevent source for hrtimers | |
765 | * T0_TOP: Timer 0, top : clocksource for generic timekeeping | |
766 | * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) | |
767 | * T1_TOP: Timer 1, top : <unused> | |
768 | */ | |
28552c2e | 769 | static struct davinci_timer_info dm646x_timer_info = { |
f64691b3 MG |
770 | .timers = davinci_timer_instance, |
771 | .clockevent_id = T0_BOT, | |
772 | .clocksource_id = T0_TOP, | |
773 | }; | |
774 | ||
65e866a9 MG |
775 | static struct plat_serial8250_port dm646x_serial_platform_data[] = { |
776 | { | |
777 | .mapbase = DAVINCI_UART0_BASE, | |
778 | .irq = IRQ_UARTINT0, | |
779 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
780 | UPF_IOREMAP, | |
781 | .iotype = UPIO_MEM32, | |
782 | .regshift = 2, | |
783 | }, | |
784 | { | |
785 | .mapbase = DAVINCI_UART1_BASE, | |
786 | .irq = IRQ_UARTINT1, | |
787 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
788 | UPF_IOREMAP, | |
789 | .iotype = UPIO_MEM32, | |
790 | .regshift = 2, | |
791 | }, | |
792 | { | |
793 | .mapbase = DAVINCI_UART2_BASE, | |
794 | .irq = IRQ_DM646X_UARTINT2, | |
795 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
796 | UPF_IOREMAP, | |
797 | .iotype = UPIO_MEM32, | |
798 | .regshift = 2, | |
799 | }, | |
800 | { | |
801 | .flags = 0 | |
802 | }, | |
803 | }; | |
804 | ||
805 | static struct platform_device dm646x_serial_device = { | |
806 | .name = "serial8250", | |
807 | .id = PLAT8250_DEV_PLATFORM, | |
808 | .dev = { | |
809 | .platform_data = dm646x_serial_platform_data, | |
810 | }, | |
811 | }; | |
812 | ||
79c3c0b7 MG |
813 | static struct davinci_soc_info davinci_soc_info_dm646x = { |
814 | .io_desc = dm646x_io_desc, | |
815 | .io_desc_num = ARRAY_SIZE(dm646x_io_desc), | |
3347db83 | 816 | .jtag_id_reg = 0x01c40028, |
b9ab1279 MG |
817 | .ids = dm646x_ids, |
818 | .ids_num = ARRAY_SIZE(dm646x_ids), | |
66e0c399 | 819 | .cpu_clks = dm646x_clks, |
d81d188c MG |
820 | .psc_bases = dm646x_psc_bases, |
821 | .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), | |
779b0d53 | 822 | .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, |
0e585952 MG |
823 | .pinmux_pins = dm646x_pins, |
824 | .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), | |
bd808947 | 825 | .intc_base = DAVINCI_ARM_INTC_BASE, |
673dd36f MG |
826 | .intc_type = DAVINCI_INTC_TYPE_AINTC, |
827 | .intc_irq_prios = dm646x_default_priorities, | |
828 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | |
f64691b3 | 829 | .timer_info = &dm646x_timer_info, |
686b634a | 830 | .gpio_type = GPIO_TYPE_DAVINCI, |
b8d44293 | 831 | .gpio_base = DAVINCI_GPIO_BASE, |
a994955c MG |
832 | .gpio_num = 43, /* Only 33 usable */ |
833 | .gpio_irq = IRQ_DM646X_GPIOBNK0, | |
65e866a9 | 834 | .serial_dev = &dm646x_serial_device, |
972412b6 | 835 | .emac_pdata = &dm646x_emac_pdata, |
0d04eb47 DB |
836 | .sram_dma = 0x10010000, |
837 | .sram_len = SZ_32K, | |
c78a5bc2 | 838 | .reset_device = &davinci_wdt_device, |
79c3c0b7 MG |
839 | }; |
840 | ||
25acf553 C |
841 | void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) |
842 | { | |
843 | dm646x_mcasp0_device.dev.platform_data = pdata; | |
844 | platform_device_register(&dm646x_mcasp0_device); | |
845 | } | |
846 | ||
847 | void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) | |
848 | { | |
849 | dm646x_mcasp1_device.dev.platform_data = pdata; | |
850 | platform_device_register(&dm646x_mcasp1_device); | |
851 | platform_device_register(&dm646x_dit_device); | |
852 | } | |
853 | ||
85609c1c MK |
854 | void dm646x_setup_vpif(struct vpif_display_config *display_config, |
855 | struct vpif_capture_config *capture_config) | |
856 | { | |
857 | unsigned int value; | |
858 | void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); | |
859 | ||
860 | value = __raw_readl(base + VSCLKDIS_OFFSET); | |
861 | value &= ~VSCLKDIS_MASK; | |
862 | __raw_writel(value, base + VSCLKDIS_OFFSET); | |
863 | ||
864 | value = __raw_readl(base + VDD3P3V_PWDN_OFFSET); | |
865 | value &= ~VDD3P3V_VID_MASK; | |
866 | __raw_writel(value, base + VDD3P3V_PWDN_OFFSET); | |
867 | ||
868 | davinci_cfg_reg(DM646X_STSOMUX_DISABLE); | |
869 | davinci_cfg_reg(DM646X_STSIMUX_DISABLE); | |
870 | davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); | |
871 | davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); | |
872 | ||
873 | vpif_display_dev.dev.platform_data = display_config; | |
874 | vpif_capture_dev.dev.platform_data = capture_config; | |
875 | platform_device_register(&vpif_dev); | |
876 | platform_device_register(&vpif_display_dev); | |
877 | platform_device_register(&vpif_capture_dev); | |
878 | } | |
879 | ||
e38d92fd KH |
880 | void __init dm646x_init(void) |
881 | { | |
c1978e1d | 882 | dm646x_board_setup_refclk(&ref_clk); |
79c3c0b7 | 883 | davinci_common_init(&davinci_soc_info_dm646x); |
e38d92fd KH |
884 | } |
885 | ||
886 | static int __init dm646x_init_devices(void) | |
887 | { | |
888 | if (!cpu_is_davinci_dm646x()) | |
889 | return 0; | |
890 | ||
891 | platform_device_register(&dm646x_edma_device); | |
972412b6 | 892 | platform_device_register(&dm646x_emac_device); |
e38d92fd KH |
893 | return 0; |
894 | } | |
895 | postcore_initcall(dm646x_init_devices); |