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ARM: davinci: aintc: wrap davinci_irq_init() with a helper
[linux-2.6-block.git] / arch / arm / mach-davinci / dm644x.c
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d0e47fba
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
a5b1a871
DL		 11
12#include <linux/clk-provider.h>
13#include <linux/clk/davinci.h>
14#include <linux/clkdev.h>
a4f86c55 15#include <linux/dmaengine.h>
a5b1a871 16#include <linux/init.h>
3ad7a42d 17#include <linux/platform_data/edma.h>
9cc1515c 18#include <linux/platform_data/gpio-davinci.h>
a5b1a871
DL		 19#include <linux/platform_device.h>
20#include <linux/serial_8250.h>
d0e47fba 21
79c3c0b7
MG		 22#include <asm/mach/map.h>
23
a5b1a871 24#include <mach/common.h>
d0e47fba 25#include <mach/cputype.h>
d0e47fba 26#include <mach/mux.h>
65e866a9 27#include <mach/serial.h>
a5b1a871 28#include <mach/time.h>
d0e47fba 29
a5b1a871 30#include "asp.h"
39c6d2d1 31#include "davinci.h"
544ca0b0 32#include "irqs.h"
d0e47fba 33#include "mux.h"
a5b1a871 34
d0e47fba
KH		 35/*
36 * Device specific clocks
37 */
38#define DM644X_REF_FREQ 27000000
39
887b8a93
MH		 40#define DM644X_EMAC_BASE 0x01c80000
41#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
42#define DM644X_EMAC_CNTRL_OFFSET 0x0000
43#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
44#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
45#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
46
972412b6
MG		 47static struct emac_platform_data dm644x_emac_pdata = {
48 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
49 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
50 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 51 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
52 .version = EMAC_VERSION_1,
53};
d0e47fba
KH		 54
55static struct resource dm644x_emac_resources[] = {
56 {
57 .start = DM644X_EMAC_BASE,
d22960c8 58 .end = DM644X_EMAC_BASE + SZ_16K - 1,
d0e47fba
KH		 59 .flags = IORESOURCE_MEM,
60 },
61 {
a98ca73e
BG		 62 .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
63 .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
d0e47fba
KH		 64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct platform_device dm644x_emac_device = {
69 .name = "davinci_emac",
70 .id = 1,
972412b6
MG		 71 .dev = {
72 .platform_data = &dm644x_emac_pdata,
73 },
d0e47fba
KH		 74 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
75 .resource = dm644x_emac_resources,
76};
77
d22960c8
CC		 78static struct resource dm644x_mdio_resources[] = {
79 {
80 .start = DM644X_EMAC_MDIO_BASE,
81 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
82 .flags = IORESOURCE_MEM,
83 },
84};
85
86static struct platform_device dm644x_mdio_device = {
87 .name = "davinci_mdio",
88 .id = 0,
89 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
90 .resource = dm644x_mdio_resources,
91};
92
d0e47fba
KH		 93/*
94 * Device specific mux setup
95 *
96 * soc description mux mode mode mux dbg
97 * reg offset mask mode
98 */
99static const struct mux_config dm644x_pins[] = {
0e585952 100#ifdef CONFIG_DAVINCI_MUX
d0e47fba
KH		 101MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
102MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
103MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
104
105MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
106
107MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
c16fe267
AP		 108MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
109MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
110MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
111MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
112MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
d0e47fba
KH		 113
114MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
115
116MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
117
118MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
119
120MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
121MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
122
123MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
124
125MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
126
127MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
128
129MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
130MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
131MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
132
133MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
134
135MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
136
137MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
138MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
139MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
140MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
141
142MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
143
144MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
145MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
0e585952 146#endif
d0e47fba
KH		 147};
148
673dd36f
MG		 149/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
150static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
151 [IRQ_VDINT0] = 2,
152 [IRQ_VDINT1] = 6,
153 [IRQ_VDINT2] = 6,
154 [IRQ_HISTINT] = 6,
155 [IRQ_H3AINT] = 6,
156 [IRQ_PRVUINT] = 6,
157 [IRQ_RSZINT] = 6,
158 [7] = 7,
159 [IRQ_VENCINT] = 6,
160 [IRQ_ASQINT] = 6,
161 [IRQ_IMXINT] = 6,
162 [IRQ_VLCDINT] = 6,
163 [IRQ_USBINT] = 4,
164 [IRQ_EMACINT] = 4,
165 [14] = 7,
166 [15] = 7,
167 [IRQ_CCINT0] = 5, /* dma */
168 [IRQ_CCERRINT] = 5, /* dma */
169 [IRQ_TCERRINT0] = 5, /* dma */
170 [IRQ_TCERRINT] = 5, /* dma */
171 [IRQ_PSCIN] = 7,
172 [21] = 7,
173 [IRQ_IDE] = 4,
174 [23] = 7,
175 [IRQ_MBXINT] = 7,
176 [IRQ_MBRINT] = 7,
177 [IRQ_MMCINT] = 7,
178 [IRQ_SDIOINT] = 7,
179 [28] = 7,
180 [IRQ_DDRINT] = 7,
181 [IRQ_AEMIFINT] = 7,
182 [IRQ_VLQINT] = 4,
183 [IRQ_TINT0_TINT12] = 2, /* clockevent */
184 [IRQ_TINT0_TINT34] = 2, /* clocksource */
185 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
186 [IRQ_TINT1_TINT34] = 7, /* system tick */
187 [IRQ_PWMINT0] = 7,
188 [IRQ_PWMINT1] = 7,
189 [IRQ_PWMINT2] = 7,
190 [IRQ_I2C] = 3,
191 [IRQ_UARTINT0] = 3,
192 [IRQ_UARTINT1] = 3,
193 [IRQ_UARTINT2] = 3,
194 [IRQ_SPINT0] = 3,
195 [IRQ_SPINT1] = 3,
196 [45] = 7,
197 [IRQ_DSP2ARM0] = 4,
198 [IRQ_DSP2ARM1] = 4,
199 [IRQ_GPIO0] = 7,
200 [IRQ_GPIO1] = 7,
201 [IRQ_GPIO2] = 7,
202 [IRQ_GPIO3] = 7,
203 [IRQ_GPIO4] = 7,
204 [IRQ_GPIO5] = 7,
205 [IRQ_GPIO6] = 7,
206 [IRQ_GPIO7] = 7,
207 [IRQ_GPIOBNK0] = 7,
208 [IRQ_GPIOBNK1] = 7,
209 [IRQ_GPIOBNK2] = 7,
210 [IRQ_GPIOBNK3] = 7,
211 [IRQ_GPIOBNK4] = 7,
212 [IRQ_COMMTX] = 7,
213 [IRQ_COMMRX] = 7,
214 [IRQ_EMUINT] = 7,
215};
216
d0e47fba
KH		 217/*----------------------------------------------------------------------*/
218
d4cb7f40 219static s8 queue_priority_mapping[][2] = {
60902a2c
SR		 220 /* {event queue no, Priority} */
221 {0, 3},
222 {1, 7},
223 {-1, -1},
224};
225
a4f86c55
PU		 226static const struct dma_slave_map dm644x_edma_map[] = {
227 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
228 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
229 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
230 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
231 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
232 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
233};
234
d4cb7f40 235static struct edma_soc_info dm644x_edma_pdata = {
bc3ac9f3 236 .queue_priority_mapping = queue_priority_mapping,
f23fe857 237 .default_queue = EVENTQ_1,
a4f86c55
PU		 238 .slave_map = dm644x_edma_map,
239 .slavecnt = ARRAY_SIZE(dm644x_edma_map),
bc3ac9f3
SN		 240};
241
d0e47fba
KH		 242static struct resource edma_resources[] = {
243 {
d4cb7f40 244 .name = "edma3_cc",
d0e47fba
KH		 245 .start = 0x01c00000,
246 .end = 0x01c00000 + SZ_64K - 1,
247 .flags = IORESOURCE_MEM,
248 },
249 {
d4cb7f40 250 .name = "edma3_tc0",
d0e47fba
KH		 251 .start = 0x01c10000,
252 .end = 0x01c10000 + SZ_1K - 1,
253 .flags = IORESOURCE_MEM,
254 },
255 {
d4cb7f40 256 .name = "edma3_tc1",
d0e47fba
KH		 257 .start = 0x01c10400,
258 .end = 0x01c10400 + SZ_1K - 1,
259 .flags = IORESOURCE_MEM,
260 },
261 {
d4cb7f40 262 .name = "edma3_ccint",
a98ca73e 263 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
d0e47fba
KH		 264 .flags = IORESOURCE_IRQ,
265 },
266 {
d4cb7f40 267 .name = "edma3_ccerrint",
a98ca73e 268 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
d0e47fba
KH		 269 .flags = IORESOURCE_IRQ,
270 },
271 /* not using TC*_ERR */
272};
273
7ab388e8
PU		 274static const struct platform_device_info dm644x_edma_device __initconst = {
275 .name = "edma",
276 .id = 0,
cef5b0da 277 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 278 .res = edma_resources,
279 .num_res = ARRAY_SIZE(edma_resources),
280 .data = &dm644x_edma_pdata,
281 .size_data = sizeof(dm644x_edma_pdata),
d0e47fba
KH		 282};
283
25acf553
C		 284/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
285static struct resource dm644x_asp_resources[] = {
286 {
ee880dbd 287 .name = "mpu",
25acf553
C		 288 .start = DAVINCI_ASP0_BASE,
289 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
290 .flags = IORESOURCE_MEM,
291 },
292 {
293 .start = DAVINCI_DMA_ASP0_TX,
294 .end = DAVINCI_DMA_ASP0_TX,
295 .flags = IORESOURCE_DMA,
296 },
297 {
298 .start = DAVINCI_DMA_ASP0_RX,
299 .end = DAVINCI_DMA_ASP0_RX,
300 .flags = IORESOURCE_DMA,
301 },
302};
303
304static struct platform_device dm644x_asp_device = {
bedad0ca 305 .name = "davinci-mcbsp",
25acf553
C		 306 .id = -1,
307 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
308 .resource = dm644x_asp_resources,
309};
310
51f31cb3
MH		 311#define DM644X_VPSS_BASE 0x01c73400
312
ab8e8df8
MK		 313static struct resource dm644x_vpss_resources[] = {
314 {
315 /* VPSS Base address */
316 .name = "vpss",
51f31cb3
MH		 317 .start = DM644X_VPSS_BASE,
318 .end = DM644X_VPSS_BASE + 0xff,
319 .flags = IORESOURCE_MEM,
ab8e8df8
MK		 320 },
321};
322
323static struct platform_device dm644x_vpss_device = {
324 .name = "vpss",
325 .id = -1,
326 .dev.platform_data = "dm644x_vpss",
327 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
328 .resource = dm644x_vpss_resources,
329};
330
314d7389 331static struct resource dm644x_vpfe_resources[] = {
ab8e8df8 332 {
a98ca73e
BG		 333 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
334 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
ab8e8df8
MK		 335 .flags = IORESOURCE_IRQ,
336 },
337 {
a98ca73e
BG		 338 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
339 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
ab8e8df8
MK		 340 .flags = IORESOURCE_IRQ,
341 },
77c8b5fb
MK		 342};
343
af946f26 344static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
77c8b5fb
MK		 345static struct resource dm644x_ccdc_resource[] = {
346 /* CCDC Base address */
ab8e8df8
MK		 347 {
348 .start = 0x01c70400,
349 .end = 0x01c70400 + 0xff,
350 .flags = IORESOURCE_MEM,
351 },
352};
353
77c8b5fb
MK		 354static struct platform_device dm644x_ccdc_dev = {
355 .name = "dm644x_ccdc",
356 .id = -1,
357 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
358 .resource = dm644x_ccdc_resource,
359 .dev = {
af946f26 360 .dma_mask = &dm644x_video_dma_mask,
77c8b5fb
MK		 361 .coherent_dma_mask = DMA_BIT_MASK(32),
362 },
363};
364
314d7389 365static struct platform_device dm644x_vpfe_dev = {
ab8e8df8
MK		 366 .name = CAPTURE_DRV_NAME,
367 .id = -1,
314d7389
MH		 368 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
369 .resource = dm644x_vpfe_resources,
ab8e8df8 370 .dev = {
af946f26
MH		 371 .dma_mask = &dm644x_video_dma_mask,
372 .coherent_dma_mask = DMA_BIT_MASK(32),
373 },
374};
375
376#define DM644X_OSD_BASE 0x01c72600
377
378static struct resource dm644x_osd_resources[] = {
379 {
380 .start = DM644X_OSD_BASE,
381 .end = DM644X_OSD_BASE + 0x1ff,
382 .flags = IORESOURCE_MEM,
383 },
384};
385
af946f26 386static struct platform_device dm644x_osd_dev = {
caff80c3 387 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
af946f26
MH		 388 .id = -1,
389 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
390 .resource = dm644x_osd_resources,
391 .dev = {
392 .dma_mask = &dm644x_video_dma_mask,
393 .coherent_dma_mask = DMA_BIT_MASK(32),
af946f26
MH		 394 },
395};
396
397#define DM644X_VENC_BASE 0x01c72400
398
399static struct resource dm644x_venc_resources[] = {
400 {
401 .start = DM644X_VENC_BASE,
402 .end = DM644X_VENC_BASE + 0x17f,
403 .flags = IORESOURCE_MEM,
404 },
405};
406
407#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
408#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
409#define DM644X_VPSS_VENCLKEN BIT(3)
410#define DM644X_VPSS_DACCLKEN BIT(4)
411
412static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
36864082 413 unsigned int pclock)
af946f26
MH		 414{
415 int ret = 0;
416 u32 v = DM644X_VPSS_VENCLKEN;
417
418 switch (type) {
419 case VPBE_ENC_STD:
420 v |= DM644X_VPSS_DACCLKEN;
421 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
422 break;
ef2d41b1 423 case VPBE_ENC_DV_TIMINGS:
36864082 424 if (pclock <= 27000000) {
e37212aa 425 v |= DM644X_VPSS_DACCLKEN;
af946f26 426 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
36864082 427 } else {
af946f26
MH		 428 /*
429 * For HD, use external clock source since
430 * HD requires higher clock rate
431 */
432 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
433 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
af946f26
MH		 434 }
435 break;
436 default:
437 ret = -EINVAL;
438 }
439
440 return ret;
441}
442
443static struct resource dm644x_v4l2_disp_resources[] = {
444 {
a98ca73e
BG		 445 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
446 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
af946f26
MH		 447 .flags = IORESOURCE_IRQ,
448 },
449};
450
451static struct platform_device dm644x_vpbe_display = {
452 .name = "vpbe-v4l2",
453 .id = -1,
454 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
455 .resource = dm644x_v4l2_disp_resources,
456 .dev = {
457 .dma_mask = &dm644x_video_dma_mask,
458 .coherent_dma_mask = DMA_BIT_MASK(32),
459 },
460};
461
462static struct venc_platform_data dm644x_venc_pdata = {
af946f26
MH		 463 .setup_clock = dm644x_venc_setup_clock,
464};
465
466static struct platform_device dm644x_venc_dev = {
caff80c3 467 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
af946f26
MH		 468 .id = -1,
469 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
470 .resource = dm644x_venc_resources,
471 .dev = {
472 .dma_mask = &dm644x_video_dma_mask,
473 .coherent_dma_mask = DMA_BIT_MASK(32),
474 .platform_data = &dm644x_venc_pdata,
475 },
476};
477
478static struct platform_device dm644x_vpbe_dev = {
479 .name = "vpbe_controller",
480 .id = -1,
481 .dev = {
482 .dma_mask = &dm644x_video_dma_mask,
ab8e8df8
MK		 483 .coherent_dma_mask = DMA_BIT_MASK(32),
484 },
485};
486
9cc1515c
PA		 487static struct resource dm644_gpio_resources[] = {
488 { /* registers */
489 .start = DAVINCI_GPIO_BASE,
490 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
491 .flags = IORESOURCE_MEM,
492 },
493 { /* interrupt */
a98ca73e
BG		 494 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
495 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
adcf60ce
BG		 496 .flags = IORESOURCE_IRQ,
497 },
498 {
a98ca73e
BG		 499 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
500 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
adcf60ce
BG		 501 .flags = IORESOURCE_IRQ,
502 },
503 {
a98ca73e
BG		 504 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
505 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
adcf60ce
BG		 506 .flags = IORESOURCE_IRQ,
507 },
508 {
a98ca73e
BG		 509 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
510 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
adcf60ce
BG		 511 .flags = IORESOURCE_IRQ,
512 },
513 {
a98ca73e
BG		 514 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
515 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
9cc1515c
PA		 516 .flags = IORESOURCE_IRQ,
517 },
518};
519
520static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
27df7977
BG		 521 .no_auto_base = true,
522 .base = 0,
9cc1515c 523 .ngpio = 71,
9cc1515c
PA		 524};
525
526int __init dm644x_gpio_register(void)
527{
528 return davinci_gpio_register(dm644_gpio_resources,
e462f1f5 529 ARRAY_SIZE(dm644_gpio_resources),
9cc1515c
PA		 530 &dm644_gpio_platform_data);
531}
d0e47fba 532/*----------------------------------------------------------------------*/
ac7b75b5 533
79c3c0b7
MG		 534static struct map_desc dm644x_io_desc[] = {
535 {
536 .virtual = IO_VIRT,
537 .pfn = __phys_to_pfn(IO_PHYS),
538 .length = IO_SIZE,
539 .type = MT_DEVICE
540 },
541};
542
b9ab1279
MG		 543/* Contents of JTAG ID register used to identify exact cpu type */
544static struct davinci_id dm644x_ids[] = {
545 {
546 .variant = 0x0,
547 .part_no = 0xb700,
548 .manufacturer = 0x017,
549 .cpu_id = DAVINCI_CPU_ID_DM6446,
550 .name = "dm6446",
551 },
98d0e9fc
RS		 552 {
553 .variant = 0x1,
554 .part_no = 0xb700,
555 .manufacturer = 0x017,
556 .cpu_id = DAVINCI_CPU_ID_DM6446,
557 .name = "dm6446a",
558 },
b9ab1279
MG		 559};
560
f64691b3
MG		 561/*
562 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
563 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
564 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
565 * T1_TOP: Timer 1, top : <unused>
566 */
28552c2e 567static struct davinci_timer_info dm644x_timer_info = {
f64691b3
MG		 568 .timers = davinci_timer_instance,
569 .clockevent_id = T0_BOT,
570 .clocksource_id = T0_TOP,
571};
572
19955c3d 573static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
65e866a9
MG		 574 {
575 .mapbase = DAVINCI_UART0_BASE,
a98ca73e 576 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
65e866a9
MG		 577 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
578 UPF_IOREMAP,
579 .iotype = UPIO_MEM,
580 .regshift = 2,
581 },
19955c3d
MP		 582 {
583 .flags = 0,
584 }
585};
586static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
65e866a9
MG		 587 {
588 .mapbase = DAVINCI_UART1_BASE,
a98ca73e 589 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
65e866a9
MG		 590 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
591 UPF_IOREMAP,
592 .iotype = UPIO_MEM,
593 .regshift = 2,
594 },
19955c3d
MP		 595 {
596 .flags = 0,
597 }
598};
599static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
65e866a9
MG		 600 {
601 .mapbase = DAVINCI_UART2_BASE,
a98ca73e 602 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
65e866a9
MG		 603 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
604 UPF_IOREMAP,
605 .iotype = UPIO_MEM,
606 .regshift = 2,
607 },
608 {
19955c3d
MP		 609 .flags = 0,
610 }
65e866a9
MG		 611};
612
fcf7157b 613struct platform_device dm644x_serial_device[] = {
19955c3d
MP		 614 {
615 .name = "serial8250",
616 .id = PLAT8250_DEV_PLATFORM,
617 .dev = {
618 .platform_data = dm644x_serial0_platform_data,
619 }
65e866a9 620 },
19955c3d
MP		 621 {
622 .name = "serial8250",
623 .id = PLAT8250_DEV_PLATFORM1,
624 .dev = {
625 .platform_data = dm644x_serial1_platform_data,
626 }
627 },
628 {
629 .name = "serial8250",
630 .id = PLAT8250_DEV_PLATFORM2,
631 .dev = {
632 .platform_data = dm644x_serial2_platform_data,
633 }
634 },
635 {
636 }
65e866a9
MG		 637};
638
ab41910d 639static const struct davinci_soc_info davinci_soc_info_dm644x = {
79c3c0b7
MG		 640 .io_desc = dm644x_io_desc,
641 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
3347db83 642 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 643 .ids = dm644x_ids,
644 .ids_num = ARRAY_SIZE(dm644x_ids),
779b0d53 645 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 646 .pinmux_pins = dm644x_pins,
647 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
bd808947 648 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 649 .intc_irq_prios = dm644x_default_priorities,
650 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 651 .timer_info = &dm644x_timer_info,
972412b6 652 .emac_pdata = &dm644x_emac_pdata,
0d04eb47
DB		 653 .sram_dma = 0x00008000,
654 .sram_len = SZ_16K,
79c3c0b7
MG		 655};
656
6bce5efd 657void __init dm644x_init_asp(void)
25acf553
C		 658{
659 davinci_cfg_reg(DM644X_MCBSP);
25acf553
C		 660 platform_device_register(&dm644x_asp_device);
661}
662
d0e47fba
KH		 663void __init dm644x_init(void)
664{
79c3c0b7 665 davinci_common_init(&davinci_soc_info_dm644x);
5cfb19ac 666 davinci_map_sysmod();
96c08173
DL		 667}
668
669void __init dm644x_init_time(void)
670{
a5b1a871
DL		 671 void __iomem *pll1, *psc;
672 struct clk *clk;
673
674 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
675
676 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
677 dm644x_pll1_init(NULL, pll1, NULL);
678
679 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
680 dm644x_psc_init(NULL, psc);
681
682 clk = clk_get(NULL, "timer0");
683
684 davinci_timer_init(clk);
a5b1a871
DL		 685}
686
687static struct resource dm644x_pll2_resources[] = {
688 {
689 .start = DAVINCI_PLL2_BASE,
690 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
691 .flags = IORESOURCE_MEM,
692 },
693};
694
695static struct platform_device dm644x_pll2_device = {
696 .name = "dm644x-pll2",
697 .id = -1,
698 .resource = dm644x_pll2_resources,
699 .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
700};
701
702void __init dm644x_register_clocks(void)
703{
704 /* PLL1 and PSC are registered in dm644x_init_time() */
705 platform_device_register(&dm644x_pll2_device);
d0e47fba
KH		 706}
707
af946f26
MH		 708int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
709 struct vpbe_config *vpbe_cfg)
d0e47fba 710{
af946f26
MH		 711 if (vpfe_cfg || vpbe_cfg)
712 platform_device_register(&dm644x_vpss_device);
713
714 if (vpfe_cfg) {
715 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
716 platform_device_register(&dm644x_ccdc_dev);
717 platform_device_register(&dm644x_vpfe_dev);
af946f26
MH		 718 }
719
720 if (vpbe_cfg) {
721 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
722 platform_device_register(&dm644x_osd_dev);
723 platform_device_register(&dm644x_venc_dev);
724 platform_device_register(&dm644x_vpbe_dev);
725 platform_device_register(&dm644x_vpbe_display);
726 }
12db9588
MH		 727
728 return 0;
729}
730
de4f82a2
BG		 731void __init dm644x_init_irq(void)
732{
733 davinci_irq_init();
734}
735
8e730c7f 736void __init dm644x_init_devices(void)
12db9588 737{
7ab388e8 738 struct platform_device *edma_pdev;
8e730c7f 739 int ret;
12db9588 740
7ab388e8 741 edma_pdev = platform_device_register_full(&dm644x_edma_device);
8e730c7f 742 if (IS_ERR(edma_pdev))
7ab388e8 743 pr_warn("%s: Failed to register eDMA\n", __func__);
d22960c8
CC		 744
745 platform_device_register(&dm644x_mdio_device);
972412b6 746 platform_device_register(&dm644x_emac_device);
d22960c8 747
1233090c
SN		 748 ret = davinci_init_wdt();
749 if (ret)
750 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
751
d0e47fba 752}
Linux 6.x block layer and io_uring tree(s)