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ARM: davinci: pass clock as parameter to davinci_timer_init()
[linux-2.6-block.git] / arch / arm / mach-davinci / dm644x.c
CommitLineData
d0e47fba
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
d0e47fba
KH		 11#include <linux/init.h>
12#include <linux/clk.h>
65e866a9 13#include <linux/serial_8250.h>
a4f86c55 14#include <linux/dmaengine.h>
d0e47fba 15#include <linux/platform_device.h>
3ad7a42d 16#include <linux/platform_data/edma.h>
9cc1515c 17#include <linux/platform_data/gpio-davinci.h>
d0e47fba 18
79c3c0b7
MG		 19#include <asm/mach/map.h>
20
d0e47fba 21#include <mach/cputype.h>
d0e47fba 22#include <mach/irqs.h>
3acf731c 23#include "psc.h"
d0e47fba 24#include <mach/mux.h>
f64691b3 25#include <mach/time.h>
65e866a9 26#include <mach/serial.h>
79c3c0b7 27#include <mach/common.h>
d0e47fba 28
39c6d2d1 29#include "davinci.h"
d0e47fba
KH		 30#include "clock.h"
31#include "mux.h"
896f66b7 32#include "asp.h"
d0e47fba
KH		 33
34/*
35 * Device specific clocks
36 */
37#define DM644X_REF_FREQ 27000000
38
887b8a93
MH		 39#define DM644X_EMAC_BASE 0x01c80000
40#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
41#define DM644X_EMAC_CNTRL_OFFSET 0x0000
42#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
43#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
44#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
45
d0e47fba
KH		 46static struct pll_data pll1_data = {
47 .num = 1,
48 .phys_base = DAVINCI_PLL1_BASE,
49};
50
51static struct pll_data pll2_data = {
52 .num = 2,
53 .phys_base = DAVINCI_PLL2_BASE,
54};
55
56static struct clk ref_clk = {
57 .name = "ref_clk",
58 .rate = DM644X_REF_FREQ,
59};
60
61static struct clk pll1_clk = {
62 .name = "pll1",
63 .parent = &ref_clk,
64 .pll_data = &pll1_data,
65 .flags = CLK_PLL,
66};
67
68static struct clk pll1_sysclk1 = {
69 .name = "pll1_sysclk1",
70 .parent = &pll1_clk,
71 .flags = CLK_PLL,
72 .div_reg = PLLDIV1,
73};
74
75static struct clk pll1_sysclk2 = {
76 .name = "pll1_sysclk2",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV2,
80};
81
82static struct clk pll1_sysclk3 = {
83 .name = "pll1_sysclk3",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV3,
87};
88
89static struct clk pll1_sysclk5 = {
90 .name = "pll1_sysclk5",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV5,
94};
95
96static struct clk pll1_aux_clk = {
97 .name = "pll1_aux_clk",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL | PRE_PLL,
100};
101
102static struct clk pll1_sysclkbp = {
103 .name = "pll1_sysclkbp",
104 .parent = &pll1_clk,
105 .flags = CLK_PLL | PRE_PLL,
106 .div_reg = BPDIV
107};
108
109static struct clk pll2_clk = {
110 .name = "pll2",
111 .parent = &ref_clk,
112 .pll_data = &pll2_data,
113 .flags = CLK_PLL,
114};
115
116static struct clk pll2_sysclk1 = {
117 .name = "pll2_sysclk1",
118 .parent = &pll2_clk,
119 .flags = CLK_PLL,
120 .div_reg = PLLDIV1,
121};
122
123static struct clk pll2_sysclk2 = {
124 .name = "pll2_sysclk2",
125 .parent = &pll2_clk,
126 .flags = CLK_PLL,
127 .div_reg = PLLDIV2,
128};
129
130static struct clk pll2_sysclkbp = {
131 .name = "pll2_sysclkbp",
132 .parent = &pll2_clk,
133 .flags = CLK_PLL | PRE_PLL,
134 .div_reg = BPDIV
135};
136
137static struct clk dsp_clk = {
138 .name = "dsp",
139 .parent = &pll1_sysclk1,
140 .lpsc = DAVINCI_LPSC_GEM,
12221d43 141 .domain = DAVINCI_GPSC_DSPDOMAIN,
d0e47fba
KH		 142 .usecount = 1, /* REVISIT how to disable? */
143};
144
145static struct clk arm_clk = {
146 .name = "arm",
147 .parent = &pll1_sysclk2,
148 .lpsc = DAVINCI_LPSC_ARM,
149 .flags = ALWAYS_ENABLED,
150};
151
152static struct clk vicp_clk = {
153 .name = "vicp",
154 .parent = &pll1_sysclk2,
155 .lpsc = DAVINCI_LPSC_IMCOP,
12221d43 156 .domain = DAVINCI_GPSC_DSPDOMAIN,
d0e47fba
KH		 157 .usecount = 1, /* REVISIT how to disable? */
158};
159
160static struct clk vpss_master_clk = {
161 .name = "vpss_master",
162 .parent = &pll1_sysclk3,
163 .lpsc = DAVINCI_LPSC_VPSSMSTR,
164 .flags = CLK_PSC,
165};
166
167static struct clk vpss_slave_clk = {
168 .name = "vpss_slave",
169 .parent = &pll1_sysclk3,
170 .lpsc = DAVINCI_LPSC_VPSSSLV,
171};
172
173static struct clk uart0_clk = {
174 .name = "uart0",
175 .parent = &pll1_aux_clk,
176 .lpsc = DAVINCI_LPSC_UART0,
177};
178
179static struct clk uart1_clk = {
180 .name = "uart1",
181 .parent = &pll1_aux_clk,
182 .lpsc = DAVINCI_LPSC_UART1,
183};
184
185static struct clk uart2_clk = {
186 .name = "uart2",
187 .parent = &pll1_aux_clk,
188 .lpsc = DAVINCI_LPSC_UART2,
189};
190
191static struct clk emac_clk = {
192 .name = "emac",
193 .parent = &pll1_sysclk5,
194 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
195};
196
197static struct clk i2c_clk = {
198 .name = "i2c",
199 .parent = &pll1_aux_clk,
200 .lpsc = DAVINCI_LPSC_I2C,
201};
202
203static struct clk ide_clk = {
204 .name = "ide",
205 .parent = &pll1_sysclk5,
206 .lpsc = DAVINCI_LPSC_ATA,
207};
208
209static struct clk asp_clk = {
210 .name = "asp0",
211 .parent = &pll1_sysclk5,
212 .lpsc = DAVINCI_LPSC_McBSP,
213};
214
215static struct clk mmcsd_clk = {
216 .name = "mmcsd",
217 .parent = &pll1_sysclk5,
218 .lpsc = DAVINCI_LPSC_MMC_SD,
219};
220
221static struct clk spi_clk = {
222 .name = "spi",
223 .parent = &pll1_sysclk5,
224 .lpsc = DAVINCI_LPSC_SPI,
225};
226
227static struct clk gpio_clk = {
228 .name = "gpio",
229 .parent = &pll1_sysclk5,
230 .lpsc = DAVINCI_LPSC_GPIO,
231};
232
233static struct clk usb_clk = {
234 .name = "usb",
235 .parent = &pll1_sysclk5,
236 .lpsc = DAVINCI_LPSC_USB,
237};
238
239static struct clk vlynq_clk = {
240 .name = "vlynq",
241 .parent = &pll1_sysclk5,
242 .lpsc = DAVINCI_LPSC_VLYNQ,
243};
244
245static struct clk aemif_clk = {
246 .name = "aemif",
247 .parent = &pll1_sysclk5,
248 .lpsc = DAVINCI_LPSC_AEMIF,
249};
250
251static struct clk pwm0_clk = {
252 .name = "pwm0",
253 .parent = &pll1_aux_clk,
254 .lpsc = DAVINCI_LPSC_PWM0,
255};
256
257static struct clk pwm1_clk = {
258 .name = "pwm1",
259 .parent = &pll1_aux_clk,
260 .lpsc = DAVINCI_LPSC_PWM1,
261};
262
263static struct clk pwm2_clk = {
264 .name = "pwm2",
265 .parent = &pll1_aux_clk,
266 .lpsc = DAVINCI_LPSC_PWM2,
267};
268
269static struct clk timer0_clk = {
270 .name = "timer0",
271 .parent = &pll1_aux_clk,
272 .lpsc = DAVINCI_LPSC_TIMER0,
273};
274
275static struct clk timer1_clk = {
276 .name = "timer1",
277 .parent = &pll1_aux_clk,
278 .lpsc = DAVINCI_LPSC_TIMER1,
279};
280
281static struct clk timer2_clk = {
282 .name = "timer2",
283 .parent = &pll1_aux_clk,
284 .lpsc = DAVINCI_LPSC_TIMER2,
e9c54999 285 .usecount = 1, /* REVISIT: why can't this be disabled? */
d0e47fba
KH		 286};
287
28552c2e 288static struct clk_lookup dm644x_clks[] = {
d0e47fba
KH		 289 CLK(NULL, "ref", &ref_clk),
290 CLK(NULL, "pll1", &pll1_clk),
291 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
292 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
293 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
294 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
295 CLK(NULL, "pll1_aux", &pll1_aux_clk),
296 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
297 CLK(NULL, "pll2", &pll2_clk),
298 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
299 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
300 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
301 CLK(NULL, "dsp", &dsp_clk),
302 CLK(NULL, "arm", &arm_clk),
303 CLK(NULL, "vicp", &vicp_clk),
9a3e89b1
LP		 304 CLK("vpss", "master", &vpss_master_clk),
305 CLK("vpss", "slave", &vpss_slave_clk),
d0e47fba 306 CLK(NULL, "arm", &arm_clk),
19955c3d
MP		 307 CLK("serial8250.0", NULL, &uart0_clk),
308 CLK("serial8250.1", NULL, &uart1_clk),
309 CLK("serial8250.2", NULL, &uart2_clk),
d0e47fba 310 CLK("davinci_emac.1", NULL, &emac_clk),
46c18334 311 CLK("davinci_mdio.0", "fck", &emac_clk),
d0e47fba
KH		 312 CLK("i2c_davinci.1", NULL, &i2c_clk),
313 CLK("palm_bk3710", NULL, &ide_clk),
bedad0ca 314 CLK("davinci-mcbsp", NULL, &asp_clk),
d7ca4c75 315 CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
d0e47fba
KH		 316 CLK(NULL, "spi", &spi_clk),
317 CLK(NULL, "gpio", &gpio_clk),
318 CLK(NULL, "usb", &usb_clk),
319 CLK(NULL, "vlynq", &vlynq_clk),
320 CLK(NULL, "aemif", &aemif_clk),
321 CLK(NULL, "pwm0", &pwm0_clk),
322 CLK(NULL, "pwm1", &pwm1_clk),
323 CLK(NULL, "pwm2", &pwm2_clk),
324 CLK(NULL, "timer0", &timer0_clk),
325 CLK(NULL, "timer1", &timer1_clk),
84374812 326 CLK("davinci-wdt", NULL, &timer2_clk),
d0e47fba
KH		 327 CLK(NULL, NULL, NULL),
328};
329
972412b6
MG		 330static struct emac_platform_data dm644x_emac_pdata = {
331 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
332 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
333 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 334 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
335 .version = EMAC_VERSION_1,
336};
d0e47fba
KH		 337
338static struct resource dm644x_emac_resources[] = {
339 {
340 .start = DM644X_EMAC_BASE,
d22960c8 341 .end = DM644X_EMAC_BASE + SZ_16K - 1,
d0e47fba
KH		 342 .flags = IORESOURCE_MEM,
343 },
344 {
345 .start = IRQ_EMACINT,
346 .end = IRQ_EMACINT,
347 .flags = IORESOURCE_IRQ,
348 },
349};
350
351static struct platform_device dm644x_emac_device = {
352 .name = "davinci_emac",
353 .id = 1,
972412b6
MG		 354 .dev = {
355 .platform_data = &dm644x_emac_pdata,
356 },
d0e47fba
KH		 357 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
358 .resource = dm644x_emac_resources,
359};
360
d22960c8
CC		 361static struct resource dm644x_mdio_resources[] = {
362 {
363 .start = DM644X_EMAC_MDIO_BASE,
364 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
365 .flags = IORESOURCE_MEM,
366 },
367};
368
369static struct platform_device dm644x_mdio_device = {
370 .name = "davinci_mdio",
371 .id = 0,
372 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
373 .resource = dm644x_mdio_resources,
374};
375
d0e47fba
KH		 376/*
377 * Device specific mux setup
378 *
379 * soc description mux mode mode mux dbg
380 * reg offset mask mode
381 */
382static const struct mux_config dm644x_pins[] = {
0e585952 383#ifdef CONFIG_DAVINCI_MUX
d0e47fba
KH		 384MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
385MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
386MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
387
388MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
389
390MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
c16fe267
AP		 391MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
392MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
393MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
394MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
395MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
d0e47fba
KH		 396
397MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
398
399MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
400
401MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
402
403MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
404MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
405
406MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
407
408MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
409
410MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
411
412MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
413MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
414MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
415
416MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
417
418MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
419
420MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
421MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
422MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
423MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
424
425MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
426
427MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
428MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
0e585952 429#endif
d0e47fba
KH		 430};
431
673dd36f
MG		 432/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
433static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
434 [IRQ_VDINT0] = 2,
435 [IRQ_VDINT1] = 6,
436 [IRQ_VDINT2] = 6,
437 [IRQ_HISTINT] = 6,
438 [IRQ_H3AINT] = 6,
439 [IRQ_PRVUINT] = 6,
440 [IRQ_RSZINT] = 6,
441 [7] = 7,
442 [IRQ_VENCINT] = 6,
443 [IRQ_ASQINT] = 6,
444 [IRQ_IMXINT] = 6,
445 [IRQ_VLCDINT] = 6,
446 [IRQ_USBINT] = 4,
447 [IRQ_EMACINT] = 4,
448 [14] = 7,
449 [15] = 7,
450 [IRQ_CCINT0] = 5, /* dma */
451 [IRQ_CCERRINT] = 5, /* dma */
452 [IRQ_TCERRINT0] = 5, /* dma */
453 [IRQ_TCERRINT] = 5, /* dma */
454 [IRQ_PSCIN] = 7,
455 [21] = 7,
456 [IRQ_IDE] = 4,
457 [23] = 7,
458 [IRQ_MBXINT] = 7,
459 [IRQ_MBRINT] = 7,
460 [IRQ_MMCINT] = 7,
461 [IRQ_SDIOINT] = 7,
462 [28] = 7,
463 [IRQ_DDRINT] = 7,
464 [IRQ_AEMIFINT] = 7,
465 [IRQ_VLQINT] = 4,
466 [IRQ_TINT0_TINT12] = 2, /* clockevent */
467 [IRQ_TINT0_TINT34] = 2, /* clocksource */
468 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
469 [IRQ_TINT1_TINT34] = 7, /* system tick */
470 [IRQ_PWMINT0] = 7,
471 [IRQ_PWMINT1] = 7,
472 [IRQ_PWMINT2] = 7,
473 [IRQ_I2C] = 3,
474 [IRQ_UARTINT0] = 3,
475 [IRQ_UARTINT1] = 3,
476 [IRQ_UARTINT2] = 3,
477 [IRQ_SPINT0] = 3,
478 [IRQ_SPINT1] = 3,
479 [45] = 7,
480 [IRQ_DSP2ARM0] = 4,
481 [IRQ_DSP2ARM1] = 4,
482 [IRQ_GPIO0] = 7,
483 [IRQ_GPIO1] = 7,
484 [IRQ_GPIO2] = 7,
485 [IRQ_GPIO3] = 7,
486 [IRQ_GPIO4] = 7,
487 [IRQ_GPIO5] = 7,
488 [IRQ_GPIO6] = 7,
489 [IRQ_GPIO7] = 7,
490 [IRQ_GPIOBNK0] = 7,
491 [IRQ_GPIOBNK1] = 7,
492 [IRQ_GPIOBNK2] = 7,
493 [IRQ_GPIOBNK3] = 7,
494 [IRQ_GPIOBNK4] = 7,
495 [IRQ_COMMTX] = 7,
496 [IRQ_COMMRX] = 7,
497 [IRQ_EMUINT] = 7,
498};
499
d0e47fba
KH		 500/*----------------------------------------------------------------------*/
501
d4cb7f40 502static s8 queue_priority_mapping[][2] = {
60902a2c
SR		 503 /* {event queue no, Priority} */
504 {0, 3},
505 {1, 7},
506 {-1, -1},
507};
508
a4f86c55
PU		 509static const struct dma_slave_map dm644x_edma_map[] = {
510 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
511 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
512 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
513 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
514 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
515 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
516};
517
d4cb7f40 518static struct edma_soc_info dm644x_edma_pdata = {
bc3ac9f3 519 .queue_priority_mapping = queue_priority_mapping,
f23fe857 520 .default_queue = EVENTQ_1,
a4f86c55
PU		 521 .slave_map = dm644x_edma_map,
522 .slavecnt = ARRAY_SIZE(dm644x_edma_map),
bc3ac9f3
SN		 523};
524
d0e47fba
KH		 525static struct resource edma_resources[] = {
526 {
d4cb7f40 527 .name = "edma3_cc",
d0e47fba
KH		 528 .start = 0x01c00000,
529 .end = 0x01c00000 + SZ_64K - 1,
530 .flags = IORESOURCE_MEM,
531 },
532 {
d4cb7f40 533 .name = "edma3_tc0",
d0e47fba
KH		 534 .start = 0x01c10000,
535 .end = 0x01c10000 + SZ_1K - 1,
536 .flags = IORESOURCE_MEM,
537 },
538 {
d4cb7f40 539 .name = "edma3_tc1",
d0e47fba
KH		 540 .start = 0x01c10400,
541 .end = 0x01c10400 + SZ_1K - 1,
542 .flags = IORESOURCE_MEM,
543 },
544 {
d4cb7f40 545 .name = "edma3_ccint",
d0e47fba
KH		 546 .start = IRQ_CCINT0,
547 .flags = IORESOURCE_IRQ,
548 },
549 {
d4cb7f40 550 .name = "edma3_ccerrint",
d0e47fba
KH		 551 .start = IRQ_CCERRINT,
552 .flags = IORESOURCE_IRQ,
553 },
554 /* not using TC*_ERR */
555};
556
7ab388e8
PU		 557static const struct platform_device_info dm644x_edma_device __initconst = {
558 .name = "edma",
559 .id = 0,
cef5b0da 560 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 561 .res = edma_resources,
562 .num_res = ARRAY_SIZE(edma_resources),
563 .data = &dm644x_edma_pdata,
564 .size_data = sizeof(dm644x_edma_pdata),
d0e47fba
KH		 565};
566
25acf553
C		 567/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
568static struct resource dm644x_asp_resources[] = {
569 {
ee880dbd 570 .name = "mpu",
25acf553
C		 571 .start = DAVINCI_ASP0_BASE,
572 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
573 .flags = IORESOURCE_MEM,
574 },
575 {
576 .start = DAVINCI_DMA_ASP0_TX,
577 .end = DAVINCI_DMA_ASP0_TX,
578 .flags = IORESOURCE_DMA,
579 },
580 {
581 .start = DAVINCI_DMA_ASP0_RX,
582 .end = DAVINCI_DMA_ASP0_RX,
583 .flags = IORESOURCE_DMA,
584 },
585};
586
587static struct platform_device dm644x_asp_device = {
bedad0ca 588 .name = "davinci-mcbsp",
25acf553
C		 589 .id = -1,
590 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
591 .resource = dm644x_asp_resources,
592};
593
51f31cb3
MH		 594#define DM644X_VPSS_BASE 0x01c73400
595
ab8e8df8
MK		 596static struct resource dm644x_vpss_resources[] = {
597 {
598 /* VPSS Base address */
599 .name = "vpss",
51f31cb3
MH		 600 .start = DM644X_VPSS_BASE,
601 .end = DM644X_VPSS_BASE + 0xff,
602 .flags = IORESOURCE_MEM,
ab8e8df8
MK		 603 },
604};
605
606static struct platform_device dm644x_vpss_device = {
607 .name = "vpss",
608 .id = -1,
609 .dev.platform_data = "dm644x_vpss",
610 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
611 .resource = dm644x_vpss_resources,
612};
613
314d7389 614static struct resource dm644x_vpfe_resources[] = {
ab8e8df8
MK		 615 {
616 .start = IRQ_VDINT0,
617 .end = IRQ_VDINT0,
618 .flags = IORESOURCE_IRQ,
619 },
620 {
621 .start = IRQ_VDINT1,
622 .end = IRQ_VDINT1,
623 .flags = IORESOURCE_IRQ,
624 },
77c8b5fb
MK		 625};
626
af946f26 627static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
77c8b5fb
MK		 628static struct resource dm644x_ccdc_resource[] = {
629 /* CCDC Base address */
ab8e8df8
MK		 630 {
631 .start = 0x01c70400,
632 .end = 0x01c70400 + 0xff,
633 .flags = IORESOURCE_MEM,
634 },
635};
636
77c8b5fb
MK		 637static struct platform_device dm644x_ccdc_dev = {
638 .name = "dm644x_ccdc",
639 .id = -1,
640 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
641 .resource = dm644x_ccdc_resource,
642 .dev = {
af946f26 643 .dma_mask = &dm644x_video_dma_mask,
77c8b5fb
MK		 644 .coherent_dma_mask = DMA_BIT_MASK(32),
645 },
646};
647
314d7389 648static struct platform_device dm644x_vpfe_dev = {
ab8e8df8
MK		 649 .name = CAPTURE_DRV_NAME,
650 .id = -1,
314d7389
MH		 651 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
652 .resource = dm644x_vpfe_resources,
ab8e8df8 653 .dev = {
af946f26
MH		 654 .dma_mask = &dm644x_video_dma_mask,
655 .coherent_dma_mask = DMA_BIT_MASK(32),
656 },
657};
658
659#define DM644X_OSD_BASE 0x01c72600
660
661static struct resource dm644x_osd_resources[] = {
662 {
663 .start = DM644X_OSD_BASE,
664 .end = DM644X_OSD_BASE + 0x1ff,
665 .flags = IORESOURCE_MEM,
666 },
667};
668
af946f26 669static struct platform_device dm644x_osd_dev = {
caff80c3 670 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
af946f26
MH		 671 .id = -1,
672 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
673 .resource = dm644x_osd_resources,
674 .dev = {
675 .dma_mask = &dm644x_video_dma_mask,
676 .coherent_dma_mask = DMA_BIT_MASK(32),
af946f26
MH		 677 },
678};
679
680#define DM644X_VENC_BASE 0x01c72400
681
682static struct resource dm644x_venc_resources[] = {
683 {
684 .start = DM644X_VENC_BASE,
685 .end = DM644X_VENC_BASE + 0x17f,
686 .flags = IORESOURCE_MEM,
687 },
688};
689
690#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
691#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
692#define DM644X_VPSS_VENCLKEN BIT(3)
693#define DM644X_VPSS_DACCLKEN BIT(4)
694
695static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
36864082 696 unsigned int pclock)
af946f26
MH		 697{
698 int ret = 0;
699 u32 v = DM644X_VPSS_VENCLKEN;
700
701 switch (type) {
702 case VPBE_ENC_STD:
703 v |= DM644X_VPSS_DACCLKEN;
704 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
705 break;
ef2d41b1 706 case VPBE_ENC_DV_TIMINGS:
36864082 707 if (pclock <= 27000000) {
e37212aa 708 v |= DM644X_VPSS_DACCLKEN;
af946f26 709 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
36864082 710 } else {
af946f26
MH		 711 /*
712 * For HD, use external clock source since
713 * HD requires higher clock rate
714 */
715 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
716 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
af946f26
MH		 717 }
718 break;
719 default:
720 ret = -EINVAL;
721 }
722
723 return ret;
724}
725
726static struct resource dm644x_v4l2_disp_resources[] = {
727 {
728 .start = IRQ_VENCINT,
729 .end = IRQ_VENCINT,
730 .flags = IORESOURCE_IRQ,
731 },
732};
733
734static struct platform_device dm644x_vpbe_display = {
735 .name = "vpbe-v4l2",
736 .id = -1,
737 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
738 .resource = dm644x_v4l2_disp_resources,
739 .dev = {
740 .dma_mask = &dm644x_video_dma_mask,
741 .coherent_dma_mask = DMA_BIT_MASK(32),
742 },
743};
744
745static struct venc_platform_data dm644x_venc_pdata = {
af946f26
MH		 746 .setup_clock = dm644x_venc_setup_clock,
747};
748
749static struct platform_device dm644x_venc_dev = {
caff80c3 750 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
af946f26
MH		 751 .id = -1,
752 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
753 .resource = dm644x_venc_resources,
754 .dev = {
755 .dma_mask = &dm644x_video_dma_mask,
756 .coherent_dma_mask = DMA_BIT_MASK(32),
757 .platform_data = &dm644x_venc_pdata,
758 },
759};
760
761static struct platform_device dm644x_vpbe_dev = {
762 .name = "vpbe_controller",
763 .id = -1,
764 .dev = {
765 .dma_mask = &dm644x_video_dma_mask,
ab8e8df8
MK		 766 .coherent_dma_mask = DMA_BIT_MASK(32),
767 },
768};
769
9cc1515c
PA		 770static struct resource dm644_gpio_resources[] = {
771 { /* registers */
772 .start = DAVINCI_GPIO_BASE,
773 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
774 .flags = IORESOURCE_MEM,
775 },
776 { /* interrupt */
777 .start = IRQ_GPIOBNK0,
778 .end = IRQ_GPIOBNK4,
779 .flags = IORESOURCE_IRQ,
780 },
781};
782
783static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
784 .ngpio = 71,
9cc1515c
PA		 785};
786
787int __init dm644x_gpio_register(void)
788{
789 return davinci_gpio_register(dm644_gpio_resources,
e462f1f5 790 ARRAY_SIZE(dm644_gpio_resources),
9cc1515c
PA		 791 &dm644_gpio_platform_data);
792}
d0e47fba 793/*----------------------------------------------------------------------*/
ac7b75b5 794
79c3c0b7
MG		 795static struct map_desc dm644x_io_desc[] = {
796 {
797 .virtual = IO_VIRT,
798 .pfn = __phys_to_pfn(IO_PHYS),
799 .length = IO_SIZE,
800 .type = MT_DEVICE
801 },
802};
803
b9ab1279
MG		 804/* Contents of JTAG ID register used to identify exact cpu type */
805static struct davinci_id dm644x_ids[] = {
806 {
807 .variant = 0x0,
808 .part_no = 0xb700,
809 .manufacturer = 0x017,
810 .cpu_id = DAVINCI_CPU_ID_DM6446,
811 .name = "dm6446",
812 },
98d0e9fc
RS		 813 {
814 .variant = 0x1,
815 .part_no = 0xb700,
816 .manufacturer = 0x017,
817 .cpu_id = DAVINCI_CPU_ID_DM6446,
818 .name = "dm6446a",
819 },
b9ab1279
MG		 820};
821
e4c822c7 822static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 823
f64691b3
MG		 824/*
825 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
826 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
827 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
828 * T1_TOP: Timer 1, top : <unused>
829 */
28552c2e 830static struct davinci_timer_info dm644x_timer_info = {
f64691b3
MG		 831 .timers = davinci_timer_instance,
832 .clockevent_id = T0_BOT,
833 .clocksource_id = T0_TOP,
834};
835
19955c3d 836static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
65e866a9
MG		 837 {
838 .mapbase = DAVINCI_UART0_BASE,
839 .irq = IRQ_UARTINT0,
840 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
841 UPF_IOREMAP,
842 .iotype = UPIO_MEM,
843 .regshift = 2,
844 },
19955c3d
MP		 845 {
846 .flags = 0,
847 }
848};
849static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
65e866a9
MG		 850 {
851 .mapbase = DAVINCI_UART1_BASE,
852 .irq = IRQ_UARTINT1,
853 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
854 UPF_IOREMAP,
855 .iotype = UPIO_MEM,
856 .regshift = 2,
857 },
19955c3d
MP		 858 {
859 .flags = 0,
860 }
861};
862static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
65e866a9
MG		 863 {
864 .mapbase = DAVINCI_UART2_BASE,
865 .irq = IRQ_UARTINT2,
866 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
867 UPF_IOREMAP,
868 .iotype = UPIO_MEM,
869 .regshift = 2,
870 },
871 {
19955c3d
MP		 872 .flags = 0,
873 }
65e866a9
MG		 874};
875
fcf7157b 876struct platform_device dm644x_serial_device[] = {
19955c3d
MP		 877 {
878 .name = "serial8250",
879 .id = PLAT8250_DEV_PLATFORM,
880 .dev = {
881 .platform_data = dm644x_serial0_platform_data,
882 }
65e866a9 883 },
19955c3d
MP		 884 {
885 .name = "serial8250",
886 .id = PLAT8250_DEV_PLATFORM1,
887 .dev = {
888 .platform_data = dm644x_serial1_platform_data,
889 }
890 },
891 {
892 .name = "serial8250",
893 .id = PLAT8250_DEV_PLATFORM2,
894 .dev = {
895 .platform_data = dm644x_serial2_platform_data,
896 }
897 },
898 {
899 }
65e866a9
MG		 900};
901
ab41910d 902static const struct davinci_soc_info davinci_soc_info_dm644x = {
79c3c0b7
MG		 903 .io_desc = dm644x_io_desc,
904 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
3347db83 905 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 906 .ids = dm644x_ids,
907 .ids_num = ARRAY_SIZE(dm644x_ids),
d81d188c
MG		 908 .psc_bases = dm644x_psc_bases,
909 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
779b0d53 910 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 911 .pinmux_pins = dm644x_pins,
912 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
bd808947 913 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 914 .intc_type = DAVINCI_INTC_TYPE_AINTC,
915 .intc_irq_prios = dm644x_default_priorities,
916 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 917 .timer_info = &dm644x_timer_info,
972412b6 918 .emac_pdata = &dm644x_emac_pdata,
0d04eb47
DB		 919 .sram_dma = 0x00008000,
920 .sram_len = SZ_16K,
79c3c0b7
MG		 921};
922
6bce5efd 923void __init dm644x_init_asp(void)
25acf553
C		 924{
925 davinci_cfg_reg(DM644X_MCBSP);
25acf553
C		 926 platform_device_register(&dm644x_asp_device);
927}
928
d0e47fba
KH		 929void __init dm644x_init(void)
930{
79c3c0b7 931 davinci_common_init(&davinci_soc_info_dm644x);
5cfb19ac 932 davinci_map_sysmod();
96c08173
DL		 933}
934
935void __init dm644x_init_time(void)
936{
937 davinci_clk_init(dm644x_clks);
a7da5277 938 davinci_timer_init(&timer0_clk);
d0e47fba
KH		 939}
940
af946f26
MH		 941int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
942 struct vpbe_config *vpbe_cfg)
d0e47fba 943{
af946f26
MH		 944 if (vpfe_cfg || vpbe_cfg)
945 platform_device_register(&dm644x_vpss_device);
946
947 if (vpfe_cfg) {
948 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
949 platform_device_register(&dm644x_ccdc_dev);
950 platform_device_register(&dm644x_vpfe_dev);
af946f26
MH		 951 }
952
953 if (vpbe_cfg) {
954 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
955 platform_device_register(&dm644x_osd_dev);
956 platform_device_register(&dm644x_venc_dev);
957 platform_device_register(&dm644x_vpbe_dev);
958 platform_device_register(&dm644x_vpbe_display);
959 }
12db9588
MH		 960
961 return 0;
962}
963
8e730c7f 964void __init dm644x_init_devices(void)
12db9588 965{
7ab388e8 966 struct platform_device *edma_pdev;
8e730c7f 967 int ret;
12db9588 968
7ab388e8 969 edma_pdev = platform_device_register_full(&dm644x_edma_device);
8e730c7f 970 if (IS_ERR(edma_pdev))
7ab388e8 971 pr_warn("%s: Failed to register eDMA\n", __func__);
d22960c8
CC		 972
973 platform_device_register(&dm644x_mdio_device);
972412b6 974 platform_device_register(&dm644x_emac_device);
d22960c8 975
1233090c
SN		 976 ret = davinci_init_wdt();
977 if (ret)
978 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
979
d0e47fba 980}
Linux 6.x block layer and io_uring tree(s)