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ARM: davinci: dm644x: add new clock init using common clock framework
[linux-2.6-block.git] / arch / arm / mach-davinci / dm644x.c
CommitLineData
d0e47fba
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
a5b1a871
DL		 11
12#include <linux/clk-provider.h>
13#include <linux/clk/davinci.h>
14#include <linux/clkdev.h>
a4f86c55 15#include <linux/dmaengine.h>
a5b1a871 16#include <linux/init.h>
3ad7a42d 17#include <linux/platform_data/edma.h>
9cc1515c 18#include <linux/platform_data/gpio-davinci.h>
a5b1a871
DL		 19#include <linux/platform_device.h>
20#include <linux/serial_8250.h>
d0e47fba 21
79c3c0b7
MG		 22#include <asm/mach/map.h>
23
a5b1a871 24#include <mach/common.h>
d0e47fba 25#include <mach/cputype.h>
d0e47fba 26#include <mach/irqs.h>
d0e47fba 27#include <mach/mux.h>
65e866a9 28#include <mach/serial.h>
a5b1a871 29#include <mach/time.h>
d0e47fba 30
a5b1a871 31#include "asp.h"
39c6d2d1 32#include "davinci.h"
d0e47fba 33#include "mux.h"
a5b1a871
DL		 34
35#ifndef CONFIG_COMMON_CLK
36#include "clock.h"
37#include "psc.h"
38#endif
d0e47fba
KH		 39
40/*
41 * Device specific clocks
42 */
43#define DM644X_REF_FREQ 27000000
44
887b8a93
MH		 45#define DM644X_EMAC_BASE 0x01c80000
46#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
47#define DM644X_EMAC_CNTRL_OFFSET 0x0000
48#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
49#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
50#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
51
a5b1a871 52#ifndef CONFIG_COMMON_CLK
d0e47fba
KH		 53static struct pll_data pll1_data = {
54 .num = 1,
55 .phys_base = DAVINCI_PLL1_BASE,
56};
57
58static struct pll_data pll2_data = {
59 .num = 2,
60 .phys_base = DAVINCI_PLL2_BASE,
61};
62
63static struct clk ref_clk = {
64 .name = "ref_clk",
65 .rate = DM644X_REF_FREQ,
66};
67
68static struct clk pll1_clk = {
69 .name = "pll1",
70 .parent = &ref_clk,
71 .pll_data = &pll1_data,
72 .flags = CLK_PLL,
73};
74
75static struct clk pll1_sysclk1 = {
76 .name = "pll1_sysclk1",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV1,
80};
81
82static struct clk pll1_sysclk2 = {
83 .name = "pll1_sysclk2",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV2,
87};
88
89static struct clk pll1_sysclk3 = {
90 .name = "pll1_sysclk3",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV3,
94};
95
96static struct clk pll1_sysclk5 = {
97 .name = "pll1_sysclk5",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV5,
101};
102
103static struct clk pll1_aux_clk = {
104 .name = "pll1_aux_clk",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL | PRE_PLL,
107};
108
109static struct clk pll1_sysclkbp = {
110 .name = "pll1_sysclkbp",
111 .parent = &pll1_clk,
112 .flags = CLK_PLL | PRE_PLL,
113 .div_reg = BPDIV
114};
115
116static struct clk pll2_clk = {
117 .name = "pll2",
118 .parent = &ref_clk,
119 .pll_data = &pll2_data,
120 .flags = CLK_PLL,
121};
122
123static struct clk pll2_sysclk1 = {
124 .name = "pll2_sysclk1",
125 .parent = &pll2_clk,
126 .flags = CLK_PLL,
127 .div_reg = PLLDIV1,
128};
129
130static struct clk pll2_sysclk2 = {
131 .name = "pll2_sysclk2",
132 .parent = &pll2_clk,
133 .flags = CLK_PLL,
134 .div_reg = PLLDIV2,
135};
136
137static struct clk pll2_sysclkbp = {
138 .name = "pll2_sysclkbp",
139 .parent = &pll2_clk,
140 .flags = CLK_PLL | PRE_PLL,
141 .div_reg = BPDIV
142};
143
144static struct clk dsp_clk = {
145 .name = "dsp",
146 .parent = &pll1_sysclk1,
147 .lpsc = DAVINCI_LPSC_GEM,
12221d43 148 .domain = DAVINCI_GPSC_DSPDOMAIN,
d0e47fba
KH		 149 .usecount = 1, /* REVISIT how to disable? */
150};
151
152static struct clk arm_clk = {
153 .name = "arm",
154 .parent = &pll1_sysclk2,
155 .lpsc = DAVINCI_LPSC_ARM,
156 .flags = ALWAYS_ENABLED,
157};
158
159static struct clk vicp_clk = {
160 .name = "vicp",
161 .parent = &pll1_sysclk2,
162 .lpsc = DAVINCI_LPSC_IMCOP,
12221d43 163 .domain = DAVINCI_GPSC_DSPDOMAIN,
d0e47fba
KH		 164 .usecount = 1, /* REVISIT how to disable? */
165};
166
167static struct clk vpss_master_clk = {
168 .name = "vpss_master",
169 .parent = &pll1_sysclk3,
170 .lpsc = DAVINCI_LPSC_VPSSMSTR,
171 .flags = CLK_PSC,
172};
173
174static struct clk vpss_slave_clk = {
175 .name = "vpss_slave",
176 .parent = &pll1_sysclk3,
177 .lpsc = DAVINCI_LPSC_VPSSSLV,
178};
179
180static struct clk uart0_clk = {
181 .name = "uart0",
182 .parent = &pll1_aux_clk,
183 .lpsc = DAVINCI_LPSC_UART0,
184};
185
186static struct clk uart1_clk = {
187 .name = "uart1",
188 .parent = &pll1_aux_clk,
189 .lpsc = DAVINCI_LPSC_UART1,
190};
191
192static struct clk uart2_clk = {
193 .name = "uart2",
194 .parent = &pll1_aux_clk,
195 .lpsc = DAVINCI_LPSC_UART2,
196};
197
198static struct clk emac_clk = {
199 .name = "emac",
200 .parent = &pll1_sysclk5,
201 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
202};
203
204static struct clk i2c_clk = {
205 .name = "i2c",
206 .parent = &pll1_aux_clk,
207 .lpsc = DAVINCI_LPSC_I2C,
208};
209
210static struct clk ide_clk = {
211 .name = "ide",
212 .parent = &pll1_sysclk5,
213 .lpsc = DAVINCI_LPSC_ATA,
214};
215
216static struct clk asp_clk = {
217 .name = "asp0",
218 .parent = &pll1_sysclk5,
219 .lpsc = DAVINCI_LPSC_McBSP,
220};
221
222static struct clk mmcsd_clk = {
223 .name = "mmcsd",
224 .parent = &pll1_sysclk5,
225 .lpsc = DAVINCI_LPSC_MMC_SD,
226};
227
228static struct clk spi_clk = {
229 .name = "spi",
230 .parent = &pll1_sysclk5,
231 .lpsc = DAVINCI_LPSC_SPI,
232};
233
234static struct clk gpio_clk = {
235 .name = "gpio",
236 .parent = &pll1_sysclk5,
237 .lpsc = DAVINCI_LPSC_GPIO,
238};
239
240static struct clk usb_clk = {
241 .name = "usb",
242 .parent = &pll1_sysclk5,
243 .lpsc = DAVINCI_LPSC_USB,
244};
245
246static struct clk vlynq_clk = {
247 .name = "vlynq",
248 .parent = &pll1_sysclk5,
249 .lpsc = DAVINCI_LPSC_VLYNQ,
250};
251
252static struct clk aemif_clk = {
253 .name = "aemif",
254 .parent = &pll1_sysclk5,
255 .lpsc = DAVINCI_LPSC_AEMIF,
256};
257
258static struct clk pwm0_clk = {
259 .name = "pwm0",
260 .parent = &pll1_aux_clk,
261 .lpsc = DAVINCI_LPSC_PWM0,
262};
263
264static struct clk pwm1_clk = {
265 .name = "pwm1",
266 .parent = &pll1_aux_clk,
267 .lpsc = DAVINCI_LPSC_PWM1,
268};
269
270static struct clk pwm2_clk = {
271 .name = "pwm2",
272 .parent = &pll1_aux_clk,
273 .lpsc = DAVINCI_LPSC_PWM2,
274};
275
276static struct clk timer0_clk = {
277 .name = "timer0",
278 .parent = &pll1_aux_clk,
279 .lpsc = DAVINCI_LPSC_TIMER0,
280};
281
282static struct clk timer1_clk = {
283 .name = "timer1",
284 .parent = &pll1_aux_clk,
285 .lpsc = DAVINCI_LPSC_TIMER1,
286};
287
288static struct clk timer2_clk = {
289 .name = "timer2",
290 .parent = &pll1_aux_clk,
291 .lpsc = DAVINCI_LPSC_TIMER2,
e9c54999 292 .usecount = 1, /* REVISIT: why can't this be disabled? */
d0e47fba
KH		 293};
294
28552c2e 295static struct clk_lookup dm644x_clks[] = {
d0e47fba
KH		 296 CLK(NULL, "ref", &ref_clk),
297 CLK(NULL, "pll1", &pll1_clk),
298 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
299 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
300 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
301 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
302 CLK(NULL, "pll1_aux", &pll1_aux_clk),
303 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
304 CLK(NULL, "pll2", &pll2_clk),
305 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
306 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
307 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
308 CLK(NULL, "dsp", &dsp_clk),
309 CLK(NULL, "arm", &arm_clk),
310 CLK(NULL, "vicp", &vicp_clk),
9a3e89b1
LP		 311 CLK("vpss", "master", &vpss_master_clk),
312 CLK("vpss", "slave", &vpss_slave_clk),
d0e47fba 313 CLK(NULL, "arm", &arm_clk),
19955c3d
MP		 314 CLK("serial8250.0", NULL, &uart0_clk),
315 CLK("serial8250.1", NULL, &uart1_clk),
316 CLK("serial8250.2", NULL, &uart2_clk),
d0e47fba 317 CLK("davinci_emac.1", NULL, &emac_clk),
46c18334 318 CLK("davinci_mdio.0", "fck", &emac_clk),
d0e47fba
KH		 319 CLK("i2c_davinci.1", NULL, &i2c_clk),
320 CLK("palm_bk3710", NULL, &ide_clk),
bedad0ca 321 CLK("davinci-mcbsp", NULL, &asp_clk),
d7ca4c75 322 CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
d0e47fba
KH		 323 CLK(NULL, "spi", &spi_clk),
324 CLK(NULL, "gpio", &gpio_clk),
325 CLK(NULL, "usb", &usb_clk),
326 CLK(NULL, "vlynq", &vlynq_clk),
327 CLK(NULL, "aemif", &aemif_clk),
328 CLK(NULL, "pwm0", &pwm0_clk),
329 CLK(NULL, "pwm1", &pwm1_clk),
330 CLK(NULL, "pwm2", &pwm2_clk),
331 CLK(NULL, "timer0", &timer0_clk),
332 CLK(NULL, "timer1", &timer1_clk),
84374812 333 CLK("davinci-wdt", NULL, &timer2_clk),
d0e47fba
KH		 334 CLK(NULL, NULL, NULL),
335};
a5b1a871 336#endif
d0e47fba 337
972412b6
MG		 338static struct emac_platform_data dm644x_emac_pdata = {
339 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
340 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
341 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 342 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
343 .version = EMAC_VERSION_1,
344};
d0e47fba
KH		 345
346static struct resource dm644x_emac_resources[] = {
347 {
348 .start = DM644X_EMAC_BASE,
d22960c8 349 .end = DM644X_EMAC_BASE + SZ_16K - 1,
d0e47fba
KH		 350 .flags = IORESOURCE_MEM,
351 },
352 {
353 .start = IRQ_EMACINT,
354 .end = IRQ_EMACINT,
355 .flags = IORESOURCE_IRQ,
356 },
357};
358
359static struct platform_device dm644x_emac_device = {
360 .name = "davinci_emac",
361 .id = 1,
972412b6
MG		 362 .dev = {
363 .platform_data = &dm644x_emac_pdata,
364 },
d0e47fba
KH		 365 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
366 .resource = dm644x_emac_resources,
367};
368
d22960c8
CC		 369static struct resource dm644x_mdio_resources[] = {
370 {
371 .start = DM644X_EMAC_MDIO_BASE,
372 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
373 .flags = IORESOURCE_MEM,
374 },
375};
376
377static struct platform_device dm644x_mdio_device = {
378 .name = "davinci_mdio",
379 .id = 0,
380 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
381 .resource = dm644x_mdio_resources,
382};
383
d0e47fba
KH		 384/*
385 * Device specific mux setup
386 *
387 * soc description mux mode mode mux dbg
388 * reg offset mask mode
389 */
390static const struct mux_config dm644x_pins[] = {
0e585952 391#ifdef CONFIG_DAVINCI_MUX
d0e47fba
KH		 392MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
393MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
394MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
395
396MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
397
398MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
c16fe267
AP		 399MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
400MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
401MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
402MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
403MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
d0e47fba
KH		 404
405MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
406
407MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
408
409MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
410
411MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
412MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
413
414MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
415
416MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
417
418MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
419
420MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
421MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
422MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
423
424MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
425
426MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
427
428MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
429MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
430MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
431MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
432
433MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
434
435MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
436MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
0e585952 437#endif
d0e47fba
KH		 438};
439
673dd36f
MG		 440/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
441static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
442 [IRQ_VDINT0] = 2,
443 [IRQ_VDINT1] = 6,
444 [IRQ_VDINT2] = 6,
445 [IRQ_HISTINT] = 6,
446 [IRQ_H3AINT] = 6,
447 [IRQ_PRVUINT] = 6,
448 [IRQ_RSZINT] = 6,
449 [7] = 7,
450 [IRQ_VENCINT] = 6,
451 [IRQ_ASQINT] = 6,
452 [IRQ_IMXINT] = 6,
453 [IRQ_VLCDINT] = 6,
454 [IRQ_USBINT] = 4,
455 [IRQ_EMACINT] = 4,
456 [14] = 7,
457 [15] = 7,
458 [IRQ_CCINT0] = 5, /* dma */
459 [IRQ_CCERRINT] = 5, /* dma */
460 [IRQ_TCERRINT0] = 5, /* dma */
461 [IRQ_TCERRINT] = 5, /* dma */
462 [IRQ_PSCIN] = 7,
463 [21] = 7,
464 [IRQ_IDE] = 4,
465 [23] = 7,
466 [IRQ_MBXINT] = 7,
467 [IRQ_MBRINT] = 7,
468 [IRQ_MMCINT] = 7,
469 [IRQ_SDIOINT] = 7,
470 [28] = 7,
471 [IRQ_DDRINT] = 7,
472 [IRQ_AEMIFINT] = 7,
473 [IRQ_VLQINT] = 4,
474 [IRQ_TINT0_TINT12] = 2, /* clockevent */
475 [IRQ_TINT0_TINT34] = 2, /* clocksource */
476 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
477 [IRQ_TINT1_TINT34] = 7, /* system tick */
478 [IRQ_PWMINT0] = 7,
479 [IRQ_PWMINT1] = 7,
480 [IRQ_PWMINT2] = 7,
481 [IRQ_I2C] = 3,
482 [IRQ_UARTINT0] = 3,
483 [IRQ_UARTINT1] = 3,
484 [IRQ_UARTINT2] = 3,
485 [IRQ_SPINT0] = 3,
486 [IRQ_SPINT1] = 3,
487 [45] = 7,
488 [IRQ_DSP2ARM0] = 4,
489 [IRQ_DSP2ARM1] = 4,
490 [IRQ_GPIO0] = 7,
491 [IRQ_GPIO1] = 7,
492 [IRQ_GPIO2] = 7,
493 [IRQ_GPIO3] = 7,
494 [IRQ_GPIO4] = 7,
495 [IRQ_GPIO5] = 7,
496 [IRQ_GPIO6] = 7,
497 [IRQ_GPIO7] = 7,
498 [IRQ_GPIOBNK0] = 7,
499 [IRQ_GPIOBNK1] = 7,
500 [IRQ_GPIOBNK2] = 7,
501 [IRQ_GPIOBNK3] = 7,
502 [IRQ_GPIOBNK4] = 7,
503 [IRQ_COMMTX] = 7,
504 [IRQ_COMMRX] = 7,
505 [IRQ_EMUINT] = 7,
506};
507
d0e47fba
KH		 508/*----------------------------------------------------------------------*/
509
d4cb7f40 510static s8 queue_priority_mapping[][2] = {
60902a2c
SR		 511 /* {event queue no, Priority} */
512 {0, 3},
513 {1, 7},
514 {-1, -1},
515};
516
a4f86c55
PU		 517static const struct dma_slave_map dm644x_edma_map[] = {
518 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
519 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
520 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
521 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
522 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
523 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
524};
525
d4cb7f40 526static struct edma_soc_info dm644x_edma_pdata = {
bc3ac9f3 527 .queue_priority_mapping = queue_priority_mapping,
f23fe857 528 .default_queue = EVENTQ_1,
a4f86c55
PU		 529 .slave_map = dm644x_edma_map,
530 .slavecnt = ARRAY_SIZE(dm644x_edma_map),
bc3ac9f3
SN		 531};
532
d0e47fba
KH		 533static struct resource edma_resources[] = {
534 {
d4cb7f40 535 .name = "edma3_cc",
d0e47fba
KH		 536 .start = 0x01c00000,
537 .end = 0x01c00000 + SZ_64K - 1,
538 .flags = IORESOURCE_MEM,
539 },
540 {
d4cb7f40 541 .name = "edma3_tc0",
d0e47fba
KH		 542 .start = 0x01c10000,
543 .end = 0x01c10000 + SZ_1K - 1,
544 .flags = IORESOURCE_MEM,
545 },
546 {
d4cb7f40 547 .name = "edma3_tc1",
d0e47fba
KH		 548 .start = 0x01c10400,
549 .end = 0x01c10400 + SZ_1K - 1,
550 .flags = IORESOURCE_MEM,
551 },
552 {
d4cb7f40 553 .name = "edma3_ccint",
d0e47fba
KH		 554 .start = IRQ_CCINT0,
555 .flags = IORESOURCE_IRQ,
556 },
557 {
d4cb7f40 558 .name = "edma3_ccerrint",
d0e47fba
KH		 559 .start = IRQ_CCERRINT,
560 .flags = IORESOURCE_IRQ,
561 },
562 /* not using TC*_ERR */
563};
564
7ab388e8
PU		 565static const struct platform_device_info dm644x_edma_device __initconst = {
566 .name = "edma",
567 .id = 0,
cef5b0da 568 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 569 .res = edma_resources,
570 .num_res = ARRAY_SIZE(edma_resources),
571 .data = &dm644x_edma_pdata,
572 .size_data = sizeof(dm644x_edma_pdata),
d0e47fba
KH		 573};
574
25acf553
C		 575/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
576static struct resource dm644x_asp_resources[] = {
577 {
ee880dbd 578 .name = "mpu",
25acf553
C		 579 .start = DAVINCI_ASP0_BASE,
580 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
581 .flags = IORESOURCE_MEM,
582 },
583 {
584 .start = DAVINCI_DMA_ASP0_TX,
585 .end = DAVINCI_DMA_ASP0_TX,
586 .flags = IORESOURCE_DMA,
587 },
588 {
589 .start = DAVINCI_DMA_ASP0_RX,
590 .end = DAVINCI_DMA_ASP0_RX,
591 .flags = IORESOURCE_DMA,
592 },
593};
594
595static struct platform_device dm644x_asp_device = {
bedad0ca 596 .name = "davinci-mcbsp",
25acf553
C		 597 .id = -1,
598 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
599 .resource = dm644x_asp_resources,
600};
601
51f31cb3
MH		 602#define DM644X_VPSS_BASE 0x01c73400
603
ab8e8df8
MK		 604static struct resource dm644x_vpss_resources[] = {
605 {
606 /* VPSS Base address */
607 .name = "vpss",
51f31cb3
MH		 608 .start = DM644X_VPSS_BASE,
609 .end = DM644X_VPSS_BASE + 0xff,
610 .flags = IORESOURCE_MEM,
ab8e8df8
MK		 611 },
612};
613
614static struct platform_device dm644x_vpss_device = {
615 .name = "vpss",
616 .id = -1,
617 .dev.platform_data = "dm644x_vpss",
618 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
619 .resource = dm644x_vpss_resources,
620};
621
314d7389 622static struct resource dm644x_vpfe_resources[] = {
ab8e8df8
MK		 623 {
624 .start = IRQ_VDINT0,
625 .end = IRQ_VDINT0,
626 .flags = IORESOURCE_IRQ,
627 },
628 {
629 .start = IRQ_VDINT1,
630 .end = IRQ_VDINT1,
631 .flags = IORESOURCE_IRQ,
632 },
77c8b5fb
MK		 633};
634
af946f26 635static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
77c8b5fb
MK		 636static struct resource dm644x_ccdc_resource[] = {
637 /* CCDC Base address */
ab8e8df8
MK		 638 {
639 .start = 0x01c70400,
640 .end = 0x01c70400 + 0xff,
641 .flags = IORESOURCE_MEM,
642 },
643};
644
77c8b5fb
MK		 645static struct platform_device dm644x_ccdc_dev = {
646 .name = "dm644x_ccdc",
647 .id = -1,
648 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
649 .resource = dm644x_ccdc_resource,
650 .dev = {
af946f26 651 .dma_mask = &dm644x_video_dma_mask,
77c8b5fb
MK		 652 .coherent_dma_mask = DMA_BIT_MASK(32),
653 },
654};
655
314d7389 656static struct platform_device dm644x_vpfe_dev = {
ab8e8df8
MK		 657 .name = CAPTURE_DRV_NAME,
658 .id = -1,
314d7389
MH		 659 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
660 .resource = dm644x_vpfe_resources,
ab8e8df8 661 .dev = {
af946f26
MH		 662 .dma_mask = &dm644x_video_dma_mask,
663 .coherent_dma_mask = DMA_BIT_MASK(32),
664 },
665};
666
667#define DM644X_OSD_BASE 0x01c72600
668
669static struct resource dm644x_osd_resources[] = {
670 {
671 .start = DM644X_OSD_BASE,
672 .end = DM644X_OSD_BASE + 0x1ff,
673 .flags = IORESOURCE_MEM,
674 },
675};
676
af946f26 677static struct platform_device dm644x_osd_dev = {
caff80c3 678 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
af946f26
MH		 679 .id = -1,
680 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
681 .resource = dm644x_osd_resources,
682 .dev = {
683 .dma_mask = &dm644x_video_dma_mask,
684 .coherent_dma_mask = DMA_BIT_MASK(32),
af946f26
MH		 685 },
686};
687
688#define DM644X_VENC_BASE 0x01c72400
689
690static struct resource dm644x_venc_resources[] = {
691 {
692 .start = DM644X_VENC_BASE,
693 .end = DM644X_VENC_BASE + 0x17f,
694 .flags = IORESOURCE_MEM,
695 },
696};
697
698#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
699#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
700#define DM644X_VPSS_VENCLKEN BIT(3)
701#define DM644X_VPSS_DACCLKEN BIT(4)
702
703static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
36864082 704 unsigned int pclock)
af946f26
MH		 705{
706 int ret = 0;
707 u32 v = DM644X_VPSS_VENCLKEN;
708
709 switch (type) {
710 case VPBE_ENC_STD:
711 v |= DM644X_VPSS_DACCLKEN;
712 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
713 break;
ef2d41b1 714 case VPBE_ENC_DV_TIMINGS:
36864082 715 if (pclock <= 27000000) {
e37212aa 716 v |= DM644X_VPSS_DACCLKEN;
af946f26 717 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
36864082 718 } else {
af946f26
MH		 719 /*
720 * For HD, use external clock source since
721 * HD requires higher clock rate
722 */
723 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
724 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
af946f26
MH		 725 }
726 break;
727 default:
728 ret = -EINVAL;
729 }
730
731 return ret;
732}
733
734static struct resource dm644x_v4l2_disp_resources[] = {
735 {
736 .start = IRQ_VENCINT,
737 .end = IRQ_VENCINT,
738 .flags = IORESOURCE_IRQ,
739 },
740};
741
742static struct platform_device dm644x_vpbe_display = {
743 .name = "vpbe-v4l2",
744 .id = -1,
745 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
746 .resource = dm644x_v4l2_disp_resources,
747 .dev = {
748 .dma_mask = &dm644x_video_dma_mask,
749 .coherent_dma_mask = DMA_BIT_MASK(32),
750 },
751};
752
753static struct venc_platform_data dm644x_venc_pdata = {
af946f26
MH		 754 .setup_clock = dm644x_venc_setup_clock,
755};
756
757static struct platform_device dm644x_venc_dev = {
caff80c3 758 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
af946f26
MH		 759 .id = -1,
760 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
761 .resource = dm644x_venc_resources,
762 .dev = {
763 .dma_mask = &dm644x_video_dma_mask,
764 .coherent_dma_mask = DMA_BIT_MASK(32),
765 .platform_data = &dm644x_venc_pdata,
766 },
767};
768
769static struct platform_device dm644x_vpbe_dev = {
770 .name = "vpbe_controller",
771 .id = -1,
772 .dev = {
773 .dma_mask = &dm644x_video_dma_mask,
ab8e8df8
MK		 774 .coherent_dma_mask = DMA_BIT_MASK(32),
775 },
776};
777
9cc1515c
PA		 778static struct resource dm644_gpio_resources[] = {
779 { /* registers */
780 .start = DAVINCI_GPIO_BASE,
781 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
782 .flags = IORESOURCE_MEM,
783 },
784 { /* interrupt */
785 .start = IRQ_GPIOBNK0,
786 .end = IRQ_GPIOBNK4,
787 .flags = IORESOURCE_IRQ,
788 },
789};
790
791static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
792 .ngpio = 71,
9cc1515c
PA		 793};
794
795int __init dm644x_gpio_register(void)
796{
797 return davinci_gpio_register(dm644_gpio_resources,
e462f1f5 798 ARRAY_SIZE(dm644_gpio_resources),
9cc1515c
PA		 799 &dm644_gpio_platform_data);
800}
d0e47fba 801/*----------------------------------------------------------------------*/
ac7b75b5 802
79c3c0b7
MG		 803static struct map_desc dm644x_io_desc[] = {
804 {
805 .virtual = IO_VIRT,
806 .pfn = __phys_to_pfn(IO_PHYS),
807 .length = IO_SIZE,
808 .type = MT_DEVICE
809 },
810};
811
b9ab1279
MG		 812/* Contents of JTAG ID register used to identify exact cpu type */
813static struct davinci_id dm644x_ids[] = {
814 {
815 .variant = 0x0,
816 .part_no = 0xb700,
817 .manufacturer = 0x017,
818 .cpu_id = DAVINCI_CPU_ID_DM6446,
819 .name = "dm6446",
820 },
98d0e9fc
RS		 821 {
822 .variant = 0x1,
823 .part_no = 0xb700,
824 .manufacturer = 0x017,
825 .cpu_id = DAVINCI_CPU_ID_DM6446,
826 .name = "dm6446a",
827 },
b9ab1279
MG		 828};
829
e4c822c7 830static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 831
f64691b3
MG		 832/*
833 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
834 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
835 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
836 * T1_TOP: Timer 1, top : <unused>
837 */
28552c2e 838static struct davinci_timer_info dm644x_timer_info = {
f64691b3
MG		 839 .timers = davinci_timer_instance,
840 .clockevent_id = T0_BOT,
841 .clocksource_id = T0_TOP,
842};
843
19955c3d 844static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
65e866a9
MG		 845 {
846 .mapbase = DAVINCI_UART0_BASE,
847 .irq = IRQ_UARTINT0,
848 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
849 UPF_IOREMAP,
850 .iotype = UPIO_MEM,
851 .regshift = 2,
852 },
19955c3d
MP		 853 {
854 .flags = 0,
855 }
856};
857static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
65e866a9
MG		 858 {
859 .mapbase = DAVINCI_UART1_BASE,
860 .irq = IRQ_UARTINT1,
861 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
862 UPF_IOREMAP,
863 .iotype = UPIO_MEM,
864 .regshift = 2,
865 },
19955c3d
MP		 866 {
867 .flags = 0,
868 }
869};
870static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
65e866a9
MG		 871 {
872 .mapbase = DAVINCI_UART2_BASE,
873 .irq = IRQ_UARTINT2,
874 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
875 UPF_IOREMAP,
876 .iotype = UPIO_MEM,
877 .regshift = 2,
878 },
879 {
19955c3d
MP		 880 .flags = 0,
881 }
65e866a9
MG		 882};
883
fcf7157b 884struct platform_device dm644x_serial_device[] = {
19955c3d
MP		 885 {
886 .name = "serial8250",
887 .id = PLAT8250_DEV_PLATFORM,
888 .dev = {
889 .platform_data = dm644x_serial0_platform_data,
890 }
65e866a9 891 },
19955c3d
MP		 892 {
893 .name = "serial8250",
894 .id = PLAT8250_DEV_PLATFORM1,
895 .dev = {
896 .platform_data = dm644x_serial1_platform_data,
897 }
898 },
899 {
900 .name = "serial8250",
901 .id = PLAT8250_DEV_PLATFORM2,
902 .dev = {
903 .platform_data = dm644x_serial2_platform_data,
904 }
905 },
906 {
907 }
65e866a9
MG		 908};
909
ab41910d 910static const struct davinci_soc_info davinci_soc_info_dm644x = {
79c3c0b7
MG		 911 .io_desc = dm644x_io_desc,
912 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
3347db83 913 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 914 .ids = dm644x_ids,
915 .ids_num = ARRAY_SIZE(dm644x_ids),
d81d188c
MG		 916 .psc_bases = dm644x_psc_bases,
917 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
779b0d53 918 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 919 .pinmux_pins = dm644x_pins,
920 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
bd808947 921 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 922 .intc_type = DAVINCI_INTC_TYPE_AINTC,
923 .intc_irq_prios = dm644x_default_priorities,
924 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 925 .timer_info = &dm644x_timer_info,
972412b6 926 .emac_pdata = &dm644x_emac_pdata,
0d04eb47
DB		 927 .sram_dma = 0x00008000,
928 .sram_len = SZ_16K,
79c3c0b7
MG		 929};
930
6bce5efd 931void __init dm644x_init_asp(void)
25acf553
C		 932{
933 davinci_cfg_reg(DM644X_MCBSP);
25acf553
C		 934 platform_device_register(&dm644x_asp_device);
935}
936
d0e47fba
KH		 937void __init dm644x_init(void)
938{
79c3c0b7 939 davinci_common_init(&davinci_soc_info_dm644x);
5cfb19ac 940 davinci_map_sysmod();
96c08173
DL		 941}
942
943void __init dm644x_init_time(void)
944{
a5b1a871
DL		 945#ifdef CONFIG_COMMON_CLK
946 void __iomem *pll1, *psc;
947 struct clk *clk;
948
949 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
950
951 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
952 dm644x_pll1_init(NULL, pll1, NULL);
953
954 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
955 dm644x_psc_init(NULL, psc);
956
957 clk = clk_get(NULL, "timer0");
958
959 davinci_timer_init(clk);
960#else
96c08173 961 davinci_clk_init(dm644x_clks);
a7da5277 962 davinci_timer_init(&timer0_clk);
a5b1a871
DL		 963#endif
964}
965
966static struct resource dm644x_pll2_resources[] = {
967 {
968 .start = DAVINCI_PLL2_BASE,
969 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
970 .flags = IORESOURCE_MEM,
971 },
972};
973
974static struct platform_device dm644x_pll2_device = {
975 .name = "dm644x-pll2",
976 .id = -1,
977 .resource = dm644x_pll2_resources,
978 .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
979};
980
981void __init dm644x_register_clocks(void)
982{
983 /* PLL1 and PSC are registered in dm644x_init_time() */
984 platform_device_register(&dm644x_pll2_device);
d0e47fba
KH		 985}
986
af946f26
MH		 987int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
988 struct vpbe_config *vpbe_cfg)
d0e47fba 989{
af946f26
MH		 990 if (vpfe_cfg || vpbe_cfg)
991 platform_device_register(&dm644x_vpss_device);
992
993 if (vpfe_cfg) {
994 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
995 platform_device_register(&dm644x_ccdc_dev);
996 platform_device_register(&dm644x_vpfe_dev);
af946f26
MH		 997 }
998
999 if (vpbe_cfg) {
1000 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
1001 platform_device_register(&dm644x_osd_dev);
1002 platform_device_register(&dm644x_venc_dev);
1003 platform_device_register(&dm644x_vpbe_dev);
1004 platform_device_register(&dm644x_vpbe_display);
1005 }
12db9588
MH		 1006
1007 return 0;
1008}
1009
8e730c7f 1010void __init dm644x_init_devices(void)
12db9588 1011{
7ab388e8 1012 struct platform_device *edma_pdev;
8e730c7f 1013 int ret;
12db9588 1014
7ab388e8 1015 edma_pdev = platform_device_register_full(&dm644x_edma_device);
8e730c7f 1016 if (IS_ERR(edma_pdev))
7ab388e8 1017 pr_warn("%s: Failed to register eDMA\n", __func__);
d22960c8
CC		 1018
1019 platform_device_register(&dm644x_mdio_device);
972412b6 1020 platform_device_register(&dm644x_emac_device);
d22960c8 1021
1233090c
SN		 1022 ret = davinci_init_wdt();
1023 if (ret)
1024 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1025
d0e47fba 1026}
Linux 6.x block layer and io_uring tree(s)