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d0e47fba KH |
1 | /* |
2 | * TI DaVinci DM644x chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
d0e47fba KH |
11 | #include <linux/init.h> |
12 | #include <linux/clk.h> | |
65e866a9 | 13 | #include <linux/serial_8250.h> |
d0e47fba | 14 | #include <linux/platform_device.h> |
3ad7a42d | 15 | #include <linux/platform_data/edma.h> |
9cc1515c | 16 | #include <linux/platform_data/gpio-davinci.h> |
d0e47fba | 17 | |
79c3c0b7 MG |
18 | #include <asm/mach/map.h> |
19 | ||
d0e47fba | 20 | #include <mach/cputype.h> |
d0e47fba KH |
21 | #include <mach/irqs.h> |
22 | #include <mach/psc.h> | |
23 | #include <mach/mux.h> | |
f64691b3 | 24 | #include <mach/time.h> |
65e866a9 | 25 | #include <mach/serial.h> |
79c3c0b7 | 26 | #include <mach/common.h> |
d0e47fba | 27 | |
39c6d2d1 | 28 | #include "davinci.h" |
d0e47fba KH |
29 | #include "clock.h" |
30 | #include "mux.h" | |
896f66b7 | 31 | #include "asp.h" |
d0e47fba KH |
32 | |
33 | /* | |
34 | * Device specific clocks | |
35 | */ | |
36 | #define DM644X_REF_FREQ 27000000 | |
37 | ||
887b8a93 MH |
38 | #define DM644X_EMAC_BASE 0x01c80000 |
39 | #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000) | |
40 | #define DM644X_EMAC_CNTRL_OFFSET 0x0000 | |
41 | #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000 | |
42 | #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000 | |
43 | #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000 | |
44 | ||
d0e47fba KH |
45 | static struct pll_data pll1_data = { |
46 | .num = 1, | |
47 | .phys_base = DAVINCI_PLL1_BASE, | |
48 | }; | |
49 | ||
50 | static struct pll_data pll2_data = { | |
51 | .num = 2, | |
52 | .phys_base = DAVINCI_PLL2_BASE, | |
53 | }; | |
54 | ||
55 | static struct clk ref_clk = { | |
56 | .name = "ref_clk", | |
57 | .rate = DM644X_REF_FREQ, | |
58 | }; | |
59 | ||
60 | static struct clk pll1_clk = { | |
61 | .name = "pll1", | |
62 | .parent = &ref_clk, | |
63 | .pll_data = &pll1_data, | |
64 | .flags = CLK_PLL, | |
65 | }; | |
66 | ||
67 | static struct clk pll1_sysclk1 = { | |
68 | .name = "pll1_sysclk1", | |
69 | .parent = &pll1_clk, | |
70 | .flags = CLK_PLL, | |
71 | .div_reg = PLLDIV1, | |
72 | }; | |
73 | ||
74 | static struct clk pll1_sysclk2 = { | |
75 | .name = "pll1_sysclk2", | |
76 | .parent = &pll1_clk, | |
77 | .flags = CLK_PLL, | |
78 | .div_reg = PLLDIV2, | |
79 | }; | |
80 | ||
81 | static struct clk pll1_sysclk3 = { | |
82 | .name = "pll1_sysclk3", | |
83 | .parent = &pll1_clk, | |
84 | .flags = CLK_PLL, | |
85 | .div_reg = PLLDIV3, | |
86 | }; | |
87 | ||
88 | static struct clk pll1_sysclk5 = { | |
89 | .name = "pll1_sysclk5", | |
90 | .parent = &pll1_clk, | |
91 | .flags = CLK_PLL, | |
92 | .div_reg = PLLDIV5, | |
93 | }; | |
94 | ||
95 | static struct clk pll1_aux_clk = { | |
96 | .name = "pll1_aux_clk", | |
97 | .parent = &pll1_clk, | |
98 | .flags = CLK_PLL | PRE_PLL, | |
99 | }; | |
100 | ||
101 | static struct clk pll1_sysclkbp = { | |
102 | .name = "pll1_sysclkbp", | |
103 | .parent = &pll1_clk, | |
104 | .flags = CLK_PLL | PRE_PLL, | |
105 | .div_reg = BPDIV | |
106 | }; | |
107 | ||
108 | static struct clk pll2_clk = { | |
109 | .name = "pll2", | |
110 | .parent = &ref_clk, | |
111 | .pll_data = &pll2_data, | |
112 | .flags = CLK_PLL, | |
113 | }; | |
114 | ||
115 | static struct clk pll2_sysclk1 = { | |
116 | .name = "pll2_sysclk1", | |
117 | .parent = &pll2_clk, | |
118 | .flags = CLK_PLL, | |
119 | .div_reg = PLLDIV1, | |
120 | }; | |
121 | ||
122 | static struct clk pll2_sysclk2 = { | |
123 | .name = "pll2_sysclk2", | |
124 | .parent = &pll2_clk, | |
125 | .flags = CLK_PLL, | |
126 | .div_reg = PLLDIV2, | |
127 | }; | |
128 | ||
129 | static struct clk pll2_sysclkbp = { | |
130 | .name = "pll2_sysclkbp", | |
131 | .parent = &pll2_clk, | |
132 | .flags = CLK_PLL | PRE_PLL, | |
133 | .div_reg = BPDIV | |
134 | }; | |
135 | ||
136 | static struct clk dsp_clk = { | |
137 | .name = "dsp", | |
138 | .parent = &pll1_sysclk1, | |
139 | .lpsc = DAVINCI_LPSC_GEM, | |
12221d43 | 140 | .domain = DAVINCI_GPSC_DSPDOMAIN, |
d0e47fba KH |
141 | .usecount = 1, /* REVISIT how to disable? */ |
142 | }; | |
143 | ||
144 | static struct clk arm_clk = { | |
145 | .name = "arm", | |
146 | .parent = &pll1_sysclk2, | |
147 | .lpsc = DAVINCI_LPSC_ARM, | |
148 | .flags = ALWAYS_ENABLED, | |
149 | }; | |
150 | ||
151 | static struct clk vicp_clk = { | |
152 | .name = "vicp", | |
153 | .parent = &pll1_sysclk2, | |
154 | .lpsc = DAVINCI_LPSC_IMCOP, | |
12221d43 | 155 | .domain = DAVINCI_GPSC_DSPDOMAIN, |
d0e47fba KH |
156 | .usecount = 1, /* REVISIT how to disable? */ |
157 | }; | |
158 | ||
159 | static struct clk vpss_master_clk = { | |
160 | .name = "vpss_master", | |
161 | .parent = &pll1_sysclk3, | |
162 | .lpsc = DAVINCI_LPSC_VPSSMSTR, | |
163 | .flags = CLK_PSC, | |
164 | }; | |
165 | ||
166 | static struct clk vpss_slave_clk = { | |
167 | .name = "vpss_slave", | |
168 | .parent = &pll1_sysclk3, | |
169 | .lpsc = DAVINCI_LPSC_VPSSSLV, | |
170 | }; | |
171 | ||
172 | static struct clk uart0_clk = { | |
173 | .name = "uart0", | |
174 | .parent = &pll1_aux_clk, | |
175 | .lpsc = DAVINCI_LPSC_UART0, | |
176 | }; | |
177 | ||
178 | static struct clk uart1_clk = { | |
179 | .name = "uart1", | |
180 | .parent = &pll1_aux_clk, | |
181 | .lpsc = DAVINCI_LPSC_UART1, | |
182 | }; | |
183 | ||
184 | static struct clk uart2_clk = { | |
185 | .name = "uart2", | |
186 | .parent = &pll1_aux_clk, | |
187 | .lpsc = DAVINCI_LPSC_UART2, | |
188 | }; | |
189 | ||
190 | static struct clk emac_clk = { | |
191 | .name = "emac", | |
192 | .parent = &pll1_sysclk5, | |
193 | .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, | |
194 | }; | |
195 | ||
196 | static struct clk i2c_clk = { | |
197 | .name = "i2c", | |
198 | .parent = &pll1_aux_clk, | |
199 | .lpsc = DAVINCI_LPSC_I2C, | |
200 | }; | |
201 | ||
202 | static struct clk ide_clk = { | |
203 | .name = "ide", | |
204 | .parent = &pll1_sysclk5, | |
205 | .lpsc = DAVINCI_LPSC_ATA, | |
206 | }; | |
207 | ||
208 | static struct clk asp_clk = { | |
209 | .name = "asp0", | |
210 | .parent = &pll1_sysclk5, | |
211 | .lpsc = DAVINCI_LPSC_McBSP, | |
212 | }; | |
213 | ||
214 | static struct clk mmcsd_clk = { | |
215 | .name = "mmcsd", | |
216 | .parent = &pll1_sysclk5, | |
217 | .lpsc = DAVINCI_LPSC_MMC_SD, | |
218 | }; | |
219 | ||
220 | static struct clk spi_clk = { | |
221 | .name = "spi", | |
222 | .parent = &pll1_sysclk5, | |
223 | .lpsc = DAVINCI_LPSC_SPI, | |
224 | }; | |
225 | ||
226 | static struct clk gpio_clk = { | |
227 | .name = "gpio", | |
228 | .parent = &pll1_sysclk5, | |
229 | .lpsc = DAVINCI_LPSC_GPIO, | |
230 | }; | |
231 | ||
232 | static struct clk usb_clk = { | |
233 | .name = "usb", | |
234 | .parent = &pll1_sysclk5, | |
235 | .lpsc = DAVINCI_LPSC_USB, | |
236 | }; | |
237 | ||
238 | static struct clk vlynq_clk = { | |
239 | .name = "vlynq", | |
240 | .parent = &pll1_sysclk5, | |
241 | .lpsc = DAVINCI_LPSC_VLYNQ, | |
242 | }; | |
243 | ||
244 | static struct clk aemif_clk = { | |
245 | .name = "aemif", | |
246 | .parent = &pll1_sysclk5, | |
247 | .lpsc = DAVINCI_LPSC_AEMIF, | |
248 | }; | |
249 | ||
250 | static struct clk pwm0_clk = { | |
251 | .name = "pwm0", | |
252 | .parent = &pll1_aux_clk, | |
253 | .lpsc = DAVINCI_LPSC_PWM0, | |
254 | }; | |
255 | ||
256 | static struct clk pwm1_clk = { | |
257 | .name = "pwm1", | |
258 | .parent = &pll1_aux_clk, | |
259 | .lpsc = DAVINCI_LPSC_PWM1, | |
260 | }; | |
261 | ||
262 | static struct clk pwm2_clk = { | |
263 | .name = "pwm2", | |
264 | .parent = &pll1_aux_clk, | |
265 | .lpsc = DAVINCI_LPSC_PWM2, | |
266 | }; | |
267 | ||
268 | static struct clk timer0_clk = { | |
269 | .name = "timer0", | |
270 | .parent = &pll1_aux_clk, | |
271 | .lpsc = DAVINCI_LPSC_TIMER0, | |
272 | }; | |
273 | ||
274 | static struct clk timer1_clk = { | |
275 | .name = "timer1", | |
276 | .parent = &pll1_aux_clk, | |
277 | .lpsc = DAVINCI_LPSC_TIMER1, | |
278 | }; | |
279 | ||
280 | static struct clk timer2_clk = { | |
281 | .name = "timer2", | |
282 | .parent = &pll1_aux_clk, | |
283 | .lpsc = DAVINCI_LPSC_TIMER2, | |
e9c54999 | 284 | .usecount = 1, /* REVISIT: why can't this be disabled? */ |
d0e47fba KH |
285 | }; |
286 | ||
28552c2e | 287 | static struct clk_lookup dm644x_clks[] = { |
d0e47fba KH |
288 | CLK(NULL, "ref", &ref_clk), |
289 | CLK(NULL, "pll1", &pll1_clk), | |
290 | CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), | |
291 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | |
292 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | |
293 | CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | |
294 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
295 | CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), | |
296 | CLK(NULL, "pll2", &pll2_clk), | |
297 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | |
298 | CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), | |
299 | CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), | |
300 | CLK(NULL, "dsp", &dsp_clk), | |
301 | CLK(NULL, "arm", &arm_clk), | |
302 | CLK(NULL, "vicp", &vicp_clk), | |
9a3e89b1 LP |
303 | CLK("vpss", "master", &vpss_master_clk), |
304 | CLK("vpss", "slave", &vpss_slave_clk), | |
d0e47fba | 305 | CLK(NULL, "arm", &arm_clk), |
19955c3d MP |
306 | CLK("serial8250.0", NULL, &uart0_clk), |
307 | CLK("serial8250.1", NULL, &uart1_clk), | |
308 | CLK("serial8250.2", NULL, &uart2_clk), | |
d0e47fba | 309 | CLK("davinci_emac.1", NULL, &emac_clk), |
46c18334 | 310 | CLK("davinci_mdio.0", "fck", &emac_clk), |
d0e47fba KH |
311 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
312 | CLK("palm_bk3710", NULL, &ide_clk), | |
bedad0ca | 313 | CLK("davinci-mcbsp", NULL, &asp_clk), |
d7ca4c75 | 314 | CLK("dm6441-mmc.0", NULL, &mmcsd_clk), |
d0e47fba KH |
315 | CLK(NULL, "spi", &spi_clk), |
316 | CLK(NULL, "gpio", &gpio_clk), | |
317 | CLK(NULL, "usb", &usb_clk), | |
318 | CLK(NULL, "vlynq", &vlynq_clk), | |
319 | CLK(NULL, "aemif", &aemif_clk), | |
320 | CLK(NULL, "pwm0", &pwm0_clk), | |
321 | CLK(NULL, "pwm1", &pwm1_clk), | |
322 | CLK(NULL, "pwm2", &pwm2_clk), | |
323 | CLK(NULL, "timer0", &timer0_clk), | |
324 | CLK(NULL, "timer1", &timer1_clk), | |
84374812 | 325 | CLK("davinci-wdt", NULL, &timer2_clk), |
d0e47fba KH |
326 | CLK(NULL, NULL, NULL), |
327 | }; | |
328 | ||
972412b6 MG |
329 | static struct emac_platform_data dm644x_emac_pdata = { |
330 | .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, | |
331 | .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, | |
332 | .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, | |
972412b6 MG |
333 | .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, |
334 | .version = EMAC_VERSION_1, | |
335 | }; | |
d0e47fba KH |
336 | |
337 | static struct resource dm644x_emac_resources[] = { | |
338 | { | |
339 | .start = DM644X_EMAC_BASE, | |
d22960c8 | 340 | .end = DM644X_EMAC_BASE + SZ_16K - 1, |
d0e47fba KH |
341 | .flags = IORESOURCE_MEM, |
342 | }, | |
343 | { | |
344 | .start = IRQ_EMACINT, | |
345 | .end = IRQ_EMACINT, | |
346 | .flags = IORESOURCE_IRQ, | |
347 | }, | |
348 | }; | |
349 | ||
350 | static struct platform_device dm644x_emac_device = { | |
351 | .name = "davinci_emac", | |
352 | .id = 1, | |
972412b6 MG |
353 | .dev = { |
354 | .platform_data = &dm644x_emac_pdata, | |
355 | }, | |
d0e47fba KH |
356 | .num_resources = ARRAY_SIZE(dm644x_emac_resources), |
357 | .resource = dm644x_emac_resources, | |
358 | }; | |
359 | ||
d22960c8 CC |
360 | static struct resource dm644x_mdio_resources[] = { |
361 | { | |
362 | .start = DM644X_EMAC_MDIO_BASE, | |
363 | .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1, | |
364 | .flags = IORESOURCE_MEM, | |
365 | }, | |
366 | }; | |
367 | ||
368 | static struct platform_device dm644x_mdio_device = { | |
369 | .name = "davinci_mdio", | |
370 | .id = 0, | |
371 | .num_resources = ARRAY_SIZE(dm644x_mdio_resources), | |
372 | .resource = dm644x_mdio_resources, | |
373 | }; | |
374 | ||
d0e47fba KH |
375 | /* |
376 | * Device specific mux setup | |
377 | * | |
378 | * soc description mux mode mode mux dbg | |
379 | * reg offset mask mode | |
380 | */ | |
381 | static const struct mux_config dm644x_pins[] = { | |
0e585952 | 382 | #ifdef CONFIG_DAVINCI_MUX |
d0e47fba KH |
383 | MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) |
384 | MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) | |
385 | MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) | |
386 | ||
387 | MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) | |
388 | ||
389 | MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) | |
c16fe267 AP |
390 | MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true) |
391 | MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true) | |
392 | MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true) | |
393 | MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true) | |
394 | MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true) | |
d0e47fba KH |
395 | |
396 | MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) | |
397 | ||
398 | MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) | |
399 | ||
400 | MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) | |
401 | ||
402 | MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true) | |
403 | MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true) | |
404 | ||
405 | MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) | |
406 | ||
407 | MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) | |
408 | ||
409 | MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) | |
410 | ||
411 | MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) | |
412 | MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) | |
413 | MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) | |
414 | ||
415 | MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) | |
416 | ||
417 | MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) | |
418 | ||
419 | MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) | |
420 | MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) | |
421 | MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) | |
422 | MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) | |
423 | ||
424 | MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) | |
425 | ||
426 | MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) | |
427 | MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) | |
0e585952 | 428 | #endif |
d0e47fba KH |
429 | }; |
430 | ||
673dd36f MG |
431 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ |
432 | static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { | |
433 | [IRQ_VDINT0] = 2, | |
434 | [IRQ_VDINT1] = 6, | |
435 | [IRQ_VDINT2] = 6, | |
436 | [IRQ_HISTINT] = 6, | |
437 | [IRQ_H3AINT] = 6, | |
438 | [IRQ_PRVUINT] = 6, | |
439 | [IRQ_RSZINT] = 6, | |
440 | [7] = 7, | |
441 | [IRQ_VENCINT] = 6, | |
442 | [IRQ_ASQINT] = 6, | |
443 | [IRQ_IMXINT] = 6, | |
444 | [IRQ_VLCDINT] = 6, | |
445 | [IRQ_USBINT] = 4, | |
446 | [IRQ_EMACINT] = 4, | |
447 | [14] = 7, | |
448 | [15] = 7, | |
449 | [IRQ_CCINT0] = 5, /* dma */ | |
450 | [IRQ_CCERRINT] = 5, /* dma */ | |
451 | [IRQ_TCERRINT0] = 5, /* dma */ | |
452 | [IRQ_TCERRINT] = 5, /* dma */ | |
453 | [IRQ_PSCIN] = 7, | |
454 | [21] = 7, | |
455 | [IRQ_IDE] = 4, | |
456 | [23] = 7, | |
457 | [IRQ_MBXINT] = 7, | |
458 | [IRQ_MBRINT] = 7, | |
459 | [IRQ_MMCINT] = 7, | |
460 | [IRQ_SDIOINT] = 7, | |
461 | [28] = 7, | |
462 | [IRQ_DDRINT] = 7, | |
463 | [IRQ_AEMIFINT] = 7, | |
464 | [IRQ_VLQINT] = 4, | |
465 | [IRQ_TINT0_TINT12] = 2, /* clockevent */ | |
466 | [IRQ_TINT0_TINT34] = 2, /* clocksource */ | |
467 | [IRQ_TINT1_TINT12] = 7, /* DSP timer */ | |
468 | [IRQ_TINT1_TINT34] = 7, /* system tick */ | |
469 | [IRQ_PWMINT0] = 7, | |
470 | [IRQ_PWMINT1] = 7, | |
471 | [IRQ_PWMINT2] = 7, | |
472 | [IRQ_I2C] = 3, | |
473 | [IRQ_UARTINT0] = 3, | |
474 | [IRQ_UARTINT1] = 3, | |
475 | [IRQ_UARTINT2] = 3, | |
476 | [IRQ_SPINT0] = 3, | |
477 | [IRQ_SPINT1] = 3, | |
478 | [45] = 7, | |
479 | [IRQ_DSP2ARM0] = 4, | |
480 | [IRQ_DSP2ARM1] = 4, | |
481 | [IRQ_GPIO0] = 7, | |
482 | [IRQ_GPIO1] = 7, | |
483 | [IRQ_GPIO2] = 7, | |
484 | [IRQ_GPIO3] = 7, | |
485 | [IRQ_GPIO4] = 7, | |
486 | [IRQ_GPIO5] = 7, | |
487 | [IRQ_GPIO6] = 7, | |
488 | [IRQ_GPIO7] = 7, | |
489 | [IRQ_GPIOBNK0] = 7, | |
490 | [IRQ_GPIOBNK1] = 7, | |
491 | [IRQ_GPIOBNK2] = 7, | |
492 | [IRQ_GPIOBNK3] = 7, | |
493 | [IRQ_GPIOBNK4] = 7, | |
494 | [IRQ_COMMTX] = 7, | |
495 | [IRQ_COMMRX] = 7, | |
496 | [IRQ_EMUINT] = 7, | |
497 | }; | |
498 | ||
d0e47fba KH |
499 | /*----------------------------------------------------------------------*/ |
500 | ||
d4cb7f40 | 501 | static s8 queue_priority_mapping[][2] = { |
60902a2c SR |
502 | /* {event queue no, Priority} */ |
503 | {0, 3}, | |
504 | {1, 7}, | |
505 | {-1, -1}, | |
506 | }; | |
507 | ||
d4cb7f40 | 508 | static struct edma_soc_info dm644x_edma_pdata = { |
bc3ac9f3 | 509 | .queue_priority_mapping = queue_priority_mapping, |
f23fe857 | 510 | .default_queue = EVENTQ_1, |
bc3ac9f3 SN |
511 | }; |
512 | ||
d0e47fba KH |
513 | static struct resource edma_resources[] = { |
514 | { | |
d4cb7f40 | 515 | .name = "edma3_cc", |
d0e47fba KH |
516 | .start = 0x01c00000, |
517 | .end = 0x01c00000 + SZ_64K - 1, | |
518 | .flags = IORESOURCE_MEM, | |
519 | }, | |
520 | { | |
d4cb7f40 | 521 | .name = "edma3_tc0", |
d0e47fba KH |
522 | .start = 0x01c10000, |
523 | .end = 0x01c10000 + SZ_1K - 1, | |
524 | .flags = IORESOURCE_MEM, | |
525 | }, | |
526 | { | |
d4cb7f40 | 527 | .name = "edma3_tc1", |
d0e47fba KH |
528 | .start = 0x01c10400, |
529 | .end = 0x01c10400 + SZ_1K - 1, | |
530 | .flags = IORESOURCE_MEM, | |
531 | }, | |
532 | { | |
d4cb7f40 | 533 | .name = "edma3_ccint", |
d0e47fba KH |
534 | .start = IRQ_CCINT0, |
535 | .flags = IORESOURCE_IRQ, | |
536 | }, | |
537 | { | |
d4cb7f40 | 538 | .name = "edma3_ccerrint", |
d0e47fba KH |
539 | .start = IRQ_CCERRINT, |
540 | .flags = IORESOURCE_IRQ, | |
541 | }, | |
542 | /* not using TC*_ERR */ | |
543 | }; | |
544 | ||
7ab388e8 PU |
545 | static const struct platform_device_info dm644x_edma_device __initconst = { |
546 | .name = "edma", | |
547 | .id = 0, | |
548 | .res = edma_resources, | |
549 | .num_res = ARRAY_SIZE(edma_resources), | |
550 | .data = &dm644x_edma_pdata, | |
551 | .size_data = sizeof(dm644x_edma_pdata), | |
d0e47fba KH |
552 | }; |
553 | ||
25acf553 C |
554 | /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ |
555 | static struct resource dm644x_asp_resources[] = { | |
556 | { | |
ee880dbd | 557 | .name = "mpu", |
25acf553 C |
558 | .start = DAVINCI_ASP0_BASE, |
559 | .end = DAVINCI_ASP0_BASE + SZ_8K - 1, | |
560 | .flags = IORESOURCE_MEM, | |
561 | }, | |
562 | { | |
563 | .start = DAVINCI_DMA_ASP0_TX, | |
564 | .end = DAVINCI_DMA_ASP0_TX, | |
565 | .flags = IORESOURCE_DMA, | |
566 | }, | |
567 | { | |
568 | .start = DAVINCI_DMA_ASP0_RX, | |
569 | .end = DAVINCI_DMA_ASP0_RX, | |
570 | .flags = IORESOURCE_DMA, | |
571 | }, | |
572 | }; | |
573 | ||
574 | static struct platform_device dm644x_asp_device = { | |
bedad0ca | 575 | .name = "davinci-mcbsp", |
25acf553 C |
576 | .id = -1, |
577 | .num_resources = ARRAY_SIZE(dm644x_asp_resources), | |
578 | .resource = dm644x_asp_resources, | |
579 | }; | |
580 | ||
51f31cb3 MH |
581 | #define DM644X_VPSS_BASE 0x01c73400 |
582 | ||
ab8e8df8 MK |
583 | static struct resource dm644x_vpss_resources[] = { |
584 | { | |
585 | /* VPSS Base address */ | |
586 | .name = "vpss", | |
51f31cb3 MH |
587 | .start = DM644X_VPSS_BASE, |
588 | .end = DM644X_VPSS_BASE + 0xff, | |
589 | .flags = IORESOURCE_MEM, | |
ab8e8df8 MK |
590 | }, |
591 | }; | |
592 | ||
593 | static struct platform_device dm644x_vpss_device = { | |
594 | .name = "vpss", | |
595 | .id = -1, | |
596 | .dev.platform_data = "dm644x_vpss", | |
597 | .num_resources = ARRAY_SIZE(dm644x_vpss_resources), | |
598 | .resource = dm644x_vpss_resources, | |
599 | }; | |
600 | ||
314d7389 | 601 | static struct resource dm644x_vpfe_resources[] = { |
ab8e8df8 MK |
602 | { |
603 | .start = IRQ_VDINT0, | |
604 | .end = IRQ_VDINT0, | |
605 | .flags = IORESOURCE_IRQ, | |
606 | }, | |
607 | { | |
608 | .start = IRQ_VDINT1, | |
609 | .end = IRQ_VDINT1, | |
610 | .flags = IORESOURCE_IRQ, | |
611 | }, | |
77c8b5fb MK |
612 | }; |
613 | ||
af946f26 | 614 | static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32); |
77c8b5fb MK |
615 | static struct resource dm644x_ccdc_resource[] = { |
616 | /* CCDC Base address */ | |
ab8e8df8 MK |
617 | { |
618 | .start = 0x01c70400, | |
619 | .end = 0x01c70400 + 0xff, | |
620 | .flags = IORESOURCE_MEM, | |
621 | }, | |
622 | }; | |
623 | ||
77c8b5fb MK |
624 | static struct platform_device dm644x_ccdc_dev = { |
625 | .name = "dm644x_ccdc", | |
626 | .id = -1, | |
627 | .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), | |
628 | .resource = dm644x_ccdc_resource, | |
629 | .dev = { | |
af946f26 | 630 | .dma_mask = &dm644x_video_dma_mask, |
77c8b5fb MK |
631 | .coherent_dma_mask = DMA_BIT_MASK(32), |
632 | }, | |
633 | }; | |
634 | ||
314d7389 | 635 | static struct platform_device dm644x_vpfe_dev = { |
ab8e8df8 MK |
636 | .name = CAPTURE_DRV_NAME, |
637 | .id = -1, | |
314d7389 MH |
638 | .num_resources = ARRAY_SIZE(dm644x_vpfe_resources), |
639 | .resource = dm644x_vpfe_resources, | |
ab8e8df8 | 640 | .dev = { |
af946f26 MH |
641 | .dma_mask = &dm644x_video_dma_mask, |
642 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
643 | }, | |
644 | }; | |
645 | ||
646 | #define DM644X_OSD_BASE 0x01c72600 | |
647 | ||
648 | static struct resource dm644x_osd_resources[] = { | |
649 | { | |
650 | .start = DM644X_OSD_BASE, | |
651 | .end = DM644X_OSD_BASE + 0x1ff, | |
652 | .flags = IORESOURCE_MEM, | |
653 | }, | |
654 | }; | |
655 | ||
af946f26 | 656 | static struct platform_device dm644x_osd_dev = { |
caff80c3 | 657 | .name = DM644X_VPBE_OSD_SUBDEV_NAME, |
af946f26 MH |
658 | .id = -1, |
659 | .num_resources = ARRAY_SIZE(dm644x_osd_resources), | |
660 | .resource = dm644x_osd_resources, | |
661 | .dev = { | |
662 | .dma_mask = &dm644x_video_dma_mask, | |
663 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
af946f26 MH |
664 | }, |
665 | }; | |
666 | ||
667 | #define DM644X_VENC_BASE 0x01c72400 | |
668 | ||
669 | static struct resource dm644x_venc_resources[] = { | |
670 | { | |
671 | .start = DM644X_VENC_BASE, | |
672 | .end = DM644X_VENC_BASE + 0x17f, | |
673 | .flags = IORESOURCE_MEM, | |
674 | }, | |
675 | }; | |
676 | ||
677 | #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0) | |
678 | #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1) | |
679 | #define DM644X_VPSS_VENCLKEN BIT(3) | |
680 | #define DM644X_VPSS_DACCLKEN BIT(4) | |
681 | ||
682 | static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, | |
36864082 | 683 | unsigned int pclock) |
af946f26 MH |
684 | { |
685 | int ret = 0; | |
686 | u32 v = DM644X_VPSS_VENCLKEN; | |
687 | ||
688 | switch (type) { | |
689 | case VPBE_ENC_STD: | |
690 | v |= DM644X_VPSS_DACCLKEN; | |
691 | writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); | |
692 | break; | |
ef2d41b1 | 693 | case VPBE_ENC_DV_TIMINGS: |
36864082 | 694 | if (pclock <= 27000000) { |
e37212aa | 695 | v |= DM644X_VPSS_DACCLKEN; |
af946f26 | 696 | writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); |
36864082 | 697 | } else { |
af946f26 MH |
698 | /* |
699 | * For HD, use external clock source since | |
700 | * HD requires higher clock rate | |
701 | */ | |
702 | v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE; | |
703 | writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); | |
af946f26 MH |
704 | } |
705 | break; | |
706 | default: | |
707 | ret = -EINVAL; | |
708 | } | |
709 | ||
710 | return ret; | |
711 | } | |
712 | ||
713 | static struct resource dm644x_v4l2_disp_resources[] = { | |
714 | { | |
715 | .start = IRQ_VENCINT, | |
716 | .end = IRQ_VENCINT, | |
717 | .flags = IORESOURCE_IRQ, | |
718 | }, | |
719 | }; | |
720 | ||
721 | static struct platform_device dm644x_vpbe_display = { | |
722 | .name = "vpbe-v4l2", | |
723 | .id = -1, | |
724 | .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources), | |
725 | .resource = dm644x_v4l2_disp_resources, | |
726 | .dev = { | |
727 | .dma_mask = &dm644x_video_dma_mask, | |
728 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
729 | }, | |
730 | }; | |
731 | ||
732 | static struct venc_platform_data dm644x_venc_pdata = { | |
af946f26 MH |
733 | .setup_clock = dm644x_venc_setup_clock, |
734 | }; | |
735 | ||
736 | static struct platform_device dm644x_venc_dev = { | |
caff80c3 | 737 | .name = DM644X_VPBE_VENC_SUBDEV_NAME, |
af946f26 MH |
738 | .id = -1, |
739 | .num_resources = ARRAY_SIZE(dm644x_venc_resources), | |
740 | .resource = dm644x_venc_resources, | |
741 | .dev = { | |
742 | .dma_mask = &dm644x_video_dma_mask, | |
743 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
744 | .platform_data = &dm644x_venc_pdata, | |
745 | }, | |
746 | }; | |
747 | ||
748 | static struct platform_device dm644x_vpbe_dev = { | |
749 | .name = "vpbe_controller", | |
750 | .id = -1, | |
751 | .dev = { | |
752 | .dma_mask = &dm644x_video_dma_mask, | |
ab8e8df8 MK |
753 | .coherent_dma_mask = DMA_BIT_MASK(32), |
754 | }, | |
755 | }; | |
756 | ||
9cc1515c PA |
757 | static struct resource dm644_gpio_resources[] = { |
758 | { /* registers */ | |
759 | .start = DAVINCI_GPIO_BASE, | |
760 | .end = DAVINCI_GPIO_BASE + SZ_4K - 1, | |
761 | .flags = IORESOURCE_MEM, | |
762 | }, | |
763 | { /* interrupt */ | |
764 | .start = IRQ_GPIOBNK0, | |
765 | .end = IRQ_GPIOBNK4, | |
766 | .flags = IORESOURCE_IRQ, | |
767 | }, | |
768 | }; | |
769 | ||
770 | static struct davinci_gpio_platform_data dm644_gpio_platform_data = { | |
771 | .ngpio = 71, | |
9cc1515c PA |
772 | }; |
773 | ||
774 | int __init dm644x_gpio_register(void) | |
775 | { | |
776 | return davinci_gpio_register(dm644_gpio_resources, | |
e462f1f5 | 777 | ARRAY_SIZE(dm644_gpio_resources), |
9cc1515c PA |
778 | &dm644_gpio_platform_data); |
779 | } | |
d0e47fba | 780 | /*----------------------------------------------------------------------*/ |
ac7b75b5 | 781 | |
79c3c0b7 MG |
782 | static struct map_desc dm644x_io_desc[] = { |
783 | { | |
784 | .virtual = IO_VIRT, | |
785 | .pfn = __phys_to_pfn(IO_PHYS), | |
786 | .length = IO_SIZE, | |
787 | .type = MT_DEVICE | |
788 | }, | |
789 | }; | |
790 | ||
b9ab1279 MG |
791 | /* Contents of JTAG ID register used to identify exact cpu type */ |
792 | static struct davinci_id dm644x_ids[] = { | |
793 | { | |
794 | .variant = 0x0, | |
795 | .part_no = 0xb700, | |
796 | .manufacturer = 0x017, | |
797 | .cpu_id = DAVINCI_CPU_ID_DM6446, | |
798 | .name = "dm6446", | |
799 | }, | |
98d0e9fc RS |
800 | { |
801 | .variant = 0x1, | |
802 | .part_no = 0xb700, | |
803 | .manufacturer = 0x017, | |
804 | .cpu_id = DAVINCI_CPU_ID_DM6446, | |
805 | .name = "dm6446a", | |
806 | }, | |
b9ab1279 MG |
807 | }; |
808 | ||
e4c822c7 | 809 | static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; |
d81d188c | 810 | |
f64691b3 MG |
811 | /* |
812 | * T0_BOT: Timer 0, bottom: clockevent source for hrtimers | |
813 | * T0_TOP: Timer 0, top : clocksource for generic timekeeping | |
814 | * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) | |
815 | * T1_TOP: Timer 1, top : <unused> | |
816 | */ | |
28552c2e | 817 | static struct davinci_timer_info dm644x_timer_info = { |
f64691b3 MG |
818 | .timers = davinci_timer_instance, |
819 | .clockevent_id = T0_BOT, | |
820 | .clocksource_id = T0_TOP, | |
821 | }; | |
822 | ||
19955c3d | 823 | static struct plat_serial8250_port dm644x_serial0_platform_data[] = { |
65e866a9 MG |
824 | { |
825 | .mapbase = DAVINCI_UART0_BASE, | |
826 | .irq = IRQ_UARTINT0, | |
827 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
828 | UPF_IOREMAP, | |
829 | .iotype = UPIO_MEM, | |
830 | .regshift = 2, | |
831 | }, | |
19955c3d MP |
832 | { |
833 | .flags = 0, | |
834 | } | |
835 | }; | |
836 | static struct plat_serial8250_port dm644x_serial1_platform_data[] = { | |
65e866a9 MG |
837 | { |
838 | .mapbase = DAVINCI_UART1_BASE, | |
839 | .irq = IRQ_UARTINT1, | |
840 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
841 | UPF_IOREMAP, | |
842 | .iotype = UPIO_MEM, | |
843 | .regshift = 2, | |
844 | }, | |
19955c3d MP |
845 | { |
846 | .flags = 0, | |
847 | } | |
848 | }; | |
849 | static struct plat_serial8250_port dm644x_serial2_platform_data[] = { | |
65e866a9 MG |
850 | { |
851 | .mapbase = DAVINCI_UART2_BASE, | |
852 | .irq = IRQ_UARTINT2, | |
853 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
854 | UPF_IOREMAP, | |
855 | .iotype = UPIO_MEM, | |
856 | .regshift = 2, | |
857 | }, | |
858 | { | |
19955c3d MP |
859 | .flags = 0, |
860 | } | |
65e866a9 MG |
861 | }; |
862 | ||
fcf7157b | 863 | struct platform_device dm644x_serial_device[] = { |
19955c3d MP |
864 | { |
865 | .name = "serial8250", | |
866 | .id = PLAT8250_DEV_PLATFORM, | |
867 | .dev = { | |
868 | .platform_data = dm644x_serial0_platform_data, | |
869 | } | |
65e866a9 | 870 | }, |
19955c3d MP |
871 | { |
872 | .name = "serial8250", | |
873 | .id = PLAT8250_DEV_PLATFORM1, | |
874 | .dev = { | |
875 | .platform_data = dm644x_serial1_platform_data, | |
876 | } | |
877 | }, | |
878 | { | |
879 | .name = "serial8250", | |
880 | .id = PLAT8250_DEV_PLATFORM2, | |
881 | .dev = { | |
882 | .platform_data = dm644x_serial2_platform_data, | |
883 | } | |
884 | }, | |
885 | { | |
886 | } | |
65e866a9 MG |
887 | }; |
888 | ||
79c3c0b7 MG |
889 | static struct davinci_soc_info davinci_soc_info_dm644x = { |
890 | .io_desc = dm644x_io_desc, | |
891 | .io_desc_num = ARRAY_SIZE(dm644x_io_desc), | |
3347db83 | 892 | .jtag_id_reg = 0x01c40028, |
b9ab1279 MG |
893 | .ids = dm644x_ids, |
894 | .ids_num = ARRAY_SIZE(dm644x_ids), | |
66e0c399 | 895 | .cpu_clks = dm644x_clks, |
d81d188c MG |
896 | .psc_bases = dm644x_psc_bases, |
897 | .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), | |
779b0d53 | 898 | .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, |
0e585952 MG |
899 | .pinmux_pins = dm644x_pins, |
900 | .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), | |
bd808947 | 901 | .intc_base = DAVINCI_ARM_INTC_BASE, |
673dd36f MG |
902 | .intc_type = DAVINCI_INTC_TYPE_AINTC, |
903 | .intc_irq_prios = dm644x_default_priorities, | |
904 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | |
f64691b3 | 905 | .timer_info = &dm644x_timer_info, |
972412b6 | 906 | .emac_pdata = &dm644x_emac_pdata, |
0d04eb47 DB |
907 | .sram_dma = 0x00008000, |
908 | .sram_len = SZ_16K, | |
79c3c0b7 MG |
909 | }; |
910 | ||
25acf553 C |
911 | void __init dm644x_init_asp(struct snd_platform_data *pdata) |
912 | { | |
913 | davinci_cfg_reg(DM644X_MCBSP); | |
914 | dm644x_asp_device.dev.platform_data = pdata; | |
915 | platform_device_register(&dm644x_asp_device); | |
916 | } | |
917 | ||
d0e47fba KH |
918 | void __init dm644x_init(void) |
919 | { | |
79c3c0b7 | 920 | davinci_common_init(&davinci_soc_info_dm644x); |
5cfb19ac | 921 | davinci_map_sysmod(); |
d0e47fba KH |
922 | } |
923 | ||
af946f26 MH |
924 | int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, |
925 | struct vpbe_config *vpbe_cfg) | |
d0e47fba | 926 | { |
af946f26 MH |
927 | if (vpfe_cfg || vpbe_cfg) |
928 | platform_device_register(&dm644x_vpss_device); | |
929 | ||
930 | if (vpfe_cfg) { | |
931 | dm644x_vpfe_dev.dev.platform_data = vpfe_cfg; | |
932 | platform_device_register(&dm644x_ccdc_dev); | |
933 | platform_device_register(&dm644x_vpfe_dev); | |
af946f26 MH |
934 | } |
935 | ||
936 | if (vpbe_cfg) { | |
937 | dm644x_vpbe_dev.dev.platform_data = vpbe_cfg; | |
938 | platform_device_register(&dm644x_osd_dev); | |
939 | platform_device_register(&dm644x_venc_dev); | |
940 | platform_device_register(&dm644x_vpbe_dev); | |
941 | platform_device_register(&dm644x_vpbe_display); | |
942 | } | |
12db9588 MH |
943 | |
944 | return 0; | |
945 | } | |
946 | ||
947 | static int __init dm644x_init_devices(void) | |
948 | { | |
7ab388e8 | 949 | struct platform_device *edma_pdev; |
1233090c SN |
950 | int ret = 0; |
951 | ||
12db9588 MH |
952 | if (!cpu_is_davinci_dm644x()) |
953 | return 0; | |
954 | ||
7ab388e8 PU |
955 | edma_pdev = platform_device_register_full(&dm644x_edma_device); |
956 | if (IS_ERR(edma_pdev)) { | |
957 | pr_warn("%s: Failed to register eDMA\n", __func__); | |
958 | return PTR_ERR(edma_pdev); | |
959 | } | |
d22960c8 CC |
960 | |
961 | platform_device_register(&dm644x_mdio_device); | |
972412b6 | 962 | platform_device_register(&dm644x_emac_device); |
d22960c8 | 963 | |
1233090c SN |
964 | ret = davinci_init_wdt(); |
965 | if (ret) | |
966 | pr_warn("%s: watchdog init failed: %d\n", __func__, ret); | |
967 | ||
968 | return ret; | |
d0e47fba KH |
969 | } |
970 | postcore_initcall(dm644x_init_devices); |