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d0e47fba KH |
1 | /* |
2 | * TI DaVinci DM644x chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
d0e47fba KH |
11 | #include <linux/init.h> |
12 | #include <linux/clk.h> | |
65e866a9 | 13 | #include <linux/serial_8250.h> |
d0e47fba | 14 | #include <linux/platform_device.h> |
a994955c | 15 | #include <linux/gpio.h> |
d0e47fba | 16 | |
79c3c0b7 MG |
17 | #include <asm/mach/map.h> |
18 | ||
d0e47fba | 19 | #include <mach/dm644x.h> |
d0e47fba KH |
20 | #include <mach/cputype.h> |
21 | #include <mach/edma.h> | |
22 | #include <mach/irqs.h> | |
23 | #include <mach/psc.h> | |
24 | #include <mach/mux.h> | |
f64691b3 | 25 | #include <mach/time.h> |
65e866a9 | 26 | #include <mach/serial.h> |
79c3c0b7 | 27 | #include <mach/common.h> |
25acf553 | 28 | #include <mach/asp.h> |
d0e47fba KH |
29 | |
30 | #include "clock.h" | |
31 | #include "mux.h" | |
32 | ||
33 | /* | |
34 | * Device specific clocks | |
35 | */ | |
36 | #define DM644X_REF_FREQ 27000000 | |
37 | ||
38 | static struct pll_data pll1_data = { | |
39 | .num = 1, | |
40 | .phys_base = DAVINCI_PLL1_BASE, | |
41 | }; | |
42 | ||
43 | static struct pll_data pll2_data = { | |
44 | .num = 2, | |
45 | .phys_base = DAVINCI_PLL2_BASE, | |
46 | }; | |
47 | ||
48 | static struct clk ref_clk = { | |
49 | .name = "ref_clk", | |
50 | .rate = DM644X_REF_FREQ, | |
51 | }; | |
52 | ||
53 | static struct clk pll1_clk = { | |
54 | .name = "pll1", | |
55 | .parent = &ref_clk, | |
56 | .pll_data = &pll1_data, | |
57 | .flags = CLK_PLL, | |
58 | }; | |
59 | ||
60 | static struct clk pll1_sysclk1 = { | |
61 | .name = "pll1_sysclk1", | |
62 | .parent = &pll1_clk, | |
63 | .flags = CLK_PLL, | |
64 | .div_reg = PLLDIV1, | |
65 | }; | |
66 | ||
67 | static struct clk pll1_sysclk2 = { | |
68 | .name = "pll1_sysclk2", | |
69 | .parent = &pll1_clk, | |
70 | .flags = CLK_PLL, | |
71 | .div_reg = PLLDIV2, | |
72 | }; | |
73 | ||
74 | static struct clk pll1_sysclk3 = { | |
75 | .name = "pll1_sysclk3", | |
76 | .parent = &pll1_clk, | |
77 | .flags = CLK_PLL, | |
78 | .div_reg = PLLDIV3, | |
79 | }; | |
80 | ||
81 | static struct clk pll1_sysclk5 = { | |
82 | .name = "pll1_sysclk5", | |
83 | .parent = &pll1_clk, | |
84 | .flags = CLK_PLL, | |
85 | .div_reg = PLLDIV5, | |
86 | }; | |
87 | ||
88 | static struct clk pll1_aux_clk = { | |
89 | .name = "pll1_aux_clk", | |
90 | .parent = &pll1_clk, | |
91 | .flags = CLK_PLL | PRE_PLL, | |
92 | }; | |
93 | ||
94 | static struct clk pll1_sysclkbp = { | |
95 | .name = "pll1_sysclkbp", | |
96 | .parent = &pll1_clk, | |
97 | .flags = CLK_PLL | PRE_PLL, | |
98 | .div_reg = BPDIV | |
99 | }; | |
100 | ||
101 | static struct clk pll2_clk = { | |
102 | .name = "pll2", | |
103 | .parent = &ref_clk, | |
104 | .pll_data = &pll2_data, | |
105 | .flags = CLK_PLL, | |
106 | }; | |
107 | ||
108 | static struct clk pll2_sysclk1 = { | |
109 | .name = "pll2_sysclk1", | |
110 | .parent = &pll2_clk, | |
111 | .flags = CLK_PLL, | |
112 | .div_reg = PLLDIV1, | |
113 | }; | |
114 | ||
115 | static struct clk pll2_sysclk2 = { | |
116 | .name = "pll2_sysclk2", | |
117 | .parent = &pll2_clk, | |
118 | .flags = CLK_PLL, | |
119 | .div_reg = PLLDIV2, | |
120 | }; | |
121 | ||
122 | static struct clk pll2_sysclkbp = { | |
123 | .name = "pll2_sysclkbp", | |
124 | .parent = &pll2_clk, | |
125 | .flags = CLK_PLL | PRE_PLL, | |
126 | .div_reg = BPDIV | |
127 | }; | |
128 | ||
129 | static struct clk dsp_clk = { | |
130 | .name = "dsp", | |
131 | .parent = &pll1_sysclk1, | |
132 | .lpsc = DAVINCI_LPSC_GEM, | |
133 | .flags = PSC_DSP, | |
134 | .usecount = 1, /* REVISIT how to disable? */ | |
135 | }; | |
136 | ||
137 | static struct clk arm_clk = { | |
138 | .name = "arm", | |
139 | .parent = &pll1_sysclk2, | |
140 | .lpsc = DAVINCI_LPSC_ARM, | |
141 | .flags = ALWAYS_ENABLED, | |
142 | }; | |
143 | ||
144 | static struct clk vicp_clk = { | |
145 | .name = "vicp", | |
146 | .parent = &pll1_sysclk2, | |
147 | .lpsc = DAVINCI_LPSC_IMCOP, | |
148 | .flags = PSC_DSP, | |
149 | .usecount = 1, /* REVISIT how to disable? */ | |
150 | }; | |
151 | ||
152 | static struct clk vpss_master_clk = { | |
153 | .name = "vpss_master", | |
154 | .parent = &pll1_sysclk3, | |
155 | .lpsc = DAVINCI_LPSC_VPSSMSTR, | |
156 | .flags = CLK_PSC, | |
157 | }; | |
158 | ||
159 | static struct clk vpss_slave_clk = { | |
160 | .name = "vpss_slave", | |
161 | .parent = &pll1_sysclk3, | |
162 | .lpsc = DAVINCI_LPSC_VPSSSLV, | |
163 | }; | |
164 | ||
165 | static struct clk uart0_clk = { | |
166 | .name = "uart0", | |
167 | .parent = &pll1_aux_clk, | |
168 | .lpsc = DAVINCI_LPSC_UART0, | |
169 | }; | |
170 | ||
171 | static struct clk uart1_clk = { | |
172 | .name = "uart1", | |
173 | .parent = &pll1_aux_clk, | |
174 | .lpsc = DAVINCI_LPSC_UART1, | |
175 | }; | |
176 | ||
177 | static struct clk uart2_clk = { | |
178 | .name = "uart2", | |
179 | .parent = &pll1_aux_clk, | |
180 | .lpsc = DAVINCI_LPSC_UART2, | |
181 | }; | |
182 | ||
183 | static struct clk emac_clk = { | |
184 | .name = "emac", | |
185 | .parent = &pll1_sysclk5, | |
186 | .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, | |
187 | }; | |
188 | ||
189 | static struct clk i2c_clk = { | |
190 | .name = "i2c", | |
191 | .parent = &pll1_aux_clk, | |
192 | .lpsc = DAVINCI_LPSC_I2C, | |
193 | }; | |
194 | ||
195 | static struct clk ide_clk = { | |
196 | .name = "ide", | |
197 | .parent = &pll1_sysclk5, | |
198 | .lpsc = DAVINCI_LPSC_ATA, | |
199 | }; | |
200 | ||
201 | static struct clk asp_clk = { | |
202 | .name = "asp0", | |
203 | .parent = &pll1_sysclk5, | |
204 | .lpsc = DAVINCI_LPSC_McBSP, | |
205 | }; | |
206 | ||
207 | static struct clk mmcsd_clk = { | |
208 | .name = "mmcsd", | |
209 | .parent = &pll1_sysclk5, | |
210 | .lpsc = DAVINCI_LPSC_MMC_SD, | |
211 | }; | |
212 | ||
213 | static struct clk spi_clk = { | |
214 | .name = "spi", | |
215 | .parent = &pll1_sysclk5, | |
216 | .lpsc = DAVINCI_LPSC_SPI, | |
217 | }; | |
218 | ||
219 | static struct clk gpio_clk = { | |
220 | .name = "gpio", | |
221 | .parent = &pll1_sysclk5, | |
222 | .lpsc = DAVINCI_LPSC_GPIO, | |
223 | }; | |
224 | ||
225 | static struct clk usb_clk = { | |
226 | .name = "usb", | |
227 | .parent = &pll1_sysclk5, | |
228 | .lpsc = DAVINCI_LPSC_USB, | |
229 | }; | |
230 | ||
231 | static struct clk vlynq_clk = { | |
232 | .name = "vlynq", | |
233 | .parent = &pll1_sysclk5, | |
234 | .lpsc = DAVINCI_LPSC_VLYNQ, | |
235 | }; | |
236 | ||
237 | static struct clk aemif_clk = { | |
238 | .name = "aemif", | |
239 | .parent = &pll1_sysclk5, | |
240 | .lpsc = DAVINCI_LPSC_AEMIF, | |
241 | }; | |
242 | ||
243 | static struct clk pwm0_clk = { | |
244 | .name = "pwm0", | |
245 | .parent = &pll1_aux_clk, | |
246 | .lpsc = DAVINCI_LPSC_PWM0, | |
247 | }; | |
248 | ||
249 | static struct clk pwm1_clk = { | |
250 | .name = "pwm1", | |
251 | .parent = &pll1_aux_clk, | |
252 | .lpsc = DAVINCI_LPSC_PWM1, | |
253 | }; | |
254 | ||
255 | static struct clk pwm2_clk = { | |
256 | .name = "pwm2", | |
257 | .parent = &pll1_aux_clk, | |
258 | .lpsc = DAVINCI_LPSC_PWM2, | |
259 | }; | |
260 | ||
261 | static struct clk timer0_clk = { | |
262 | .name = "timer0", | |
263 | .parent = &pll1_aux_clk, | |
264 | .lpsc = DAVINCI_LPSC_TIMER0, | |
265 | }; | |
266 | ||
267 | static struct clk timer1_clk = { | |
268 | .name = "timer1", | |
269 | .parent = &pll1_aux_clk, | |
270 | .lpsc = DAVINCI_LPSC_TIMER1, | |
271 | }; | |
272 | ||
273 | static struct clk timer2_clk = { | |
274 | .name = "timer2", | |
275 | .parent = &pll1_aux_clk, | |
276 | .lpsc = DAVINCI_LPSC_TIMER2, | |
277 | .usecount = 1, /* REVISIT: why cant' this be disabled? */ | |
278 | }; | |
279 | ||
28552c2e | 280 | static struct clk_lookup dm644x_clks[] = { |
d0e47fba KH |
281 | CLK(NULL, "ref", &ref_clk), |
282 | CLK(NULL, "pll1", &pll1_clk), | |
283 | CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), | |
284 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | |
285 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | |
286 | CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | |
287 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
288 | CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), | |
289 | CLK(NULL, "pll2", &pll2_clk), | |
290 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | |
291 | CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), | |
292 | CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), | |
293 | CLK(NULL, "dsp", &dsp_clk), | |
294 | CLK(NULL, "arm", &arm_clk), | |
295 | CLK(NULL, "vicp", &vicp_clk), | |
296 | CLK(NULL, "vpss_master", &vpss_master_clk), | |
297 | CLK(NULL, "vpss_slave", &vpss_slave_clk), | |
298 | CLK(NULL, "arm", &arm_clk), | |
299 | CLK(NULL, "uart0", &uart0_clk), | |
300 | CLK(NULL, "uart1", &uart1_clk), | |
301 | CLK(NULL, "uart2", &uart2_clk), | |
302 | CLK("davinci_emac.1", NULL, &emac_clk), | |
303 | CLK("i2c_davinci.1", NULL, &i2c_clk), | |
304 | CLK("palm_bk3710", NULL, &ide_clk), | |
61aa0732 | 305 | CLK("davinci-asp", NULL, &asp_clk), |
d0e47fba KH |
306 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), |
307 | CLK(NULL, "spi", &spi_clk), | |
308 | CLK(NULL, "gpio", &gpio_clk), | |
309 | CLK(NULL, "usb", &usb_clk), | |
310 | CLK(NULL, "vlynq", &vlynq_clk), | |
311 | CLK(NULL, "aemif", &aemif_clk), | |
312 | CLK(NULL, "pwm0", &pwm0_clk), | |
313 | CLK(NULL, "pwm1", &pwm1_clk), | |
314 | CLK(NULL, "pwm2", &pwm2_clk), | |
315 | CLK(NULL, "timer0", &timer0_clk), | |
316 | CLK(NULL, "timer1", &timer1_clk), | |
317 | CLK("watchdog", NULL, &timer2_clk), | |
318 | CLK(NULL, NULL, NULL), | |
319 | }; | |
320 | ||
972412b6 MG |
321 | static struct emac_platform_data dm644x_emac_pdata = { |
322 | .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, | |
323 | .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, | |
324 | .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, | |
325 | .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET, | |
326 | .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, | |
327 | .version = EMAC_VERSION_1, | |
328 | }; | |
d0e47fba KH |
329 | |
330 | static struct resource dm644x_emac_resources[] = { | |
331 | { | |
332 | .start = DM644X_EMAC_BASE, | |
333 | .end = DM644X_EMAC_BASE + 0x47ff, | |
334 | .flags = IORESOURCE_MEM, | |
335 | }, | |
336 | { | |
337 | .start = IRQ_EMACINT, | |
338 | .end = IRQ_EMACINT, | |
339 | .flags = IORESOURCE_IRQ, | |
340 | }, | |
341 | }; | |
342 | ||
343 | static struct platform_device dm644x_emac_device = { | |
344 | .name = "davinci_emac", | |
345 | .id = 1, | |
972412b6 MG |
346 | .dev = { |
347 | .platform_data = &dm644x_emac_pdata, | |
348 | }, | |
d0e47fba KH |
349 | .num_resources = ARRAY_SIZE(dm644x_emac_resources), |
350 | .resource = dm644x_emac_resources, | |
351 | }; | |
352 | ||
d0e47fba KH |
353 | /* |
354 | * Device specific mux setup | |
355 | * | |
356 | * soc description mux mode mode mux dbg | |
357 | * reg offset mask mode | |
358 | */ | |
359 | static const struct mux_config dm644x_pins[] = { | |
0e585952 | 360 | #ifdef CONFIG_DAVINCI_MUX |
d0e47fba KH |
361 | MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) |
362 | MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) | |
363 | MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) | |
364 | ||
365 | MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) | |
366 | ||
367 | MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) | |
c16fe267 AP |
368 | MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true) |
369 | MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true) | |
370 | MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true) | |
371 | MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true) | |
372 | MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true) | |
d0e47fba KH |
373 | |
374 | MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) | |
375 | ||
376 | MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) | |
377 | ||
378 | MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) | |
379 | ||
380 | MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true) | |
381 | MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true) | |
382 | ||
383 | MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) | |
384 | ||
385 | MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) | |
386 | ||
387 | MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) | |
388 | ||
389 | MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) | |
390 | MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) | |
391 | MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) | |
392 | ||
393 | MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) | |
394 | ||
395 | MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) | |
396 | ||
397 | MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) | |
398 | MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) | |
399 | MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) | |
400 | MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) | |
401 | ||
402 | MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) | |
403 | ||
404 | MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) | |
405 | MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) | |
0e585952 | 406 | #endif |
d0e47fba KH |
407 | }; |
408 | ||
673dd36f MG |
409 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ |
410 | static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { | |
411 | [IRQ_VDINT0] = 2, | |
412 | [IRQ_VDINT1] = 6, | |
413 | [IRQ_VDINT2] = 6, | |
414 | [IRQ_HISTINT] = 6, | |
415 | [IRQ_H3AINT] = 6, | |
416 | [IRQ_PRVUINT] = 6, | |
417 | [IRQ_RSZINT] = 6, | |
418 | [7] = 7, | |
419 | [IRQ_VENCINT] = 6, | |
420 | [IRQ_ASQINT] = 6, | |
421 | [IRQ_IMXINT] = 6, | |
422 | [IRQ_VLCDINT] = 6, | |
423 | [IRQ_USBINT] = 4, | |
424 | [IRQ_EMACINT] = 4, | |
425 | [14] = 7, | |
426 | [15] = 7, | |
427 | [IRQ_CCINT0] = 5, /* dma */ | |
428 | [IRQ_CCERRINT] = 5, /* dma */ | |
429 | [IRQ_TCERRINT0] = 5, /* dma */ | |
430 | [IRQ_TCERRINT] = 5, /* dma */ | |
431 | [IRQ_PSCIN] = 7, | |
432 | [21] = 7, | |
433 | [IRQ_IDE] = 4, | |
434 | [23] = 7, | |
435 | [IRQ_MBXINT] = 7, | |
436 | [IRQ_MBRINT] = 7, | |
437 | [IRQ_MMCINT] = 7, | |
438 | [IRQ_SDIOINT] = 7, | |
439 | [28] = 7, | |
440 | [IRQ_DDRINT] = 7, | |
441 | [IRQ_AEMIFINT] = 7, | |
442 | [IRQ_VLQINT] = 4, | |
443 | [IRQ_TINT0_TINT12] = 2, /* clockevent */ | |
444 | [IRQ_TINT0_TINT34] = 2, /* clocksource */ | |
445 | [IRQ_TINT1_TINT12] = 7, /* DSP timer */ | |
446 | [IRQ_TINT1_TINT34] = 7, /* system tick */ | |
447 | [IRQ_PWMINT0] = 7, | |
448 | [IRQ_PWMINT1] = 7, | |
449 | [IRQ_PWMINT2] = 7, | |
450 | [IRQ_I2C] = 3, | |
451 | [IRQ_UARTINT0] = 3, | |
452 | [IRQ_UARTINT1] = 3, | |
453 | [IRQ_UARTINT2] = 3, | |
454 | [IRQ_SPINT0] = 3, | |
455 | [IRQ_SPINT1] = 3, | |
456 | [45] = 7, | |
457 | [IRQ_DSP2ARM0] = 4, | |
458 | [IRQ_DSP2ARM1] = 4, | |
459 | [IRQ_GPIO0] = 7, | |
460 | [IRQ_GPIO1] = 7, | |
461 | [IRQ_GPIO2] = 7, | |
462 | [IRQ_GPIO3] = 7, | |
463 | [IRQ_GPIO4] = 7, | |
464 | [IRQ_GPIO5] = 7, | |
465 | [IRQ_GPIO6] = 7, | |
466 | [IRQ_GPIO7] = 7, | |
467 | [IRQ_GPIOBNK0] = 7, | |
468 | [IRQ_GPIOBNK1] = 7, | |
469 | [IRQ_GPIOBNK2] = 7, | |
470 | [IRQ_GPIOBNK3] = 7, | |
471 | [IRQ_GPIOBNK4] = 7, | |
472 | [IRQ_COMMTX] = 7, | |
473 | [IRQ_COMMRX] = 7, | |
474 | [IRQ_EMUINT] = 7, | |
475 | }; | |
476 | ||
d0e47fba KH |
477 | /*----------------------------------------------------------------------*/ |
478 | ||
60902a2c SR |
479 | static const s8 |
480 | queue_tc_mapping[][2] = { | |
481 | /* {event queue no, TC no} */ | |
482 | {0, 0}, | |
483 | {1, 1}, | |
484 | {-1, -1}, | |
485 | }; | |
486 | ||
487 | static const s8 | |
488 | queue_priority_mapping[][2] = { | |
489 | /* {event queue no, Priority} */ | |
490 | {0, 3}, | |
491 | {1, 7}, | |
492 | {-1, -1}, | |
493 | }; | |
494 | ||
495 | static struct edma_soc_info dm644x_edma_info[] = { | |
496 | { | |
497 | .n_channel = 64, | |
498 | .n_region = 4, | |
499 | .n_slot = 128, | |
500 | .n_tc = 2, | |
501 | .n_cc = 1, | |
60902a2c SR |
502 | .queue_tc_mapping = queue_tc_mapping, |
503 | .queue_priority_mapping = queue_priority_mapping, | |
504 | }, | |
d0e47fba KH |
505 | }; |
506 | ||
507 | static struct resource edma_resources[] = { | |
508 | { | |
60902a2c | 509 | .name = "edma_cc0", |
d0e47fba KH |
510 | .start = 0x01c00000, |
511 | .end = 0x01c00000 + SZ_64K - 1, | |
512 | .flags = IORESOURCE_MEM, | |
513 | }, | |
514 | { | |
515 | .name = "edma_tc0", | |
516 | .start = 0x01c10000, | |
517 | .end = 0x01c10000 + SZ_1K - 1, | |
518 | .flags = IORESOURCE_MEM, | |
519 | }, | |
520 | { | |
521 | .name = "edma_tc1", | |
522 | .start = 0x01c10400, | |
523 | .end = 0x01c10400 + SZ_1K - 1, | |
524 | .flags = IORESOURCE_MEM, | |
525 | }, | |
526 | { | |
60902a2c | 527 | .name = "edma0", |
d0e47fba KH |
528 | .start = IRQ_CCINT0, |
529 | .flags = IORESOURCE_IRQ, | |
530 | }, | |
531 | { | |
60902a2c | 532 | .name = "edma0_err", |
d0e47fba KH |
533 | .start = IRQ_CCERRINT, |
534 | .flags = IORESOURCE_IRQ, | |
535 | }, | |
536 | /* not using TC*_ERR */ | |
537 | }; | |
538 | ||
539 | static struct platform_device dm644x_edma_device = { | |
540 | .name = "edma", | |
60902a2c SR |
541 | .id = 0, |
542 | .dev.platform_data = dm644x_edma_info, | |
d0e47fba KH |
543 | .num_resources = ARRAY_SIZE(edma_resources), |
544 | .resource = edma_resources, | |
545 | }; | |
546 | ||
25acf553 C |
547 | /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ |
548 | static struct resource dm644x_asp_resources[] = { | |
549 | { | |
550 | .start = DAVINCI_ASP0_BASE, | |
551 | .end = DAVINCI_ASP0_BASE + SZ_8K - 1, | |
552 | .flags = IORESOURCE_MEM, | |
553 | }, | |
554 | { | |
555 | .start = DAVINCI_DMA_ASP0_TX, | |
556 | .end = DAVINCI_DMA_ASP0_TX, | |
557 | .flags = IORESOURCE_DMA, | |
558 | }, | |
559 | { | |
560 | .start = DAVINCI_DMA_ASP0_RX, | |
561 | .end = DAVINCI_DMA_ASP0_RX, | |
562 | .flags = IORESOURCE_DMA, | |
563 | }, | |
564 | }; | |
565 | ||
566 | static struct platform_device dm644x_asp_device = { | |
567 | .name = "davinci-asp", | |
568 | .id = -1, | |
569 | .num_resources = ARRAY_SIZE(dm644x_asp_resources), | |
570 | .resource = dm644x_asp_resources, | |
571 | }; | |
572 | ||
ab8e8df8 MK |
573 | static struct resource dm644x_vpss_resources[] = { |
574 | { | |
575 | /* VPSS Base address */ | |
576 | .name = "vpss", | |
577 | .start = 0x01c73400, | |
578 | .end = 0x01c73400 + 0xff, | |
579 | .flags = IORESOURCE_MEM, | |
580 | }, | |
581 | }; | |
582 | ||
583 | static struct platform_device dm644x_vpss_device = { | |
584 | .name = "vpss", | |
585 | .id = -1, | |
586 | .dev.platform_data = "dm644x_vpss", | |
587 | .num_resources = ARRAY_SIZE(dm644x_vpss_resources), | |
588 | .resource = dm644x_vpss_resources, | |
589 | }; | |
590 | ||
591 | static struct resource vpfe_resources[] = { | |
592 | { | |
593 | .start = IRQ_VDINT0, | |
594 | .end = IRQ_VDINT0, | |
595 | .flags = IORESOURCE_IRQ, | |
596 | }, | |
597 | { | |
598 | .start = IRQ_VDINT1, | |
599 | .end = IRQ_VDINT1, | |
600 | .flags = IORESOURCE_IRQ, | |
601 | }, | |
77c8b5fb MK |
602 | }; |
603 | ||
604 | static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); | |
605 | static struct resource dm644x_ccdc_resource[] = { | |
606 | /* CCDC Base address */ | |
ab8e8df8 MK |
607 | { |
608 | .start = 0x01c70400, | |
609 | .end = 0x01c70400 + 0xff, | |
610 | .flags = IORESOURCE_MEM, | |
611 | }, | |
612 | }; | |
613 | ||
77c8b5fb MK |
614 | static struct platform_device dm644x_ccdc_dev = { |
615 | .name = "dm644x_ccdc", | |
616 | .id = -1, | |
617 | .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), | |
618 | .resource = dm644x_ccdc_resource, | |
619 | .dev = { | |
620 | .dma_mask = &vpfe_capture_dma_mask, | |
621 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
622 | }, | |
623 | }; | |
624 | ||
ab8e8df8 MK |
625 | static struct platform_device vpfe_capture_dev = { |
626 | .name = CAPTURE_DRV_NAME, | |
627 | .id = -1, | |
628 | .num_resources = ARRAY_SIZE(vpfe_resources), | |
629 | .resource = vpfe_resources, | |
630 | .dev = { | |
631 | .dma_mask = &vpfe_capture_dma_mask, | |
632 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
633 | }, | |
634 | }; | |
635 | ||
636 | void dm644x_set_vpfe_config(struct vpfe_config *cfg) | |
637 | { | |
638 | vpfe_capture_dev.dev.platform_data = cfg; | |
639 | } | |
640 | ||
d0e47fba | 641 | /*----------------------------------------------------------------------*/ |
ac7b75b5 | 642 | |
79c3c0b7 MG |
643 | static struct map_desc dm644x_io_desc[] = { |
644 | { | |
645 | .virtual = IO_VIRT, | |
646 | .pfn = __phys_to_pfn(IO_PHYS), | |
647 | .length = IO_SIZE, | |
648 | .type = MT_DEVICE | |
649 | }, | |
0d04eb47 DB |
650 | { |
651 | .virtual = SRAM_VIRT, | |
652 | .pfn = __phys_to_pfn(0x00008000), | |
653 | .length = SZ_16K, | |
654 | /* MT_MEMORY_NONCACHED requires supersection alignment */ | |
655 | .type = MT_DEVICE, | |
656 | }, | |
79c3c0b7 MG |
657 | }; |
658 | ||
b9ab1279 MG |
659 | /* Contents of JTAG ID register used to identify exact cpu type */ |
660 | static struct davinci_id dm644x_ids[] = { | |
661 | { | |
662 | .variant = 0x0, | |
663 | .part_no = 0xb700, | |
664 | .manufacturer = 0x017, | |
665 | .cpu_id = DAVINCI_CPU_ID_DM6446, | |
666 | .name = "dm6446", | |
667 | }, | |
98d0e9fc RS |
668 | { |
669 | .variant = 0x1, | |
670 | .part_no = 0xb700, | |
671 | .manufacturer = 0x017, | |
672 | .cpu_id = DAVINCI_CPU_ID_DM6446, | |
673 | .name = "dm6446a", | |
674 | }, | |
b9ab1279 MG |
675 | }; |
676 | ||
d81d188c MG |
677 | static void __iomem *dm644x_psc_bases[] = { |
678 | IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), | |
679 | }; | |
680 | ||
f64691b3 MG |
681 | /* |
682 | * T0_BOT: Timer 0, bottom: clockevent source for hrtimers | |
683 | * T0_TOP: Timer 0, top : clocksource for generic timekeeping | |
684 | * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) | |
685 | * T1_TOP: Timer 1, top : <unused> | |
686 | */ | |
28552c2e | 687 | static struct davinci_timer_info dm644x_timer_info = { |
f64691b3 MG |
688 | .timers = davinci_timer_instance, |
689 | .clockevent_id = T0_BOT, | |
690 | .clocksource_id = T0_TOP, | |
691 | }; | |
692 | ||
65e866a9 MG |
693 | static struct plat_serial8250_port dm644x_serial_platform_data[] = { |
694 | { | |
695 | .mapbase = DAVINCI_UART0_BASE, | |
696 | .irq = IRQ_UARTINT0, | |
697 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
698 | UPF_IOREMAP, | |
699 | .iotype = UPIO_MEM, | |
700 | .regshift = 2, | |
701 | }, | |
702 | { | |
703 | .mapbase = DAVINCI_UART1_BASE, | |
704 | .irq = IRQ_UARTINT1, | |
705 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
706 | UPF_IOREMAP, | |
707 | .iotype = UPIO_MEM, | |
708 | .regshift = 2, | |
709 | }, | |
710 | { | |
711 | .mapbase = DAVINCI_UART2_BASE, | |
712 | .irq = IRQ_UARTINT2, | |
713 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
714 | UPF_IOREMAP, | |
715 | .iotype = UPIO_MEM, | |
716 | .regshift = 2, | |
717 | }, | |
718 | { | |
719 | .flags = 0 | |
720 | }, | |
721 | }; | |
722 | ||
723 | static struct platform_device dm644x_serial_device = { | |
724 | .name = "serial8250", | |
725 | .id = PLAT8250_DEV_PLATFORM, | |
726 | .dev = { | |
727 | .platform_data = dm644x_serial_platform_data, | |
728 | }, | |
729 | }; | |
730 | ||
79c3c0b7 MG |
731 | static struct davinci_soc_info davinci_soc_info_dm644x = { |
732 | .io_desc = dm644x_io_desc, | |
733 | .io_desc_num = ARRAY_SIZE(dm644x_io_desc), | |
b9ab1279 MG |
734 | .jtag_id_base = IO_ADDRESS(0x01c40028), |
735 | .ids = dm644x_ids, | |
736 | .ids_num = ARRAY_SIZE(dm644x_ids), | |
66e0c399 | 737 | .cpu_clks = dm644x_clks, |
d81d188c MG |
738 | .psc_bases = dm644x_psc_bases, |
739 | .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), | |
0e585952 MG |
740 | .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), |
741 | .pinmux_pins = dm644x_pins, | |
742 | .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), | |
673dd36f MG |
743 | .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), |
744 | .intc_type = DAVINCI_INTC_TYPE_AINTC, | |
745 | .intc_irq_prios = dm644x_default_priorities, | |
746 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | |
f64691b3 | 747 | .timer_info = &dm644x_timer_info, |
686b634a | 748 | .gpio_type = GPIO_TYPE_DAVINCI, |
a994955c MG |
749 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), |
750 | .gpio_num = 71, | |
751 | .gpio_irq = IRQ_GPIOBNK0, | |
65e866a9 | 752 | .serial_dev = &dm644x_serial_device, |
972412b6 | 753 | .emac_pdata = &dm644x_emac_pdata, |
0d04eb47 DB |
754 | .sram_dma = 0x00008000, |
755 | .sram_len = SZ_16K, | |
79c3c0b7 MG |
756 | }; |
757 | ||
25acf553 C |
758 | void __init dm644x_init_asp(struct snd_platform_data *pdata) |
759 | { | |
760 | davinci_cfg_reg(DM644X_MCBSP); | |
761 | dm644x_asp_device.dev.platform_data = pdata; | |
762 | platform_device_register(&dm644x_asp_device); | |
763 | } | |
764 | ||
d0e47fba KH |
765 | void __init dm644x_init(void) |
766 | { | |
79c3c0b7 | 767 | davinci_common_init(&davinci_soc_info_dm644x); |
d0e47fba KH |
768 | } |
769 | ||
770 | static int __init dm644x_init_devices(void) | |
771 | { | |
772 | if (!cpu_is_davinci_dm644x()) | |
773 | return 0; | |
774 | ||
77c8b5fb MK |
775 | /* Add ccdc clock aliases */ |
776 | clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); | |
777 | clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); | |
d0e47fba | 778 | platform_device_register(&dm644x_edma_device); |
972412b6 | 779 | platform_device_register(&dm644x_emac_device); |
ab8e8df8 | 780 | platform_device_register(&dm644x_vpss_device); |
77c8b5fb | 781 | platform_device_register(&dm644x_ccdc_dev); |
ab8e8df8 MK |
782 | platform_device_register(&vpfe_capture_dev); |
783 | ||
d0e47fba KH |
784 | return 0; |
785 | } | |
786 | postcore_initcall(dm644x_init_devices); |