Commit | Line | Data |
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95a3477f KH |
1 | /* |
2 | * TI DaVinci DM355 chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
5b19f66d DL |
11 | |
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/clk/davinci.h> | |
14 | #include <linux/clkdev.h> | |
95a3477f | 15 | #include <linux/dma-mapping.h> |
f7a3be50 | 16 | #include <linux/dmaengine.h> |
5b19f66d | 17 | #include <linux/init.h> |
fd0f4275 | 18 | #include <linux/irqchip/irq-davinci-aintc.h> |
9cc1515c PA |
19 | #include <linux/platform_data/edma.h> |
20 | #include <linux/platform_data/gpio-davinci.h> | |
21 | #include <linux/platform_data/spi-davinci.h> | |
5b19f66d DL |
22 | #include <linux/platform_device.h> |
23 | #include <linux/serial_8250.h> | |
24 | #include <linux/spi/spi.h> | |
95a3477f | 25 | |
79c3c0b7 MG |
26 | #include <asm/mach/map.h> |
27 | ||
5b19f66d | 28 | #include <mach/common.h> |
95a3477f | 29 | #include <mach/cputype.h> |
5b19f66d | 30 | #include <mach/mux.h> |
65e866a9 | 31 | #include <mach/serial.h> |
5b19f66d | 32 | #include <mach/time.h> |
95a3477f | 33 | |
5b19f66d | 34 | #include "asp.h" |
39c6d2d1 | 35 | #include "davinci.h" |
544ca0b0 | 36 | #include "irqs.h" |
95a3477f | 37 | #include "mux.h" |
5b19f66d | 38 | |
96ed299f | 39 | #define DM355_UART2_BASE (IO_PHYS + 0x206000) |
62a2d6cd LP |
40 | #define DM355_OSD_BASE (IO_PHYS + 0x70200) |
41 | #define DM355_VENC_BASE (IO_PHYS + 0x70400) | |
96ed299f | 42 | |
95a3477f KH |
43 | /* |
44 | * Device specific clocks | |
45 | */ | |
46 | #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ | |
47 | ||
95a3477f KH |
48 | static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32); |
49 | ||
50 | static struct resource dm355_spi0_resources[] = { | |
51 | { | |
52 | .start = 0x01c66000, | |
53 | .end = 0x01c667ff, | |
54 | .flags = IORESOURCE_MEM, | |
55 | }, | |
56 | { | |
a98ca73e | 57 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0), |
95a3477f KH |
58 | .flags = IORESOURCE_IRQ, |
59 | }, | |
95a3477f KH |
60 | }; |
61 | ||
15e86585 SP |
62 | static struct davinci_spi_platform_data dm355_spi0_pdata = { |
63 | .version = SPI_VERSION_1, | |
64 | .num_chipselect = 2, | |
c29e3c60 | 65 | .cshold_bug = true, |
2e3e2a5e | 66 | .dma_event_q = EVENTQ_1, |
1b0838b5 | 67 | .prescaler_limit = 1, |
15e86585 | 68 | }; |
95a3477f KH |
69 | static struct platform_device dm355_spi0_device = { |
70 | .name = "spi_davinci", | |
71 | .id = 0, | |
72 | .dev = { | |
73 | .dma_mask = &dm355_spi0_dma_mask, | |
74 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
15e86585 | 75 | .platform_data = &dm355_spi0_pdata, |
95a3477f KH |
76 | }, |
77 | .num_resources = ARRAY_SIZE(dm355_spi0_resources), | |
78 | .resource = dm355_spi0_resources, | |
79 | }; | |
80 | ||
81 | void __init dm355_init_spi0(unsigned chipselect_mask, | |
d65566e5 | 82 | const struct spi_board_info *info, unsigned len) |
95a3477f KH |
83 | { |
84 | /* for now, assume we need MISO */ | |
85 | davinci_cfg_reg(DM355_SPI0_SDI); | |
86 | ||
87 | /* not all slaves will be wired up */ | |
88 | if (chipselect_mask & BIT(0)) | |
89 | davinci_cfg_reg(DM355_SPI0_SDENA0); | |
90 | if (chipselect_mask & BIT(1)) | |
91 | davinci_cfg_reg(DM355_SPI0_SDENA1); | |
92 | ||
93 | spi_register_board_info(info, len); | |
94 | ||
95 | platform_device_register(&dm355_spi0_device); | |
96 | } | |
97 | ||
98 | /*----------------------------------------------------------------------*/ | |
99 | ||
5570078c MG |
100 | #define INTMUX 0x18 |
101 | #define EVTMUX 0x1c | |
102 | ||
95a3477f KH |
103 | /* |
104 | * Device specific mux setup | |
105 | * | |
106 | * soc description mux mode mode mux dbg | |
107 | * reg offset mask mode | |
108 | */ | |
109 | static const struct mux_config dm355_pins[] = { | |
0e585952 | 110 | #ifdef CONFIG_DAVINCI_MUX |
95a3477f KH |
111 | MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false) |
112 | ||
113 | MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false) | |
114 | MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false) | |
115 | MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false) | |
116 | MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false) | |
117 | MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false) | |
118 | MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false) | |
119 | ||
120 | MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false) | |
121 | MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false) | |
122 | ||
123 | MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false) | |
124 | MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false) | |
125 | MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false) | |
126 | MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false) | |
127 | MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false) | |
128 | MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false) | |
129 | ||
130 | MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false) | |
131 | MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false) | |
132 | MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false) | |
133 | ||
134 | INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false) | |
135 | INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false) | |
136 | INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) | |
137 | ||
138 | EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) | |
139 | EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) | |
140 | EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) | |
1aebb50e SP |
141 | |
142 | MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false) | |
143 | MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false) | |
144 | MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false) | |
145 | MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) | |
146 | MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) | |
51e68e27 MK |
147 | |
148 | MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false) | |
149 | MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false) | |
150 | MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false) | |
151 | MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false) | |
152 | MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false) | |
153 | MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false) | |
154 | MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false) | |
0e585952 | 155 | #endif |
95a3477f KH |
156 | }; |
157 | ||
673dd36f MG |
158 | static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { |
159 | [IRQ_DM355_CCDC_VDINT0] = 2, | |
160 | [IRQ_DM355_CCDC_VDINT1] = 6, | |
161 | [IRQ_DM355_CCDC_VDINT2] = 6, | |
162 | [IRQ_DM355_IPIPE_HST] = 6, | |
163 | [IRQ_DM355_H3AINT] = 6, | |
164 | [IRQ_DM355_IPIPE_SDR] = 6, | |
165 | [IRQ_DM355_IPIPEIFINT] = 6, | |
166 | [IRQ_DM355_OSDINT] = 7, | |
167 | [IRQ_DM355_VENCINT] = 6, | |
168 | [IRQ_ASQINT] = 6, | |
169 | [IRQ_IMXINT] = 6, | |
170 | [IRQ_USBINT] = 4, | |
171 | [IRQ_DM355_RTOINT] = 4, | |
172 | [IRQ_DM355_UARTINT2] = 7, | |
173 | [IRQ_DM355_TINT6] = 7, | |
174 | [IRQ_CCINT0] = 5, /* dma */ | |
175 | [IRQ_CCERRINT] = 5, /* dma */ | |
176 | [IRQ_TCERRINT0] = 5, /* dma */ | |
177 | [IRQ_TCERRINT] = 5, /* dma */ | |
178 | [IRQ_DM355_SPINT2_1] = 7, | |
179 | [IRQ_DM355_TINT7] = 4, | |
180 | [IRQ_DM355_SDIOINT0] = 7, | |
181 | [IRQ_MBXINT] = 7, | |
182 | [IRQ_MBRINT] = 7, | |
183 | [IRQ_MMCINT] = 7, | |
184 | [IRQ_DM355_MMCINT1] = 7, | |
185 | [IRQ_DM355_PWMINT3] = 7, | |
186 | [IRQ_DDRINT] = 7, | |
187 | [IRQ_AEMIFINT] = 7, | |
188 | [IRQ_DM355_SDIOINT1] = 4, | |
189 | [IRQ_TINT0_TINT12] = 2, /* clockevent */ | |
190 | [IRQ_TINT0_TINT34] = 2, /* clocksource */ | |
191 | [IRQ_TINT1_TINT12] = 7, /* DSP timer */ | |
192 | [IRQ_TINT1_TINT34] = 7, /* system tick */ | |
193 | [IRQ_PWMINT0] = 7, | |
194 | [IRQ_PWMINT1] = 7, | |
195 | [IRQ_PWMINT2] = 7, | |
196 | [IRQ_I2C] = 3, | |
197 | [IRQ_UARTINT0] = 3, | |
198 | [IRQ_UARTINT1] = 3, | |
199 | [IRQ_DM355_SPINT0_0] = 3, | |
200 | [IRQ_DM355_SPINT0_1] = 3, | |
201 | [IRQ_DM355_GPIO0] = 3, | |
202 | [IRQ_DM355_GPIO1] = 7, | |
203 | [IRQ_DM355_GPIO2] = 4, | |
204 | [IRQ_DM355_GPIO3] = 4, | |
205 | [IRQ_DM355_GPIO4] = 7, | |
206 | [IRQ_DM355_GPIO5] = 7, | |
207 | [IRQ_DM355_GPIO6] = 7, | |
208 | [IRQ_DM355_GPIO7] = 7, | |
209 | [IRQ_DM355_GPIO8] = 7, | |
210 | [IRQ_DM355_GPIO9] = 7, | |
211 | [IRQ_DM355_GPIOBNK0] = 7, | |
212 | [IRQ_DM355_GPIOBNK1] = 7, | |
213 | [IRQ_DM355_GPIOBNK2] = 7, | |
214 | [IRQ_DM355_GPIOBNK3] = 7, | |
215 | [IRQ_DM355_GPIOBNK4] = 7, | |
216 | [IRQ_DM355_GPIOBNK5] = 7, | |
217 | [IRQ_DM355_GPIOBNK6] = 7, | |
218 | [IRQ_COMMTX] = 7, | |
219 | [IRQ_COMMRX] = 7, | |
220 | [IRQ_EMUINT] = 7, | |
221 | }; | |
222 | ||
95a3477f KH |
223 | /*----------------------------------------------------------------------*/ |
224 | ||
d4cb7f40 | 225 | static s8 queue_priority_mapping[][2] = { |
60902a2c SR |
226 | /* {event queue no, Priority} */ |
227 | {0, 3}, | |
228 | {1, 7}, | |
229 | {-1, -1}, | |
230 | }; | |
231 | ||
f7a3be50 PU |
232 | static const struct dma_slave_map dm355_edma_map[] = { |
233 | { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) }, | |
234 | { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) }, | |
235 | { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) }, | |
236 | { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) }, | |
237 | { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, | |
238 | { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, | |
239 | { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, | |
240 | { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, | |
241 | { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, | |
242 | { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, | |
243 | { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, | |
244 | { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, | |
245 | { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, | |
246 | { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, | |
247 | }; | |
248 | ||
d4cb7f40 | 249 | static struct edma_soc_info dm355_edma_pdata = { |
bc3ac9f3 | 250 | .queue_priority_mapping = queue_priority_mapping, |
f23fe857 | 251 | .default_queue = EVENTQ_1, |
f7a3be50 PU |
252 | .slave_map = dm355_edma_map, |
253 | .slavecnt = ARRAY_SIZE(dm355_edma_map), | |
bc3ac9f3 SN |
254 | }; |
255 | ||
95a3477f KH |
256 | static struct resource edma_resources[] = { |
257 | { | |
d4cb7f40 | 258 | .name = "edma3_cc", |
95a3477f KH |
259 | .start = 0x01c00000, |
260 | .end = 0x01c00000 + SZ_64K - 1, | |
261 | .flags = IORESOURCE_MEM, | |
262 | }, | |
263 | { | |
d4cb7f40 | 264 | .name = "edma3_tc0", |
95a3477f KH |
265 | .start = 0x01c10000, |
266 | .end = 0x01c10000 + SZ_1K - 1, | |
267 | .flags = IORESOURCE_MEM, | |
268 | }, | |
269 | { | |
d4cb7f40 | 270 | .name = "edma3_tc1", |
95a3477f KH |
271 | .start = 0x01c10400, |
272 | .end = 0x01c10400 + SZ_1K - 1, | |
273 | .flags = IORESOURCE_MEM, | |
274 | }, | |
275 | { | |
d4cb7f40 | 276 | .name = "edma3_ccint", |
a98ca73e | 277 | .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), |
95a3477f KH |
278 | .flags = IORESOURCE_IRQ, |
279 | }, | |
280 | { | |
d4cb7f40 | 281 | .name = "edma3_ccerrint", |
a98ca73e | 282 | .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), |
95a3477f KH |
283 | .flags = IORESOURCE_IRQ, |
284 | }, | |
285 | /* not using (or muxing) TC*_ERR */ | |
286 | }; | |
287 | ||
7ab388e8 PU |
288 | static const struct platform_device_info dm355_edma_device __initconst = { |
289 | .name = "edma", | |
290 | .id = 0, | |
cef5b0da | 291 | .dma_mask = DMA_BIT_MASK(32), |
7ab388e8 PU |
292 | .res = edma_resources, |
293 | .num_res = ARRAY_SIZE(edma_resources), | |
294 | .data = &dm355_edma_pdata, | |
295 | .size_data = sizeof(dm355_edma_pdata), | |
95a3477f KH |
296 | }; |
297 | ||
25acf553 C |
298 | static struct resource dm355_asp1_resources[] = { |
299 | { | |
ee880dbd | 300 | .name = "mpu", |
25acf553 C |
301 | .start = DAVINCI_ASP1_BASE, |
302 | .end = DAVINCI_ASP1_BASE + SZ_8K - 1, | |
303 | .flags = IORESOURCE_MEM, | |
304 | }, | |
305 | { | |
306 | .start = DAVINCI_DMA_ASP1_TX, | |
307 | .end = DAVINCI_DMA_ASP1_TX, | |
308 | .flags = IORESOURCE_DMA, | |
309 | }, | |
310 | { | |
311 | .start = DAVINCI_DMA_ASP1_RX, | |
312 | .end = DAVINCI_DMA_ASP1_RX, | |
313 | .flags = IORESOURCE_DMA, | |
314 | }, | |
315 | }; | |
316 | ||
317 | static struct platform_device dm355_asp1_device = { | |
bedad0ca | 318 | .name = "davinci-mcbsp", |
61aa0732 | 319 | .id = 1, |
25acf553 C |
320 | .num_resources = ARRAY_SIZE(dm355_asp1_resources), |
321 | .resource = dm355_asp1_resources, | |
322 | }; | |
323 | ||
77c8b5fb MK |
324 | static void dm355_ccdc_setup_pinmux(void) |
325 | { | |
326 | davinci_cfg_reg(DM355_VIN_PCLK); | |
327 | davinci_cfg_reg(DM355_VIN_CAM_WEN); | |
328 | davinci_cfg_reg(DM355_VIN_CAM_VD); | |
329 | davinci_cfg_reg(DM355_VIN_CAM_HD); | |
330 | davinci_cfg_reg(DM355_VIN_YIN_EN); | |
331 | davinci_cfg_reg(DM355_VIN_CINL_EN); | |
332 | davinci_cfg_reg(DM355_VIN_CINH_EN); | |
333 | } | |
334 | ||
51e68e27 MK |
335 | static struct resource dm355_vpss_resources[] = { |
336 | { | |
337 | /* VPSS BL Base address */ | |
338 | .name = "vpss", | |
339 | .start = 0x01c70800, | |
340 | .end = 0x01c70800 + 0xff, | |
341 | .flags = IORESOURCE_MEM, | |
342 | }, | |
343 | { | |
344 | /* VPSS CLK Base address */ | |
345 | .name = "vpss", | |
346 | .start = 0x01c70000, | |
347 | .end = 0x01c70000 + 0xf, | |
348 | .flags = IORESOURCE_MEM, | |
349 | }, | |
350 | }; | |
351 | ||
352 | static struct platform_device dm355_vpss_device = { | |
353 | .name = "vpss", | |
354 | .id = -1, | |
355 | .dev.platform_data = "dm355_vpss", | |
356 | .num_resources = ARRAY_SIZE(dm355_vpss_resources), | |
357 | .resource = dm355_vpss_resources, | |
358 | }; | |
359 | ||
360 | static struct resource vpfe_resources[] = { | |
361 | { | |
a98ca73e BG |
362 | .start = DAVINCI_INTC_IRQ(IRQ_VDINT0), |
363 | .end = DAVINCI_INTC_IRQ(IRQ_VDINT0), | |
51e68e27 MK |
364 | .flags = IORESOURCE_IRQ, |
365 | }, | |
366 | { | |
a98ca73e BG |
367 | .start = DAVINCI_INTC_IRQ(IRQ_VDINT1), |
368 | .end = DAVINCI_INTC_IRQ(IRQ_VDINT1), | |
51e68e27 MK |
369 | .flags = IORESOURCE_IRQ, |
370 | }, | |
77c8b5fb MK |
371 | }; |
372 | ||
373 | static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); | |
374 | static struct resource dm355_ccdc_resource[] = { | |
51e68e27 MK |
375 | /* CCDC Base address */ |
376 | { | |
377 | .flags = IORESOURCE_MEM, | |
378 | .start = 0x01c70600, | |
379 | .end = 0x01c70600 + 0x1ff, | |
380 | }, | |
381 | }; | |
77c8b5fb MK |
382 | static struct platform_device dm355_ccdc_dev = { |
383 | .name = "dm355_ccdc", | |
384 | .id = -1, | |
385 | .num_resources = ARRAY_SIZE(dm355_ccdc_resource), | |
386 | .resource = dm355_ccdc_resource, | |
387 | .dev = { | |
388 | .dma_mask = &vpfe_capture_dma_mask, | |
389 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
390 | .platform_data = dm355_ccdc_setup_pinmux, | |
391 | }, | |
392 | }; | |
51e68e27 | 393 | |
51e68e27 MK |
394 | static struct platform_device vpfe_capture_dev = { |
395 | .name = CAPTURE_DRV_NAME, | |
396 | .id = -1, | |
397 | .num_resources = ARRAY_SIZE(vpfe_resources), | |
398 | .resource = vpfe_resources, | |
399 | .dev = { | |
400 | .dma_mask = &vpfe_capture_dma_mask, | |
401 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
402 | }, | |
403 | }; | |
404 | ||
62a2d6cd LP |
405 | static struct resource dm355_osd_resources[] = { |
406 | { | |
407 | .start = DM355_OSD_BASE, | |
408 | .end = DM355_OSD_BASE + 0x17f, | |
409 | .flags = IORESOURCE_MEM, | |
410 | }, | |
411 | }; | |
412 | ||
413 | static struct platform_device dm355_osd_dev = { | |
414 | .name = DM355_VPBE_OSD_SUBDEV_NAME, | |
415 | .id = -1, | |
416 | .num_resources = ARRAY_SIZE(dm355_osd_resources), | |
417 | .resource = dm355_osd_resources, | |
418 | .dev = { | |
419 | .dma_mask = &vpfe_capture_dma_mask, | |
420 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
421 | }, | |
422 | }; | |
423 | ||
424 | static struct resource dm355_venc_resources[] = { | |
425 | { | |
a98ca73e BG |
426 | .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), |
427 | .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), | |
62a2d6cd LP |
428 | .flags = IORESOURCE_IRQ, |
429 | }, | |
430 | /* venc registers io space */ | |
431 | { | |
432 | .start = DM355_VENC_BASE, | |
433 | .end = DM355_VENC_BASE + 0x17f, | |
434 | .flags = IORESOURCE_MEM, | |
435 | }, | |
436 | /* VDAC config register io space */ | |
437 | { | |
438 | .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, | |
439 | .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, | |
440 | .flags = IORESOURCE_MEM, | |
441 | }, | |
442 | }; | |
443 | ||
444 | static struct resource dm355_v4l2_disp_resources[] = { | |
445 | { | |
a98ca73e BG |
446 | .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), |
447 | .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), | |
62a2d6cd LP |
448 | .flags = IORESOURCE_IRQ, |
449 | }, | |
450 | /* venc registers io space */ | |
451 | { | |
452 | .start = DM355_VENC_BASE, | |
453 | .end = DM355_VENC_BASE + 0x17f, | |
454 | .flags = IORESOURCE_MEM, | |
455 | }, | |
456 | }; | |
457 | ||
27ffaeb0 | 458 | static int dm355_vpbe_setup_pinmux(u32 if_type, int field) |
62a2d6cd LP |
459 | { |
460 | switch (if_type) { | |
27ffaeb0 | 461 | case MEDIA_BUS_FMT_SGRBG8_1X8: |
62a2d6cd LP |
462 | davinci_cfg_reg(DM355_VOUT_FIELD_G70); |
463 | break; | |
27ffaeb0 | 464 | case MEDIA_BUS_FMT_YUYV10_1X20: |
62a2d6cd LP |
465 | if (field) |
466 | davinci_cfg_reg(DM355_VOUT_FIELD); | |
467 | else | |
468 | davinci_cfg_reg(DM355_VOUT_FIELD_G70); | |
469 | break; | |
470 | default: | |
471 | return -EINVAL; | |
472 | } | |
473 | ||
474 | davinci_cfg_reg(DM355_VOUT_COUTL_EN); | |
475 | davinci_cfg_reg(DM355_VOUT_COUTH_EN); | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type, | |
481 | unsigned int pclock) | |
51e68e27 | 482 | { |
62a2d6cd LP |
483 | void __iomem *vpss_clk_ctrl_reg; |
484 | ||
485 | vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); | |
486 | ||
487 | switch (type) { | |
488 | case VPBE_ENC_STD: | |
489 | writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE, | |
490 | vpss_clk_ctrl_reg); | |
491 | break; | |
492 | case VPBE_ENC_DV_TIMINGS: | |
493 | if (pclock > 27000000) | |
494 | /* | |
495 | * For HD, use external clock source since we cannot | |
496 | * support HD mode with internal clocks. | |
497 | */ | |
498 | writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg); | |
499 | break; | |
500 | default: | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | return 0; | |
51e68e27 MK |
505 | } |
506 | ||
62a2d6cd LP |
507 | static struct platform_device dm355_vpbe_display = { |
508 | .name = "vpbe-v4l2", | |
509 | .id = -1, | |
510 | .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources), | |
511 | .resource = dm355_v4l2_disp_resources, | |
512 | .dev = { | |
513 | .dma_mask = &vpfe_capture_dma_mask, | |
514 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
515 | }, | |
516 | }; | |
517 | ||
9c559708 | 518 | static struct venc_platform_data dm355_venc_pdata = { |
62a2d6cd LP |
519 | .setup_pinmux = dm355_vpbe_setup_pinmux, |
520 | .setup_clock = dm355_venc_setup_clock, | |
521 | }; | |
522 | ||
523 | static struct platform_device dm355_venc_dev = { | |
524 | .name = DM355_VPBE_VENC_SUBDEV_NAME, | |
525 | .id = -1, | |
526 | .num_resources = ARRAY_SIZE(dm355_venc_resources), | |
527 | .resource = dm355_venc_resources, | |
528 | .dev = { | |
529 | .dma_mask = &vpfe_capture_dma_mask, | |
530 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
531 | .platform_data = (void *)&dm355_venc_pdata, | |
532 | }, | |
533 | }; | |
534 | ||
535 | static struct platform_device dm355_vpbe_dev = { | |
536 | .name = "vpbe_controller", | |
537 | .id = -1, | |
538 | .dev = { | |
539 | .dma_mask = &vpfe_capture_dma_mask, | |
540 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
541 | }, | |
542 | }; | |
543 | ||
9cc1515c PA |
544 | static struct resource dm355_gpio_resources[] = { |
545 | { /* registers */ | |
546 | .start = DAVINCI_GPIO_BASE, | |
547 | .end = DAVINCI_GPIO_BASE + SZ_4K - 1, | |
548 | .flags = IORESOURCE_MEM, | |
549 | }, | |
550 | { /* interrupt */ | |
a98ca73e BG |
551 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0), |
552 | .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0), | |
27db7baa BG |
553 | .flags = IORESOURCE_IRQ, |
554 | }, | |
555 | { | |
a98ca73e BG |
556 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1), |
557 | .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1), | |
27db7baa BG |
558 | .flags = IORESOURCE_IRQ, |
559 | }, | |
560 | { | |
a98ca73e BG |
561 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2), |
562 | .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2), | |
27db7baa BG |
563 | .flags = IORESOURCE_IRQ, |
564 | }, | |
565 | { | |
a98ca73e BG |
566 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3), |
567 | .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3), | |
27db7baa BG |
568 | .flags = IORESOURCE_IRQ, |
569 | }, | |
570 | { | |
a98ca73e BG |
571 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4), |
572 | .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4), | |
27db7baa BG |
573 | .flags = IORESOURCE_IRQ, |
574 | }, | |
575 | { | |
a98ca73e BG |
576 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5), |
577 | .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5), | |
27db7baa BG |
578 | .flags = IORESOURCE_IRQ, |
579 | }, | |
580 | { | |
a98ca73e BG |
581 | .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6), |
582 | .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6), | |
9cc1515c PA |
583 | .flags = IORESOURCE_IRQ, |
584 | }, | |
585 | }; | |
586 | ||
587 | static struct davinci_gpio_platform_data dm355_gpio_platform_data = { | |
a6ca633e BG |
588 | .no_auto_base = true, |
589 | .base = 0, | |
9cc1515c | 590 | .ngpio = 104, |
9cc1515c PA |
591 | }; |
592 | ||
593 | int __init dm355_gpio_register(void) | |
594 | { | |
595 | return davinci_gpio_register(dm355_gpio_resources, | |
e462f1f5 | 596 | ARRAY_SIZE(dm355_gpio_resources), |
9cc1515c PA |
597 | &dm355_gpio_platform_data); |
598 | } | |
95a3477f KH |
599 | /*----------------------------------------------------------------------*/ |
600 | ||
79c3c0b7 MG |
601 | static struct map_desc dm355_io_desc[] = { |
602 | { | |
603 | .virtual = IO_VIRT, | |
604 | .pfn = __phys_to_pfn(IO_PHYS), | |
605 | .length = IO_SIZE, | |
606 | .type = MT_DEVICE | |
607 | }, | |
608 | }; | |
609 | ||
b9ab1279 MG |
610 | /* Contents of JTAG ID register used to identify exact cpu type */ |
611 | static struct davinci_id dm355_ids[] = { | |
612 | { | |
613 | .variant = 0x0, | |
614 | .part_no = 0xb73b, | |
615 | .manufacturer = 0x00f, | |
616 | .cpu_id = DAVINCI_CPU_ID_DM355, | |
617 | .name = "dm355", | |
618 | }, | |
619 | }; | |
620 | ||
f64691b3 MG |
621 | /* |
622 | * T0_BOT: Timer 0, bottom: clockevent source for hrtimers | |
623 | * T0_TOP: Timer 0, top : clocksource for generic timekeeping | |
624 | * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) | |
625 | * T1_TOP: Timer 1, top : <unused> | |
626 | */ | |
28552c2e | 627 | static struct davinci_timer_info dm355_timer_info = { |
f64691b3 MG |
628 | .timers = davinci_timer_instance, |
629 | .clockevent_id = T0_BOT, | |
630 | .clocksource_id = T0_TOP, | |
631 | }; | |
632 | ||
19955c3d | 633 | static struct plat_serial8250_port dm355_serial0_platform_data[] = { |
65e866a9 MG |
634 | { |
635 | .mapbase = DAVINCI_UART0_BASE, | |
a98ca73e | 636 | .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), |
65e866a9 MG |
637 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
638 | UPF_IOREMAP, | |
639 | .iotype = UPIO_MEM, | |
640 | .regshift = 2, | |
641 | }, | |
19955c3d MP |
642 | { |
643 | .flags = 0, | |
644 | } | |
645 | }; | |
646 | static struct plat_serial8250_port dm355_serial1_platform_data[] = { | |
65e866a9 MG |
647 | { |
648 | .mapbase = DAVINCI_UART1_BASE, | |
a98ca73e | 649 | .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), |
65e866a9 MG |
650 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
651 | UPF_IOREMAP, | |
652 | .iotype = UPIO_MEM, | |
653 | .regshift = 2, | |
654 | }, | |
19955c3d MP |
655 | { |
656 | .flags = 0, | |
657 | } | |
658 | }; | |
659 | static struct plat_serial8250_port dm355_serial2_platform_data[] = { | |
65e866a9 MG |
660 | { |
661 | .mapbase = DM355_UART2_BASE, | |
a98ca73e | 662 | .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2), |
65e866a9 MG |
663 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | |
664 | UPF_IOREMAP, | |
665 | .iotype = UPIO_MEM, | |
666 | .regshift = 2, | |
667 | }, | |
668 | { | |
19955c3d MP |
669 | .flags = 0, |
670 | } | |
65e866a9 MG |
671 | }; |
672 | ||
fcf7157b | 673 | struct platform_device dm355_serial_device[] = { |
19955c3d MP |
674 | { |
675 | .name = "serial8250", | |
676 | .id = PLAT8250_DEV_PLATFORM, | |
677 | .dev = { | |
678 | .platform_data = dm355_serial0_platform_data, | |
679 | } | |
680 | }, | |
681 | { | |
682 | .name = "serial8250", | |
683 | .id = PLAT8250_DEV_PLATFORM1, | |
684 | .dev = { | |
685 | .platform_data = dm355_serial1_platform_data, | |
686 | } | |
65e866a9 | 687 | }, |
19955c3d MP |
688 | { |
689 | .name = "serial8250", | |
690 | .id = PLAT8250_DEV_PLATFORM2, | |
691 | .dev = { | |
692 | .platform_data = dm355_serial2_platform_data, | |
693 | } | |
694 | }, | |
695 | { | |
696 | } | |
65e866a9 MG |
697 | }; |
698 | ||
ab41910d | 699 | static const struct davinci_soc_info davinci_soc_info_dm355 = { |
79c3c0b7 MG |
700 | .io_desc = dm355_io_desc, |
701 | .io_desc_num = ARRAY_SIZE(dm355_io_desc), | |
3347db83 | 702 | .jtag_id_reg = 0x01c40028, |
b9ab1279 MG |
703 | .ids = dm355_ids, |
704 | .ids_num = ARRAY_SIZE(dm355_ids), | |
779b0d53 | 705 | .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, |
0e585952 MG |
706 | .pinmux_pins = dm355_pins, |
707 | .pinmux_pins_num = ARRAY_SIZE(dm355_pins), | |
f64691b3 | 708 | .timer_info = &dm355_timer_info, |
0d04eb47 DB |
709 | .sram_dma = 0x00010000, |
710 | .sram_len = SZ_32K, | |
79c3c0b7 MG |
711 | }; |
712 | ||
6bce5efd | 713 | void __init dm355_init_asp1(u32 evt_enable) |
25acf553 C |
714 | { |
715 | /* we don't use ASP1 IRQs, or we'd need to mux them ... */ | |
716 | if (evt_enable & ASP1_TX_EVT_EN) | |
717 | davinci_cfg_reg(DM355_EVT8_ASP1_TX); | |
718 | ||
719 | if (evt_enable & ASP1_RX_EVT_EN) | |
720 | davinci_cfg_reg(DM355_EVT9_ASP1_RX); | |
721 | ||
25acf553 C |
722 | platform_device_register(&dm355_asp1_device); |
723 | } | |
724 | ||
95a3477f KH |
725 | void __init dm355_init(void) |
726 | { | |
79c3c0b7 | 727 | davinci_common_init(&davinci_soc_info_dm355); |
5cfb19ac | 728 | davinci_map_sysmod(); |
96c08173 DL |
729 | } |
730 | ||
731 | void __init dm355_init_time(void) | |
732 | { | |
5b19f66d DL |
733 | void __iomem *pll1, *psc; |
734 | struct clk *clk; | |
735 | ||
736 | clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); | |
737 | ||
738 | pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); | |
739 | dm355_pll1_init(NULL, pll1, NULL); | |
740 | ||
741 | psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); | |
742 | dm355_psc_init(NULL, psc); | |
743 | ||
744 | clk = clk_get(NULL, "timer0"); | |
745 | ||
746 | davinci_timer_init(clk); | |
5b19f66d DL |
747 | } |
748 | ||
749 | static struct resource dm355_pll2_resources[] = { | |
750 | { | |
751 | .start = DAVINCI_PLL2_BASE, | |
752 | .end = DAVINCI_PLL2_BASE + SZ_1K - 1, | |
753 | .flags = IORESOURCE_MEM, | |
754 | }, | |
755 | }; | |
756 | ||
757 | static struct platform_device dm355_pll2_device = { | |
758 | .name = "dm355-pll2", | |
759 | .id = -1, | |
760 | .resource = dm355_pll2_resources, | |
761 | .num_resources = ARRAY_SIZE(dm355_pll2_resources), | |
762 | }; | |
763 | ||
764 | void __init dm355_register_clocks(void) | |
765 | { | |
766 | /* PLL1 and PSC are registered in dm355_init_time() */ | |
767 | platform_device_register(&dm355_pll2_device); | |
95a3477f KH |
768 | } |
769 | ||
62a2d6cd LP |
770 | int __init dm355_init_video(struct vpfe_config *vpfe_cfg, |
771 | struct vpbe_config *vpbe_cfg) | |
772 | { | |
773 | if (vpfe_cfg || vpbe_cfg) | |
774 | platform_device_register(&dm355_vpss_device); | |
775 | ||
776 | if (vpfe_cfg) { | |
777 | vpfe_capture_dev.dev.platform_data = vpfe_cfg; | |
778 | platform_device_register(&dm355_ccdc_dev); | |
779 | platform_device_register(&vpfe_capture_dev); | |
780 | } | |
781 | ||
782 | if (vpbe_cfg) { | |
783 | dm355_vpbe_dev.dev.platform_data = vpbe_cfg; | |
784 | platform_device_register(&dm355_osd_dev); | |
785 | platform_device_register(&dm355_venc_dev); | |
786 | platform_device_register(&dm355_vpbe_dev); | |
787 | platform_device_register(&dm355_vpbe_display); | |
788 | } | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
fd0f4275 BG |
793 | static const struct davinci_aintc_config dm355_aintc_config = { |
794 | .reg = { | |
795 | .start = DAVINCI_ARM_INTC_BASE, | |
796 | .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, | |
797 | .flags = IORESOURCE_MEM, | |
798 | }, | |
799 | .num_irqs = 64, | |
800 | .prios = dm355_default_priorities, | |
801 | }; | |
802 | ||
de4f82a2 BG |
803 | void __init dm355_init_irq(void) |
804 | { | |
06a28716 | 805 | davinci_aintc_init(&dm355_aintc_config); |
de4f82a2 BG |
806 | } |
807 | ||
95a3477f KH |
808 | static int __init dm355_init_devices(void) |
809 | { | |
7ab388e8 | 810 | struct platform_device *edma_pdev; |
1233090c SN |
811 | int ret = 0; |
812 | ||
95a3477f KH |
813 | if (!cpu_is_davinci_dm355()) |
814 | return 0; | |
815 | ||
816 | davinci_cfg_reg(DM355_INT_EDMA_CC); | |
7ab388e8 PU |
817 | edma_pdev = platform_device_register_full(&dm355_edma_device); |
818 | if (IS_ERR(edma_pdev)) { | |
819 | pr_warn("%s: Failed to register eDMA\n", __func__); | |
820 | return PTR_ERR(edma_pdev); | |
821 | } | |
51e68e27 | 822 | |
1233090c SN |
823 | ret = davinci_init_wdt(); |
824 | if (ret) | |
825 | pr_warn("%s: watchdog init failed: %d\n", __func__, ret); | |
826 | ||
827 | return ret; | |
95a3477f KH |
828 | } |
829 | postcore_initcall(dm355_init_devices); |