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ARM: davinci: remove watchdog reset
[linux-2.6-block.git] / arch / arm / mach-davinci / devices-da8xx.c
CommitLineData
55c79a40
MG		 1/*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
55c79a40
MG		 13#include <linux/init.h>
14#include <linux/platform_device.h>
5c71d618 15#include <linux/dma-contiguous.h>
55c79a40 16#include <linux/serial_8250.h>
cbb2c961
SN		 17#include <linux/ahci_platform.h>
18#include <linux/clk.h>
7b6d864b 19#include <linux/reboot.h>
1ce9300b 20#include <linux/dmaengine.h>
55c79a40
MG		 21
22#include <mach/cputype.h>
23#include <mach/common.h>
24#include <mach/time.h>
25#include <mach/da8xx.h>
00bacfbf 26#include <mach/clock.h>
3acf731c
AB		 27#include "cpuidle.h"
28#include "sram.h"
55c79a40
MG		 29
30#include "clock.h"
896f66b7 31#include "asp.h"
55c79a40
MG		 32
33#define DA8XX_TPCC_BASE 0x01c00000
34#define DA8XX_TPTC0_BASE 0x01c08000
35#define DA8XX_TPTC1_BASE 0x01c08400
36#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
37#define DA8XX_I2C0_BASE 0x01c22000
8ac764e3 38#define DA8XX_RTC_BASE 0x01c23000
8e0d72d2 39#define DA8XX_PRUSS_MEM_BASE 0x01c30000
8ac764e3
SS		 40#define DA8XX_MMCSD0_BASE 0x01c40000
41#define DA8XX_SPI0_BASE 0x01c41000
42#define DA830_SPI1_BASE 0x01e12000
43#define DA8XX_LCD_CNTRL_BASE 0x01e13000
cbb2c961 44#define DA850_SATA_BASE 0x01e18000
8ac764e3 45#define DA850_MMCSD1_BASE 0x01e1b000
55c79a40
MG		 46#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
47#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
48#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
49#define DA8XX_EMAC_MDIO_BASE 0x01e24000
55c79a40 50#define DA8XX_I2C1_BASE 0x01e28000
8ac764e3
SS		 51#define DA850_TPCC1_BASE 0x01e30000
52#define DA850_TPTC2_BASE 0x01e38000
9e7d24f6 53#define DA850_SPI1_BASE 0x01f0e000
8ac764e3 54#define DA8XX_DDR2_CTL_BASE 0xb0000000
55c79a40
MG		 55
56#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
57#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
58#define DA8XX_EMAC_RAM_OFFSET 0x0000
55c79a40
MG		 59#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
60
d2de0582
SN		 61void __iomem *da8xx_syscfg0_base;
62void __iomem *da8xx_syscfg1_base;
6a28adef 63
19955c3d 64static struct plat_serial8250_port da8xx_serial0_pdata[] = {
55c79a40
MG		 65 {
66 .mapbase = DA8XX_UART0_BASE,
67 .irq = IRQ_DA8XX_UARTINT0,
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
69 UPF_IOREMAP,
70 .iotype = UPIO_MEM,
71 .regshift = 2,
72 },
19955c3d
MP		 73 {
74 .flags = 0,
75 }
76};
77static struct plat_serial8250_port da8xx_serial1_pdata[] = {
55c79a40
MG		 78 {
79 .mapbase = DA8XX_UART1_BASE,
80 .irq = IRQ_DA8XX_UARTINT1,
81 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
82 UPF_IOREMAP,
83 .iotype = UPIO_MEM,
84 .regshift = 2,
85 },
19955c3d
MP		 86 {
87 .flags = 0,
88 }
89};
90static struct plat_serial8250_port da8xx_serial2_pdata[] = {
55c79a40
MG		 91 {
92 .mapbase = DA8XX_UART2_BASE,
93 .irq = IRQ_DA8XX_UARTINT2,
94 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
95 UPF_IOREMAP,
96 .iotype = UPIO_MEM,
97 .regshift = 2,
98 },
99 {
100 .flags = 0,
19955c3d 101 }
55c79a40
MG		 102};
103
19955c3d
MP		 104struct platform_device da8xx_serial_device[] = {
105 {
106 .name = "serial8250",
107 .id = PLAT8250_DEV_PLATFORM,
108 .dev = {
109 .platform_data = da8xx_serial0_pdata,
110 }
111 },
112 {
113 .name = "serial8250",
114 .id = PLAT8250_DEV_PLATFORM1,
115 .dev = {
116 .platform_data = da8xx_serial1_pdata,
117 }
55c79a40 118 },
19955c3d
MP		 119 {
120 .name = "serial8250",
121 .id = PLAT8250_DEV_PLATFORM2,
122 .dev = {
123 .platform_data = da8xx_serial2_pdata,
124 }
125 },
126 {
127 }
55c79a40
MG		 128};
129
6cba4355 130static s8 da8xx_queue_priority_mapping[][2] = {
55c79a40
MG		 131 /* {event queue no, Priority} */
132 {0, 3},
133 {1, 7},
134 {-1, -1}
135};
136
6cba4355 137static s8 da850_queue_priority_mapping[][2] = {
3f995f2f
SR		 138 /* {event queue no, Priority} */
139 {0, 3},
140 {-1, -1}
141};
142
d4cb7f40 143static struct edma_soc_info da8xx_edma0_pdata = {
bc3ac9f3 144 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 145 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 146};
147
d4cb7f40
PU		 148static struct edma_soc_info da850_edma1_pdata = {
149 .queue_priority_mapping = da850_queue_priority_mapping,
150 .default_queue = EVENTQ_0,
55c79a40
MG		 151};
152
d4cb7f40 153static struct resource da8xx_edma0_resources[] = {
3f995f2f 154 {
d4cb7f40 155 .name = "edma3_cc",
55c79a40
MG		 156 .start = DA8XX_TPCC_BASE,
157 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 {
d4cb7f40 161 .name = "edma3_tc0",
55c79a40
MG		 162 .start = DA8XX_TPTC0_BASE,
163 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
164 .flags = IORESOURCE_MEM,
165 },
166 {
d4cb7f40 167 .name = "edma3_tc1",
55c79a40
MG		 168 .start = DA8XX_TPTC1_BASE,
169 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
170 .flags = IORESOURCE_MEM,
171 },
172 {
d4cb7f40 173 .name = "edma3_ccint",
2259bbd4 174 .start = IRQ_DA8XX_CCINT0,
55c79a40
MG		 175 .flags = IORESOURCE_IRQ,
176 },
177 {
d4cb7f40 178 .name = "edma3_ccerrint",
55c79a40
MG		 179 .start = IRQ_DA8XX_CCERRINT,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
d4cb7f40 184static struct resource da850_edma1_resources[] = {
3f995f2f 185 {
d4cb7f40 186 .name = "edma3_cc",
3f995f2f
SR		 187 .start = DA850_TPCC1_BASE,
188 .end = DA850_TPCC1_BASE + SZ_32K - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
d4cb7f40 192 .name = "edma3_tc0",
3f995f2f
SR		 193 .start = DA850_TPTC2_BASE,
194 .end = DA850_TPTC2_BASE + SZ_1K - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 {
d4cb7f40 198 .name = "edma3_ccint",
3f995f2f
SR		 199 .start = IRQ_DA850_CCINT1,
200 .flags = IORESOURCE_IRQ,
201 },
202 {
d4cb7f40 203 .name = "edma3_ccerrint",
3f995f2f
SR		 204 .start = IRQ_DA850_CCERRINT1,
205 .flags = IORESOURCE_IRQ,
206 },
207};
208
7ab388e8 209static const struct platform_device_info da8xx_edma0_device __initconst = {
55c79a40 210 .name = "edma",
d4cb7f40 211 .id = 0,
cef5b0da 212 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 213 .res = da8xx_edma0_resources,
214 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
215 .data = &da8xx_edma0_pdata,
216 .size_data = sizeof(da8xx_edma0_pdata),
3f995f2f
SR		 217};
218
7ab388e8 219static const struct platform_device_info da850_edma1_device __initconst = {
3f995f2f 220 .name = "edma",
d4cb7f40 221 .id = 1,
cef5b0da 222 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 223 .res = da850_edma1_resources,
224 .num_res = ARRAY_SIZE(da850_edma1_resources),
225 .data = &da850_edma1_pdata,
226 .size_data = sizeof(da850_edma1_pdata),
55c79a40
MG		 227};
228
1ce9300b
PU		 229static const struct dma_slave_map da830_edma_map[] = {
230 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
231 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
232 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
233 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
234 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
235 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
236 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
237 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
238 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
239 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
240 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
241 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
242};
243
a941c503 244int __init da830_register_edma(struct edma_rsv_info *rsv)
55c79a40 245{
7ab388e8
PU		 246 struct platform_device *edma_pdev;
247
d4cb7f40 248 da8xx_edma0_pdata.rsv = rsv;
3f995f2f 249
1ce9300b
PU		 250 da8xx_edma0_pdata.slave_map = da830_edma_map;
251 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
252
7ab388e8 253 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
a8bc4f0a 254 return PTR_ERR_OR_ZERO(edma_pdev);
a941c503
RS		 255}
256
1ce9300b
PU		 257static const struct dma_slave_map da850_edma0_map[] = {
258 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
259 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
260 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
261 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
262 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
263 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
264 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
265 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
266 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
267 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
268 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
269 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
270};
271
272static const struct dma_slave_map da850_edma1_map[] = {
273 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
274 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
275};
276
a941c503
RS		 277int __init da850_register_edma(struct edma_rsv_info *rsv[2])
278{
7ab388e8 279 struct platform_device *edma_pdev;
d4cb7f40 280
a941c503 281 if (rsv) {
d4cb7f40
PU		 282 da8xx_edma0_pdata.rsv = rsv[0];
283 da850_edma1_pdata.rsv = rsv[1];
a941c503 284 }
3f995f2f 285
1ce9300b
PU		 286 da8xx_edma0_pdata.slave_map = da850_edma0_map;
287 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
288
7ab388e8
PU		 289 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
290 if (IS_ERR(edma_pdev)) {
d4cb7f40 291 pr_warn("%s: Failed to register eDMA0\n", __func__);
7ab388e8 292 return PTR_ERR(edma_pdev);
d4cb7f40 293 }
1ce9300b
PU		 294
295 da850_edma1_pdata.slave_map = da850_edma1_map;
296 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
297
7ab388e8 298 edma_pdev = platform_device_register_full(&da850_edma1_device);
a8bc4f0a 299 return PTR_ERR_OR_ZERO(edma_pdev);
55c79a40
MG		 300}
301
302static struct resource da8xx_i2c_resources0[] = {
303 {
304 .start = DA8XX_I2C0_BASE,
305 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = IRQ_DA8XX_I2CINT0,
310 .end = IRQ_DA8XX_I2CINT0,
311 .flags = IORESOURCE_IRQ,
312 },
313};
314
315static struct platform_device da8xx_i2c_device0 = {
316 .name = "i2c_davinci",
317 .id = 1,
318 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
319 .resource = da8xx_i2c_resources0,
320};
321
322static struct resource da8xx_i2c_resources1[] = {
323 {
324 .start = DA8XX_I2C1_BASE,
325 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
326 .flags = IORESOURCE_MEM,
327 },
328 {
329 .start = IRQ_DA8XX_I2CINT1,
330 .end = IRQ_DA8XX_I2CINT1,
331 .flags = IORESOURCE_IRQ,
332 },
333};
334
335static struct platform_device da8xx_i2c_device1 = {
336 .name = "i2c_davinci",
337 .id = 2,
338 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
339 .resource = da8xx_i2c_resources1,
340};
341
342int __init da8xx_register_i2c(int instance,
343 struct davinci_i2c_platform_data *pdata)
344{
345 struct platform_device *pdev;
346
347 if (instance == 0)
348 pdev = &da8xx_i2c_device0;
349 else if (instance == 1)
350 pdev = &da8xx_i2c_device1;
351 else
352 return -EINVAL;
353
354 pdev->dev.platform_data = pdata;
355 return platform_device_register(pdev);
356}
357
358static struct resource da8xx_watchdog_resources[] = {
359 {
360 .start = DA8XX_WDOG_BASE,
361 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
362 .flags = IORESOURCE_MEM,
363 },
364};
365
19c7c0d8 366static struct platform_device da8xx_wdt_device = {
84374812 367 .name = "davinci-wdt",
55c79a40
MG		 368 .id = -1,
369 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
370 .resource = da8xx_watchdog_resources,
371};
372
373int __init da8xx_register_watchdog(void)
374{
c78a5bc2 375 return platform_device_register(&da8xx_wdt_device);
55c79a40
MG		 376}
377
378static struct resource da8xx_emac_resources[] = {
379 {
380 .start = DA8XX_EMAC_CPPI_PORT_BASE,
d22960c8 381 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
55c79a40
MG		 382 .flags = IORESOURCE_MEM,
383 },
384 {
385 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
386 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
387 .flags = IORESOURCE_IRQ,
388 },
389 {
390 .start = IRQ_DA8XX_C0_RX_PULSE,
391 .end = IRQ_DA8XX_C0_RX_PULSE,
392 .flags = IORESOURCE_IRQ,
393 },
394 {
395 .start = IRQ_DA8XX_C0_TX_PULSE,
396 .end = IRQ_DA8XX_C0_TX_PULSE,
397 .flags = IORESOURCE_IRQ,
398 },
399 {
400 .start = IRQ_DA8XX_C0_MISC_PULSE,
401 .end = IRQ_DA8XX_C0_MISC_PULSE,
402 .flags = IORESOURCE_IRQ,
403 },
404};
405
406struct emac_platform_data da8xx_emac_pdata = {
407 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
408 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
409 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
55c79a40
MG		 410 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
411 .version = EMAC_VERSION_2,
412};
413
414static struct platform_device da8xx_emac_device = {
415 .name = "davinci_emac",
416 .id = 1,
417 .dev = {
418 .platform_data = &da8xx_emac_pdata,
419 },
420 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
421 .resource = da8xx_emac_resources,
422};
423
d22960c8
CC		 424static struct resource da8xx_mdio_resources[] = {
425 {
426 .start = DA8XX_EMAC_MDIO_BASE,
427 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
428 .flags = IORESOURCE_MEM,
429 },
430};
431
432static struct platform_device da8xx_mdio_device = {
433 .name = "davinci_mdio",
434 .id = 0,
435 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
436 .resource = da8xx_mdio_resources,
437};
438
31f53cf3
MG		 439int __init da8xx_register_emac(void)
440{
d22960c8
CC		 441 int ret;
442
443 ret = platform_device_register(&da8xx_mdio_device);
444 if (ret < 0)
445 return ret;
46c18334
LP		 446
447 return platform_device_register(&da8xx_emac_device);
31f53cf3
MG		 448}
449
e33ef5e3
C		 450static struct resource da830_mcasp1_resources[] = {
451 {
ee880dbd 452 .name = "mpu",
e33ef5e3
C		 453 .start = DAVINCI_DA830_MCASP1_REG_BASE,
454 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 /* TX event */
458 {
184981d2 459 .name = "tx",
e33ef5e3
C		 460 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
461 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
462 .flags = IORESOURCE_DMA,
463 },
464 /* RX event */
465 {
184981d2 466 .name = "rx",
e33ef5e3
C		 467 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
468 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
469 .flags = IORESOURCE_DMA,
470 },
80f7d0e0
PU		 471 {
472 .name = "common",
473 .start = IRQ_DA8XX_MCASPINT,
474 .flags = IORESOURCE_IRQ,
475 },
e33ef5e3
C		 476};
477
478static struct platform_device da830_mcasp1_device = {
479 .name = "davinci-mcasp",
480 .id = 1,
481 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
482 .resource = da830_mcasp1_resources,
483};
484
3775c313
PU		 485static struct resource da830_mcasp2_resources[] = {
486 {
487 .name = "mpu",
488 .start = DAVINCI_DA830_MCASP2_REG_BASE,
489 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 /* TX event */
493 {
494 .name = "tx",
495 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
496 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
497 .flags = IORESOURCE_DMA,
498 },
499 /* RX event */
500 {
501 .name = "rx",
502 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
503 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
504 .flags = IORESOURCE_DMA,
505 },
506 {
507 .name = "common",
508 .start = IRQ_DA8XX_MCASPINT,
509 .flags = IORESOURCE_IRQ,
510 },
511};
512
513static struct platform_device da830_mcasp2_device = {
514 .name = "davinci-mcasp",
515 .id = 2,
516 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
517 .resource = da830_mcasp2_resources,
518};
519
491214e1
C		 520static struct resource da850_mcasp_resources[] = {
521 {
ee880dbd 522 .name = "mpu",
491214e1
C		 523 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
524 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
525 .flags = IORESOURCE_MEM,
526 },
527 /* TX event */
528 {
184981d2 529 .name = "tx",
491214e1
C		 530 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
531 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
532 .flags = IORESOURCE_DMA,
533 },
534 /* RX event */
535 {
184981d2 536 .name = "rx",
491214e1
C		 537 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
538 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
539 .flags = IORESOURCE_DMA,
540 },
80f7d0e0
PU		 541 {
542 .name = "common",
543 .start = IRQ_DA8XX_MCASPINT,
544 .flags = IORESOURCE_IRQ,
545 },
491214e1
C		 546};
547
548static struct platform_device da850_mcasp_device = {
549 .name = "davinci-mcasp",
550 .id = 0,
551 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
552 .resource = da850_mcasp_resources,
553};
554
b8864aa4 555void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
e33ef5e3 556{
c96aacb1
PU		 557 struct platform_device *pdev;
558
559 switch (id) {
560 case 0:
561 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
562 pdev = &da850_mcasp_device;
563 break;
564 case 1:
565 /* Valid for DA830/OMAP-L137 only */
566 if (!cpu_is_davinci_da830())
567 return;
568 pdev = &da830_mcasp1_device;
569 break;
3775c313
PU		 570 case 2:
571 /* Valid for DA830/OMAP-L137 only */
572 if (!cpu_is_davinci_da830())
573 return;
574 pdev = &da830_mcasp2_device;
575 break;
c96aacb1
PU		 576 default:
577 return;
e33ef5e3 578 }
c96aacb1
PU		 579
580 pdev->dev.platform_data = pdata;
581 platform_device_register(pdev);
e33ef5e3 582}
5cbdf276 583
8e0d72d2
MP		 584static struct resource da8xx_pruss_resources[] = {
585 {
586 .start = DA8XX_PRUSS_MEM_BASE,
587 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
588 .flags = IORESOURCE_MEM,
589 },
590 {
591 .start = IRQ_DA8XX_EVTOUT0,
592 .end = IRQ_DA8XX_EVTOUT0,
593 .flags = IORESOURCE_IRQ,
594 },
595 {
596 .start = IRQ_DA8XX_EVTOUT1,
597 .end = IRQ_DA8XX_EVTOUT1,
598 .flags = IORESOURCE_IRQ,
599 },
600 {
601 .start = IRQ_DA8XX_EVTOUT2,
602 .end = IRQ_DA8XX_EVTOUT2,
603 .flags = IORESOURCE_IRQ,
604 },
605 {
606 .start = IRQ_DA8XX_EVTOUT3,
607 .end = IRQ_DA8XX_EVTOUT3,
608 .flags = IORESOURCE_IRQ,
609 },
610 {
611 .start = IRQ_DA8XX_EVTOUT4,
612 .end = IRQ_DA8XX_EVTOUT4,
613 .flags = IORESOURCE_IRQ,
614 },
615 {
616 .start = IRQ_DA8XX_EVTOUT5,
617 .end = IRQ_DA8XX_EVTOUT5,
618 .flags = IORESOURCE_IRQ,
619 },
620 {
621 .start = IRQ_DA8XX_EVTOUT6,
622 .end = IRQ_DA8XX_EVTOUT6,
623 .flags = IORESOURCE_IRQ,
624 },
625 {
626 .start = IRQ_DA8XX_EVTOUT7,
627 .end = IRQ_DA8XX_EVTOUT7,
628 .flags = IORESOURCE_IRQ,
629 },
630};
631
632static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
633 .pintc_base = 0x4000,
634};
635
636static struct platform_device da8xx_uio_pruss_dev = {
637 .name = "pruss_uio",
638 .id = -1,
639 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
640 .resource = da8xx_pruss_resources,
641 .dev = {
642 .coherent_dma_mask = DMA_BIT_MASK(32),
643 .platform_data = &da8xx_uio_pruss_pdata,
644 }
645};
646
647int __init da8xx_register_uio_pruss(void)
648{
649 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
650 return platform_device_register(&da8xx_uio_pruss_dev);
651}
652
5cbdf276 653static struct lcd_ctrl_config lcd_cfg = {
3b43ad20 654 .panel_shade = COLOR_ACTIVE,
5cbdf276 655 .bpp = 16,
5cbdf276
SR		 656};
657
b9e6342b
MG		 658struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
659 .manu_name = "sharp",
660 .controller_data = &lcd_cfg,
661 .type = "Sharp_LCD035Q3DG01",
662};
663
664struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
665 .manu_name = "sharp",
666 .controller_data = &lcd_cfg,
667 .type = "Sharp_LK043T1DG01",
5cbdf276
SR		 668};
669
670static struct resource da8xx_lcdc_resources[] = {
671 [0] = { /* registers */
672 .start = DA8XX_LCD_CNTRL_BASE,
673 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
674 .flags = IORESOURCE_MEM,
675 },
676 [1] = { /* interrupt */
677 .start = IRQ_DA8XX_LCDINT,
678 .end = IRQ_DA8XX_LCDINT,
679 .flags = IORESOURCE_IRQ,
680 },
681};
682
b9e6342b 683static struct platform_device da8xx_lcdc_device = {
5cbdf276
SR		 684 .name = "da8xx_lcdc",
685 .id = 0,
686 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
687 .resource = da8xx_lcdc_resources,
5cbdf276
SR		 688};
689
b9e6342b 690int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
5cbdf276 691{
b9e6342b
MG		 692 da8xx_lcdc_device.dev.platform_data = pdata;
693 return platform_device_register(&da8xx_lcdc_device);
5cbdf276 694}
700691f2 695
f606d38d
KS		 696static struct resource da8xx_gpio_resources[] = {
697 { /* registers */
698 .start = DA8XX_GPIO_BASE,
699 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
700 .flags = IORESOURCE_MEM,
701 },
702 { /* interrupt */
703 .start = IRQ_DA8XX_GPIO0,
704 .end = IRQ_DA8XX_GPIO8,
705 .flags = IORESOURCE_IRQ,
706 },
707};
708
709static struct platform_device da8xx_gpio_device = {
710 .name = "davinci_gpio",
711 .id = -1,
712 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
713 .resource = da8xx_gpio_resources,
714};
715
716int __init da8xx_register_gpio(void *pdata)
717{
718 da8xx_gpio_device.dev.platform_data = pdata;
719 return platform_device_register(&da8xx_gpio_device);
720}
721
700691f2
SR		 722static struct resource da8xx_mmcsd0_resources[] = {
723 { /* registers */
724 .start = DA8XX_MMCSD0_BASE,
725 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
726 .flags = IORESOURCE_MEM,
727 },
728 { /* interrupt */
729 .start = IRQ_DA8XX_MMCSDINT0,
730 .end = IRQ_DA8XX_MMCSDINT0,
731 .flags = IORESOURCE_IRQ,
732 },
700691f2
SR		 733};
734
735static struct platform_device da8xx_mmcsd0_device = {
d7ca4c75 736 .name = "da830-mmc",
700691f2
SR		 737 .id = 0,
738 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
739 .resource = da8xx_mmcsd0_resources,
740};
741
742int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
743{
744 da8xx_mmcsd0_device.dev.platform_data = config;
745 return platform_device_register(&da8xx_mmcsd0_device);
746}
c51df70b 747
b8241aef
JK		 748#ifdef CONFIG_ARCH_DAVINCI_DA850
749static struct resource da850_mmcsd1_resources[] = {
750 { /* registers */
751 .start = DA850_MMCSD1_BASE,
752 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
753 .flags = IORESOURCE_MEM,
754 },
755 { /* interrupt */
756 .start = IRQ_DA850_MMCSDINT0_1,
757 .end = IRQ_DA850_MMCSDINT0_1,
758 .flags = IORESOURCE_IRQ,
759 },
b8241aef
JK		 760};
761
762static struct platform_device da850_mmcsd1_device = {
d7ca4c75 763 .name = "da830-mmc",
b8241aef
JK		 764 .id = 1,
765 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
766 .resource = da850_mmcsd1_resources,
767};
768
769int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
770{
771 da850_mmcsd1_device.dev.platform_data = config;
772 return platform_device_register(&da850_mmcsd1_device);
773}
774#endif
775
5c71d618
RT		 776static struct resource da8xx_rproc_resources[] = {
777 { /* DSP boot address */
6724a05f 778 .name = "host1cfg",
5c71d618
RT		 779 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
780 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
781 .flags = IORESOURCE_MEM,
782 },
783 { /* DSP interrupt registers */
6724a05f 784 .name = "chipsig",
5c71d618
RT		 785 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
786 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
787 .flags = IORESOURCE_MEM,
788 },
14ff86bc
SA		 789 { /* DSP L2 RAM */
790 .name = "l2sram",
791 .start = DA8XX_DSP_L2_RAM_BASE,
792 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
793 .flags = IORESOURCE_MEM,
794 },
795 { /* DSP L1P RAM */
796 .name = "l1pram",
797 .start = DA8XX_DSP_L1P_RAM_BASE,
798 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
799 .flags = IORESOURCE_MEM,
800 },
801 { /* DSP L1D RAM */
802 .name = "l1dram",
803 .start = DA8XX_DSP_L1D_RAM_BASE,
804 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
805 .flags = IORESOURCE_MEM,
806 },
5c71d618
RT		 807 { /* dsp irq */
808 .start = IRQ_DA8XX_CHIPINT0,
809 .end = IRQ_DA8XX_CHIPINT0,
810 .flags = IORESOURCE_IRQ,
811 },
812};
813
814static struct platform_device da8xx_dsp = {
815 .name = "davinci-rproc",
816 .dev = {
817 .coherent_dma_mask = DMA_BIT_MASK(32),
818 },
819 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
820 .resource = da8xx_rproc_resources,
821};
822
f97f0357
SA		 823static bool rproc_mem_inited __initdata;
824
5c71d618
RT		 825#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
826
827static phys_addr_t rproc_base __initdata;
828static unsigned long rproc_size __initdata;
829
830static int __init early_rproc_mem(char *p)
831{
832 char *endp;
833
834 if (p == NULL)
835 return 0;
836
837 rproc_size = memparse(p, &endp);
838 if (*endp == '@')
839 rproc_base = memparse(endp + 1, NULL);
840
841 return 0;
842}
843early_param("rproc_mem", early_rproc_mem);
844
845void __init da8xx_rproc_reserve_cma(void)
846{
847 int ret;
848
849 if (!rproc_base || !rproc_size) {
850 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
851 " 'nn' and 'address' must both be non-zero\n",
852 __func__);
853
854 return;
855 }
856
857 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
858 __func__, rproc_size, (unsigned long)rproc_base);
859
860 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
861 if (ret)
862 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
f97f0357
SA		 863 else
864 rproc_mem_inited = true;
5c71d618
RT		 865}
866
867#else
868
869void __init da8xx_rproc_reserve_cma(void)
870{
871}
872
873#endif
874
875int __init da8xx_register_rproc(void)
876{
877 int ret;
878
f97f0357
SA		 879 if (!rproc_mem_inited) {
880 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
881 __func__);
882 return -ENOMEM;
883 }
884
5c71d618
RT		 885 ret = platform_device_register(&da8xx_dsp);
886 if (ret)
887 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
888
889 return ret;
890};
891
c51df70b
MG		 892static struct resource da8xx_rtc_resources[] = {
893 {
894 .start = DA8XX_RTC_BASE,
895 .end = DA8XX_RTC_BASE + SZ_4K - 1,
896 .flags = IORESOURCE_MEM,
897 },
898 { /* timer irq */
899 .start = IRQ_DA8XX_RTC,
900 .end = IRQ_DA8XX_RTC,
901 .flags = IORESOURCE_IRQ,
902 },
903 { /* alarm irq */
904 .start = IRQ_DA8XX_RTC,
905 .end = IRQ_DA8XX_RTC,
906 .flags = IORESOURCE_IRQ,
907 },
908};
909
910static struct platform_device da8xx_rtc_device = {
852168c9 911 .name = "da830-rtc",
c51df70b
MG		 912 .id = -1,
913 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
914 .resource = da8xx_rtc_resources,
915};
916
917int da8xx_register_rtc(void)
918{
79eb1636 919 return platform_device_register(&da8xx_rtc_device);
c51df70b 920}
1960e693 921
948c66df
SN		 922static void __iomem *da8xx_ddr2_ctlr_base;
923void __iomem * __init da8xx_get_mem_ctlr(void)
924{
925 if (da8xx_ddr2_ctlr_base)
926 return da8xx_ddr2_ctlr_base;
927
928 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
929 if (!da8xx_ddr2_ctlr_base)
d2e0c18a 930 pr_warn("%s: Unable to map DDR2 controller", __func__);
948c66df
SN		 931
932 return da8xx_ddr2_ctlr_base;
933}
934
1960e693
SN		 935static struct resource da8xx_cpuidle_resources[] = {
936 {
937 .start = DA8XX_DDR2_CTL_BASE,
938 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
939 .flags = IORESOURCE_MEM,
940 },
941};
942
943/* DA8XX devices support DDR2 power down */
944static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
945 .ddr2_pdown = 1,
946};
947
948
949static struct platform_device da8xx_cpuidle_device = {
950 .name = "cpuidle-davinci",
951 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
952 .resource = da8xx_cpuidle_resources,
953 .dev = {
954 .platform_data = &da8xx_cpuidle_pdata,
955 },
956};
957
958int __init da8xx_register_cpuidle(void)
959{
948c66df
SN		 960 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
961
1960e693
SN		 962 return platform_device_register(&da8xx_cpuidle_device);
963}
54ce6883
MW		 964
965static struct resource da8xx_spi0_resources[] = {
966 [0] = {
967 .start = DA8XX_SPI0_BASE,
968 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
969 .flags = IORESOURCE_MEM,
970 },
971 [1] = {
972 .start = IRQ_DA8XX_SPINT0,
973 .end = IRQ_DA8XX_SPINT0,
974 .flags = IORESOURCE_IRQ,
975 },
54ce6883
MW		 976};
977
978static struct resource da8xx_spi1_resources[] = {
979 [0] = {
9e7d24f6
SS		 980 .start = DA830_SPI1_BASE,
981 .end = DA830_SPI1_BASE + SZ_4K - 1,
54ce6883
MW		 982 .flags = IORESOURCE_MEM,
983 },
984 [1] = {
985 .start = IRQ_DA8XX_SPINT1,
986 .end = IRQ_DA8XX_SPINT1,
987 .flags = IORESOURCE_IRQ,
988 },
54ce6883
MW		 989};
990
0273612c 991static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
54ce6883
MW		 992 [0] = {
993 .version = SPI_VERSION_2,
994 .intr_line = 1,
995 .dma_event_q = EVENTQ_0,
1b0838b5 996 .prescaler_limit = 2,
54ce6883
MW		 997 },
998 [1] = {
999 .version = SPI_VERSION_2,
1000 .intr_line = 1,
1001 .dma_event_q = EVENTQ_0,
1b0838b5 1002 .prescaler_limit = 2,
54ce6883
MW		 1003 },
1004};
1005
1006static struct platform_device da8xx_spi_device[] = {
1007 [0] = {
1008 .name = "spi_davinci",
1009 .id = 0,
1010 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1011 .resource = da8xx_spi0_resources,
1012 .dev = {
1013 .platform_data = &da8xx_spi_pdata[0],
1014 },
1015 },
1016 [1] = {
1017 .name = "spi_davinci",
1018 .id = 1,
1019 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1020 .resource = da8xx_spi1_resources,
1021 .dev = {
1022 .platform_data = &da8xx_spi_pdata[1],
1023 },
1024 },
1025};
1026
0273612c 1027int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
54ce6883 1028{
54ce6883
MW		 1029 if (instance < 0 || instance > 1)
1030 return -EINVAL;
1031
0273612c 1032 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
54ce6883 1033
9e7d24f6
SS		 1034 if (instance == 1 && cpu_is_davinci_da850()) {
1035 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1036 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1037 }
1038
54ce6883
MW		 1039 return platform_device_register(&da8xx_spi_device[instance]);
1040}
cbb2c961
SN		 1041
1042#ifdef CONFIG_ARCH_DAVINCI_DA850
00bacfbf
BG		 1043static struct clk sata_refclk = {
1044 .name = "sata_refclk",
1045 .set_rate = davinci_simple_set_rate,
1046};
1047
1048static struct clk_lookup sata_refclk_lookup =
1049 CLK("ahci_da850", "refclk", &sata_refclk);
1050
1051int __init da850_register_sata_refclk(int rate)
1052{
1053 int ret;
1054
1055 sata_refclk.rate = rate;
1056 ret = clk_register(&sata_refclk);
1057 if (ret)
1058 return ret;
1059
1060 clkdev_add(&sata_refclk_lookup);
1061
1062 return 0;
1063}
1064
cbb2c961
SN		 1065static struct resource da850_sata_resources[] = {
1066 {
1067 .start = DA850_SATA_BASE,
1068 .end = DA850_SATA_BASE + 0x1fff,
1069 .flags = IORESOURCE_MEM,
1070 },
080c492d
BZ		 1071 {
1072 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1073 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1074 .flags = IORESOURCE_MEM,
1075 },
cbb2c961
SN		 1076 {
1077 .start = IRQ_DA850_SATAINT,
1078 .flags = IORESOURCE_IRQ,
1079 },
1080};
1081
cbb2c961
SN		 1082static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1083
1084static struct platform_device da850_sata_device = {
080c492d 1085 .name = "ahci_da850",
cbb2c961
SN		 1086 .id = -1,
1087 .dev = {
cbb2c961
SN		 1088 .dma_mask = &da850_sata_dmamask,
1089 .coherent_dma_mask = DMA_BIT_MASK(32),
1090 },
1091 .num_resources = ARRAY_SIZE(da850_sata_resources),
1092 .resource = da850_sata_resources,
1093};
1094
1095int __init da850_register_sata(unsigned long refclkpn)
1096{
00bacfbf
BG		 1097 int ret;
1098
00bacfbf
BG		 1099 ret = da850_register_sata_refclk(refclkpn);
1100 if (ret)
1101 return ret;
1102
cbb2c961
SN		 1103 return platform_device_register(&da850_sata_device);
1104}
1105#endif
0fcd5411 1106
bdec5a6b 1107static struct regmap *da8xx_cfgchip;
0fcd5411 1108
bdec5a6b
DL		 1109/* regmap doesn't make a copy of this, so we need to keep the pointer around */
1110static const char da8xx_cfgchip_name[] = "cfgchip";
0fcd5411 1111
bdec5a6b
DL		 1112static const struct regmap_config da8xx_cfgchip_config __initconst = {
1113 .name = da8xx_cfgchip_name,
1114 .reg_bits = 32,
1115 .val_bits = 32,
1116 .reg_stride = 4,
1117 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
0fcd5411
DL		 1118};
1119
bdec5a6b
DL		 1120/**
1121 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1122 *
1123 * This is for use on non-DT boards only. For DT boards, use
1124 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1125 *
1126 * Returns: Pointer to the CFGCHIP regmap or negative error code.
1127 */
1128struct regmap * __init da8xx_get_cfgchip(void)
0fcd5411 1129{
bdec5a6b
DL		 1130 if (IS_ERR_OR_NULL(da8xx_cfgchip))
1131 da8xx_cfgchip = regmap_init_mmio(NULL,
1132 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
1133 &da8xx_cfgchip_config);
1134
1135 return da8xx_cfgchip;
0fcd5411 1136}
Linux 6.x block layer and io_uring tree(s)