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dma-contiguous: remove dev_set_cma_area
[linux-2.6-block.git] / arch / arm / mach-davinci / devices-da8xx.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
55c79a40
MG		 2/*
3 * DA8XX/OMAP L1XX platform device data
4 *
5 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
6 * Derived from code that was:
7 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
55c79a40 8 */
cbb2c961 9#include <linux/ahci_platform.h>
aa1da33c 10#include <linux/clk-provider.h>
cbb2c961 11#include <linux/clk.h>
aa1da33c
DL		 12#include <linux/clkdev.h>
13#include <linux/dma-contiguous.h>
1ce9300b 14#include <linux/dmaengine.h>
aa1da33c 15#include <linux/init.h>
62e59c4e 16#include <linux/io.h>
aa1da33c
DL		 17#include <linux/platform_device.h>
18#include <linux/reboot.h>
19#include <linux/serial_8250.h>
55c79a40 20
55c79a40 21#include <mach/common.h>
aa1da33c 22#include <mach/cputype.h>
55c79a40 23#include <mach/da8xx.h>
aa1da33c
DL		 24
25#include "asp.h"
3acf731c 26#include "cpuidle.h"
544ca0b0 27#include "irqs.h"
3acf731c 28#include "sram.h"
55c79a40 29
55c79a40
MG		 30#define DA8XX_TPCC_BASE 0x01c00000
31#define DA8XX_TPTC0_BASE 0x01c08000
32#define DA8XX_TPTC1_BASE 0x01c08400
33#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
34#define DA8XX_I2C0_BASE 0x01c22000
8ac764e3 35#define DA8XX_RTC_BASE 0x01c23000
8e0d72d2 36#define DA8XX_PRUSS_MEM_BASE 0x01c30000
8ac764e3
SS		 37#define DA8XX_MMCSD0_BASE 0x01c40000
38#define DA8XX_SPI0_BASE 0x01c41000
39#define DA830_SPI1_BASE 0x01e12000
40#define DA8XX_LCD_CNTRL_BASE 0x01e13000
cbb2c961 41#define DA850_SATA_BASE 0x01e18000
8ac764e3 42#define DA850_MMCSD1_BASE 0x01e1b000
55c79a40
MG		 43#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
44#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
45#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
46#define DA8XX_EMAC_MDIO_BASE 0x01e24000
55c79a40 47#define DA8XX_I2C1_BASE 0x01e28000
8ac764e3
SS		 48#define DA850_TPCC1_BASE 0x01e30000
49#define DA850_TPTC2_BASE 0x01e38000
9e7d24f6 50#define DA850_SPI1_BASE 0x01f0e000
8ac764e3 51#define DA8XX_DDR2_CTL_BASE 0xb0000000
55c79a40
MG		 52
53#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
54#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
55#define DA8XX_EMAC_RAM_OFFSET 0x0000
55c79a40
MG		 56#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
57
d2de0582
SN		 58void __iomem *da8xx_syscfg0_base;
59void __iomem *da8xx_syscfg1_base;
6a28adef 60
19955c3d 61static struct plat_serial8250_port da8xx_serial0_pdata[] = {
55c79a40
MG		 62 {
63 .mapbase = DA8XX_UART0_BASE,
a98ca73e 64 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
55c79a40
MG		 65 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
66 UPF_IOREMAP,
67 .iotype = UPIO_MEM,
68 .regshift = 2,
69 },
19955c3d
MP		 70 {
71 .flags = 0,
72 }
73};
74static struct plat_serial8250_port da8xx_serial1_pdata[] = {
55c79a40
MG		 75 {
76 .mapbase = DA8XX_UART1_BASE,
a98ca73e 77 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
55c79a40
MG		 78 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
79 UPF_IOREMAP,
80 .iotype = UPIO_MEM,
81 .regshift = 2,
82 },
19955c3d
MP		 83 {
84 .flags = 0,
85 }
86};
87static struct plat_serial8250_port da8xx_serial2_pdata[] = {
55c79a40
MG		 88 {
89 .mapbase = DA8XX_UART2_BASE,
a98ca73e 90 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
55c79a40
MG		 91 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
92 UPF_IOREMAP,
93 .iotype = UPIO_MEM,
94 .regshift = 2,
95 },
96 {
97 .flags = 0,
19955c3d 98 }
55c79a40
MG		 99};
100
19955c3d
MP		 101struct platform_device da8xx_serial_device[] = {
102 {
103 .name = "serial8250",
104 .id = PLAT8250_DEV_PLATFORM,
105 .dev = {
106 .platform_data = da8xx_serial0_pdata,
107 }
108 },
109 {
110 .name = "serial8250",
111 .id = PLAT8250_DEV_PLATFORM1,
112 .dev = {
113 .platform_data = da8xx_serial1_pdata,
114 }
55c79a40 115 },
19955c3d
MP		 116 {
117 .name = "serial8250",
118 .id = PLAT8250_DEV_PLATFORM2,
119 .dev = {
120 .platform_data = da8xx_serial2_pdata,
121 }
122 },
123 {
124 }
55c79a40
MG		 125};
126
6cba4355 127static s8 da8xx_queue_priority_mapping[][2] = {
55c79a40
MG		 128 /* {event queue no, Priority} */
129 {0, 3},
130 {1, 7},
131 {-1, -1}
132};
133
6cba4355 134static s8 da850_queue_priority_mapping[][2] = {
3f995f2f
SR		 135 /* {event queue no, Priority} */
136 {0, 3},
137 {-1, -1}
138};
139
d4cb7f40 140static struct edma_soc_info da8xx_edma0_pdata = {
bc3ac9f3 141 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 142 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 143};
144
d4cb7f40
PU		 145static struct edma_soc_info da850_edma1_pdata = {
146 .queue_priority_mapping = da850_queue_priority_mapping,
147 .default_queue = EVENTQ_0,
55c79a40
MG		 148};
149
d4cb7f40 150static struct resource da8xx_edma0_resources[] = {
3f995f2f 151 {
d4cb7f40 152 .name = "edma3_cc",
55c79a40
MG		 153 .start = DA8XX_TPCC_BASE,
154 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
155 .flags = IORESOURCE_MEM,
156 },
157 {
d4cb7f40 158 .name = "edma3_tc0",
55c79a40
MG		 159 .start = DA8XX_TPTC0_BASE,
160 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 {
d4cb7f40 164 .name = "edma3_tc1",
55c79a40
MG		 165 .start = DA8XX_TPTC1_BASE,
166 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
167 .flags = IORESOURCE_MEM,
168 },
169 {
d4cb7f40 170 .name = "edma3_ccint",
a98ca73e 171 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
55c79a40
MG		 172 .flags = IORESOURCE_IRQ,
173 },
174 {
d4cb7f40 175 .name = "edma3_ccerrint",
a98ca73e 176 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
55c79a40
MG		 177 .flags = IORESOURCE_IRQ,
178 },
179};
180
d4cb7f40 181static struct resource da850_edma1_resources[] = {
3f995f2f 182 {
d4cb7f40 183 .name = "edma3_cc",
3f995f2f
SR		 184 .start = DA850_TPCC1_BASE,
185 .end = DA850_TPCC1_BASE + SZ_32K - 1,
186 .flags = IORESOURCE_MEM,
187 },
188 {
d4cb7f40 189 .name = "edma3_tc0",
3f995f2f
SR		 190 .start = DA850_TPTC2_BASE,
191 .end = DA850_TPTC2_BASE + SZ_1K - 1,
192 .flags = IORESOURCE_MEM,
193 },
194 {
d4cb7f40 195 .name = "edma3_ccint",
a98ca73e 196 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
3f995f2f
SR		 197 .flags = IORESOURCE_IRQ,
198 },
199 {
d4cb7f40 200 .name = "edma3_ccerrint",
a98ca73e 201 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
3f995f2f
SR		 202 .flags = IORESOURCE_IRQ,
203 },
204};
205
7ab388e8 206static const struct platform_device_info da8xx_edma0_device __initconst = {
55c79a40 207 .name = "edma",
d4cb7f40 208 .id = 0,
cef5b0da 209 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 210 .res = da8xx_edma0_resources,
211 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
212 .data = &da8xx_edma0_pdata,
213 .size_data = sizeof(da8xx_edma0_pdata),
3f995f2f
SR		 214};
215
7ab388e8 216static const struct platform_device_info da850_edma1_device __initconst = {
3f995f2f 217 .name = "edma",
d4cb7f40 218 .id = 1,
cef5b0da 219 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 220 .res = da850_edma1_resources,
221 .num_res = ARRAY_SIZE(da850_edma1_resources),
222 .data = &da850_edma1_pdata,
223 .size_data = sizeof(da850_edma1_pdata),
55c79a40
MG		 224};
225
1ce9300b
PU		 226static const struct dma_slave_map da830_edma_map[] = {
227 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
228 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
229 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
230 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
231 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
232 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
233 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
234 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
235 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
236 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
237 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
238 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
239};
240
a941c503 241int __init da830_register_edma(struct edma_rsv_info *rsv)
55c79a40 242{
7ab388e8
PU		 243 struct platform_device *edma_pdev;
244
d4cb7f40 245 da8xx_edma0_pdata.rsv = rsv;
3f995f2f 246
1ce9300b
PU		 247 da8xx_edma0_pdata.slave_map = da830_edma_map;
248 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
249
7ab388e8 250 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
a8bc4f0a 251 return PTR_ERR_OR_ZERO(edma_pdev);
a941c503
RS		 252}
253
1ce9300b
PU		 254static const struct dma_slave_map da850_edma0_map[] = {
255 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
256 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
257 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
258 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
259 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
260 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
261 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
262 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
263 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
264 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
265 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
266 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
267};
268
269static const struct dma_slave_map da850_edma1_map[] = {
270 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
271 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
272};
273
a941c503
RS		 274int __init da850_register_edma(struct edma_rsv_info *rsv[2])
275{
7ab388e8 276 struct platform_device *edma_pdev;
d4cb7f40 277
a941c503 278 if (rsv) {
d4cb7f40
PU		 279 da8xx_edma0_pdata.rsv = rsv[0];
280 da850_edma1_pdata.rsv = rsv[1];
a941c503 281 }
3f995f2f 282
1ce9300b
PU		 283 da8xx_edma0_pdata.slave_map = da850_edma0_map;
284 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
285
7ab388e8
PU		 286 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
287 if (IS_ERR(edma_pdev)) {
d4cb7f40 288 pr_warn("%s: Failed to register eDMA0\n", __func__);
7ab388e8 289 return PTR_ERR(edma_pdev);
d4cb7f40 290 }
1ce9300b
PU		 291
292 da850_edma1_pdata.slave_map = da850_edma1_map;
293 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
294
7ab388e8 295 edma_pdev = platform_device_register_full(&da850_edma1_device);
a8bc4f0a 296 return PTR_ERR_OR_ZERO(edma_pdev);
55c79a40
MG		 297}
298
299static struct resource da8xx_i2c_resources0[] = {
300 {
301 .start = DA8XX_I2C0_BASE,
302 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
303 .flags = IORESOURCE_MEM,
304 },
305 {
a98ca73e
BG		 306 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
307 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
55c79a40
MG		 308 .flags = IORESOURCE_IRQ,
309 },
310};
311
312static struct platform_device da8xx_i2c_device0 = {
313 .name = "i2c_davinci",
314 .id = 1,
315 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
316 .resource = da8xx_i2c_resources0,
317};
318
319static struct resource da8xx_i2c_resources1[] = {
320 {
321 .start = DA8XX_I2C1_BASE,
322 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
323 .flags = IORESOURCE_MEM,
324 },
325 {
a98ca73e
BG		 326 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
327 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
55c79a40
MG		 328 .flags = IORESOURCE_IRQ,
329 },
330};
331
332static struct platform_device da8xx_i2c_device1 = {
333 .name = "i2c_davinci",
334 .id = 2,
335 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
336 .resource = da8xx_i2c_resources1,
337};
338
339int __init da8xx_register_i2c(int instance,
340 struct davinci_i2c_platform_data *pdata)
341{
342 struct platform_device *pdev;
343
344 if (instance == 0)
345 pdev = &da8xx_i2c_device0;
346 else if (instance == 1)
347 pdev = &da8xx_i2c_device1;
348 else
349 return -EINVAL;
350
351 pdev->dev.platform_data = pdata;
352 return platform_device_register(pdev);
353}
354
355static struct resource da8xx_watchdog_resources[] = {
356 {
357 .start = DA8XX_WDOG_BASE,
358 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
359 .flags = IORESOURCE_MEM,
360 },
361};
362
19c7c0d8 363static struct platform_device da8xx_wdt_device = {
84374812 364 .name = "davinci-wdt",
55c79a40
MG		 365 .id = -1,
366 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
367 .resource = da8xx_watchdog_resources,
368};
369
370int __init da8xx_register_watchdog(void)
371{
c78a5bc2 372 return platform_device_register(&da8xx_wdt_device);
55c79a40
MG		 373}
374
375static struct resource da8xx_emac_resources[] = {
376 {
377 .start = DA8XX_EMAC_CPPI_PORT_BASE,
d22960c8 378 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
55c79a40
MG		 379 .flags = IORESOURCE_MEM,
380 },
381 {
a98ca73e
BG		 382 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
383 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
55c79a40
MG		 384 .flags = IORESOURCE_IRQ,
385 },
386 {
a98ca73e
BG		 387 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
388 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
55c79a40
MG		 389 .flags = IORESOURCE_IRQ,
390 },
391 {
a98ca73e
BG		 392 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
393 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
55c79a40
MG		 394 .flags = IORESOURCE_IRQ,
395 },
396 {
a98ca73e
BG		 397 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
398 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
55c79a40
MG		 399 .flags = IORESOURCE_IRQ,
400 },
401};
402
403struct emac_platform_data da8xx_emac_pdata = {
404 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
405 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
406 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
55c79a40
MG		 407 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
408 .version = EMAC_VERSION_2,
409};
410
411static struct platform_device da8xx_emac_device = {
412 .name = "davinci_emac",
413 .id = 1,
414 .dev = {
415 .platform_data = &da8xx_emac_pdata,
416 },
417 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
418 .resource = da8xx_emac_resources,
419};
420
d22960c8
CC		 421static struct resource da8xx_mdio_resources[] = {
422 {
423 .start = DA8XX_EMAC_MDIO_BASE,
424 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
425 .flags = IORESOURCE_MEM,
426 },
427};
428
429static struct platform_device da8xx_mdio_device = {
430 .name = "davinci_mdio",
431 .id = 0,
432 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
433 .resource = da8xx_mdio_resources,
434};
435
31f53cf3
MG		 436int __init da8xx_register_emac(void)
437{
d22960c8
CC		 438 int ret;
439
440 ret = platform_device_register(&da8xx_mdio_device);
441 if (ret < 0)
442 return ret;
46c18334
LP		 443
444 return platform_device_register(&da8xx_emac_device);
31f53cf3
MG		 445}
446
e33ef5e3
C		 447static struct resource da830_mcasp1_resources[] = {
448 {
ee880dbd 449 .name = "mpu",
e33ef5e3
C		 450 .start = DAVINCI_DA830_MCASP1_REG_BASE,
451 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
452 .flags = IORESOURCE_MEM,
453 },
454 /* TX event */
455 {
184981d2 456 .name = "tx",
e33ef5e3
C		 457 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
458 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
459 .flags = IORESOURCE_DMA,
460 },
461 /* RX event */
462 {
184981d2 463 .name = "rx",
e33ef5e3
C		 464 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
465 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
466 .flags = IORESOURCE_DMA,
467 },
80f7d0e0
PU		 468 {
469 .name = "common",
a98ca73e 470 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
80f7d0e0
PU		 471 .flags = IORESOURCE_IRQ,
472 },
e33ef5e3
C		 473};
474
475static struct platform_device da830_mcasp1_device = {
476 .name = "davinci-mcasp",
477 .id = 1,
478 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
479 .resource = da830_mcasp1_resources,
480};
481
3775c313
PU		 482static struct resource da830_mcasp2_resources[] = {
483 {
484 .name = "mpu",
485 .start = DAVINCI_DA830_MCASP2_REG_BASE,
486 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
487 .flags = IORESOURCE_MEM,
488 },
489 /* TX event */
490 {
491 .name = "tx",
492 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
493 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
494 .flags = IORESOURCE_DMA,
495 },
496 /* RX event */
497 {
498 .name = "rx",
499 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
500 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
501 .flags = IORESOURCE_DMA,
502 },
503 {
504 .name = "common",
a98ca73e 505 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
3775c313
PU		 506 .flags = IORESOURCE_IRQ,
507 },
508};
509
510static struct platform_device da830_mcasp2_device = {
511 .name = "davinci-mcasp",
512 .id = 2,
513 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
514 .resource = da830_mcasp2_resources,
515};
516
491214e1
C		 517static struct resource da850_mcasp_resources[] = {
518 {
ee880dbd 519 .name = "mpu",
491214e1
C		 520 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
521 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
522 .flags = IORESOURCE_MEM,
523 },
524 /* TX event */
525 {
184981d2 526 .name = "tx",
491214e1
C		 527 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
528 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
529 .flags = IORESOURCE_DMA,
530 },
531 /* RX event */
532 {
184981d2 533 .name = "rx",
491214e1
C		 534 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
535 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
536 .flags = IORESOURCE_DMA,
537 },
80f7d0e0
PU		 538 {
539 .name = "common",
a98ca73e 540 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
80f7d0e0
PU		 541 .flags = IORESOURCE_IRQ,
542 },
491214e1
C		 543};
544
545static struct platform_device da850_mcasp_device = {
546 .name = "davinci-mcasp",
547 .id = 0,
548 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
549 .resource = da850_mcasp_resources,
550};
551
b8864aa4 552void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
e33ef5e3 553{
c96aacb1
PU		 554 struct platform_device *pdev;
555
556 switch (id) {
557 case 0:
558 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
559 pdev = &da850_mcasp_device;
560 break;
561 case 1:
562 /* Valid for DA830/OMAP-L137 only */
563 if (!cpu_is_davinci_da830())
564 return;
565 pdev = &da830_mcasp1_device;
566 break;
3775c313
PU		 567 case 2:
568 /* Valid for DA830/OMAP-L137 only */
569 if (!cpu_is_davinci_da830())
570 return;
571 pdev = &da830_mcasp2_device;
572 break;
c96aacb1
PU		 573 default:
574 return;
e33ef5e3 575 }
c96aacb1
PU		 576
577 pdev->dev.platform_data = pdata;
578 platform_device_register(pdev);
e33ef5e3 579}
5cbdf276 580
8e0d72d2
MP		 581static struct resource da8xx_pruss_resources[] = {
582 {
583 .start = DA8XX_PRUSS_MEM_BASE,
584 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
585 .flags = IORESOURCE_MEM,
586 },
587 {
a98ca73e
BG		 588 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
589 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
8e0d72d2
MP		 590 .flags = IORESOURCE_IRQ,
591 },
592 {
a98ca73e
BG		 593 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
594 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
8e0d72d2
MP		 595 .flags = IORESOURCE_IRQ,
596 },
597 {
a98ca73e
BG		 598 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
599 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
8e0d72d2
MP		 600 .flags = IORESOURCE_IRQ,
601 },
602 {
a98ca73e
BG		 603 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
604 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
8e0d72d2
MP		 605 .flags = IORESOURCE_IRQ,
606 },
607 {
a98ca73e
BG		 608 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
609 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
8e0d72d2
MP		 610 .flags = IORESOURCE_IRQ,
611 },
612 {
a98ca73e
BG		 613 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
614 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
8e0d72d2
MP		 615 .flags = IORESOURCE_IRQ,
616 },
617 {
a98ca73e
BG		 618 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
619 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
8e0d72d2
MP		 620 .flags = IORESOURCE_IRQ,
621 },
622 {
a98ca73e
BG		 623 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
624 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
8e0d72d2
MP		 625 .flags = IORESOURCE_IRQ,
626 },
627};
628
629static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
630 .pintc_base = 0x4000,
631};
632
633static struct platform_device da8xx_uio_pruss_dev = {
634 .name = "pruss_uio",
635 .id = -1,
636 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
637 .resource = da8xx_pruss_resources,
638 .dev = {
639 .coherent_dma_mask = DMA_BIT_MASK(32),
640 .platform_data = &da8xx_uio_pruss_pdata,
641 }
642};
643
644int __init da8xx_register_uio_pruss(void)
645{
646 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
647 return platform_device_register(&da8xx_uio_pruss_dev);
648}
649
5cbdf276 650static struct lcd_ctrl_config lcd_cfg = {
3b43ad20 651 .panel_shade = COLOR_ACTIVE,
5cbdf276 652 .bpp = 16,
5cbdf276
SR		 653};
654
b9e6342b
MG		 655struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
656 .manu_name = "sharp",
657 .controller_data = &lcd_cfg,
658 .type = "Sharp_LCD035Q3DG01",
659};
660
661struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
662 .manu_name = "sharp",
663 .controller_data = &lcd_cfg,
664 .type = "Sharp_LK043T1DG01",
5cbdf276
SR		 665};
666
667static struct resource da8xx_lcdc_resources[] = {
668 [0] = { /* registers */
669 .start = DA8XX_LCD_CNTRL_BASE,
670 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
671 .flags = IORESOURCE_MEM,
672 },
673 [1] = { /* interrupt */
a98ca73e
BG		 674 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
675 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
5cbdf276
SR		 676 .flags = IORESOURCE_IRQ,
677 },
678};
679
b9e6342b 680static struct platform_device da8xx_lcdc_device = {
5cbdf276
SR		 681 .name = "da8xx_lcdc",
682 .id = 0,
683 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
684 .resource = da8xx_lcdc_resources,
68f2515b
BG		 685 .dev = {
686 .coherent_dma_mask = DMA_BIT_MASK(32),
687 }
5cbdf276
SR		 688};
689
b9e6342b 690int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
5cbdf276 691{
b9e6342b
MG		 692 da8xx_lcdc_device.dev.platform_data = pdata;
693 return platform_device_register(&da8xx_lcdc_device);
5cbdf276 694}
700691f2 695
f606d38d
KS		 696static struct resource da8xx_gpio_resources[] = {
697 { /* registers */
698 .start = DA8XX_GPIO_BASE,
699 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
700 .flags = IORESOURCE_MEM,
701 },
702 { /* interrupt */
a98ca73e
BG		 703 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
704 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
58a0afbf
BG		 705 .flags = IORESOURCE_IRQ,
706 },
707 {
a98ca73e
BG		 708 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
709 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
58a0afbf
BG		 710 .flags = IORESOURCE_IRQ,
711 },
712 {
a98ca73e
BG		 713 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
714 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
58a0afbf
BG		 715 .flags = IORESOURCE_IRQ,
716 },
717 {
a98ca73e
BG		 718 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
719 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
58a0afbf
BG		 720 .flags = IORESOURCE_IRQ,
721 },
722 {
a98ca73e
BG		 723 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
724 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
58a0afbf
BG		 725 .flags = IORESOURCE_IRQ,
726 },
727 {
a98ca73e
BG		 728 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
729 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
58a0afbf
BG		 730 .flags = IORESOURCE_IRQ,
731 },
732 {
a98ca73e
BG		 733 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
734 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
58a0afbf
BG		 735 .flags = IORESOURCE_IRQ,
736 },
737 {
a98ca73e
BG		 738 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
739 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
58a0afbf
BG		 740 .flags = IORESOURCE_IRQ,
741 },
742 {
a98ca73e
BG		 743 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
744 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
f606d38d
KS		 745 .flags = IORESOURCE_IRQ,
746 },
747};
748
749static struct platform_device da8xx_gpio_device = {
750 .name = "davinci_gpio",
751 .id = -1,
752 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
753 .resource = da8xx_gpio_resources,
754};
755
756int __init da8xx_register_gpio(void *pdata)
757{
758 da8xx_gpio_device.dev.platform_data = pdata;
759 return platform_device_register(&da8xx_gpio_device);
760}
761
700691f2
SR		 762static struct resource da8xx_mmcsd0_resources[] = {
763 { /* registers */
764 .start = DA8XX_MMCSD0_BASE,
765 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
766 .flags = IORESOURCE_MEM,
767 },
768 { /* interrupt */
a98ca73e
BG		 769 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
770 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
700691f2
SR		 771 .flags = IORESOURCE_IRQ,
772 },
700691f2
SR		 773};
774
775static struct platform_device da8xx_mmcsd0_device = {
d7ca4c75 776 .name = "da830-mmc",
700691f2
SR		 777 .id = 0,
778 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
779 .resource = da8xx_mmcsd0_resources,
780};
781
782int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
783{
784 da8xx_mmcsd0_device.dev.platform_data = config;
785 return platform_device_register(&da8xx_mmcsd0_device);
786}
c51df70b 787
b8241aef
JK		 788#ifdef CONFIG_ARCH_DAVINCI_DA850
789static struct resource da850_mmcsd1_resources[] = {
790 { /* registers */
791 .start = DA850_MMCSD1_BASE,
792 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
793 .flags = IORESOURCE_MEM,
794 },
795 { /* interrupt */
a98ca73e
BG		 796 .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
797 .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
b8241aef
JK		 798 .flags = IORESOURCE_IRQ,
799 },
b8241aef
JK		 800};
801
802static struct platform_device da850_mmcsd1_device = {
d7ca4c75 803 .name = "da830-mmc",
b8241aef
JK		 804 .id = 1,
805 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
806 .resource = da850_mmcsd1_resources,
807};
808
809int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
810{
811 da850_mmcsd1_device.dev.platform_data = config;
812 return platform_device_register(&da850_mmcsd1_device);
813}
814#endif
815
5c71d618
RT		 816static struct resource da8xx_rproc_resources[] = {
817 { /* DSP boot address */
6724a05f 818 .name = "host1cfg",
5c71d618
RT		 819 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
820 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
821 .flags = IORESOURCE_MEM,
822 },
823 { /* DSP interrupt registers */
6724a05f 824 .name = "chipsig",
5c71d618
RT		 825 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
826 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
827 .flags = IORESOURCE_MEM,
828 },
14ff86bc
SA		 829 { /* DSP L2 RAM */
830 .name = "l2sram",
831 .start = DA8XX_DSP_L2_RAM_BASE,
832 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
833 .flags = IORESOURCE_MEM,
834 },
835 { /* DSP L1P RAM */
836 .name = "l1pram",
837 .start = DA8XX_DSP_L1P_RAM_BASE,
838 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
839 .flags = IORESOURCE_MEM,
840 },
841 { /* DSP L1D RAM */
842 .name = "l1dram",
843 .start = DA8XX_DSP_L1D_RAM_BASE,
844 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
845 .flags = IORESOURCE_MEM,
846 },
5c71d618 847 { /* dsp irq */
a98ca73e
BG		 848 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
849 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
5c71d618
RT		 850 .flags = IORESOURCE_IRQ,
851 },
852};
853
854static struct platform_device da8xx_dsp = {
855 .name = "davinci-rproc",
856 .dev = {
857 .coherent_dma_mask = DMA_BIT_MASK(32),
858 },
859 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
860 .resource = da8xx_rproc_resources,
861};
862
f97f0357
SA		 863static bool rproc_mem_inited __initdata;
864
5c71d618
RT		 865#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
866
867static phys_addr_t rproc_base __initdata;
868static unsigned long rproc_size __initdata;
869
870static int __init early_rproc_mem(char *p)
871{
872 char *endp;
873
874 if (p == NULL)
875 return 0;
876
877 rproc_size = memparse(p, &endp);
878 if (*endp == '@')
879 rproc_base = memparse(endp + 1, NULL);
880
881 return 0;
882}
883early_param("rproc_mem", early_rproc_mem);
884
885void __init da8xx_rproc_reserve_cma(void)
886{
8df40512 887 struct cma *cma;
5c71d618
RT		 888 int ret;
889
890 if (!rproc_base || !rproc_size) {
891 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
892 " 'nn' and 'address' must both be non-zero\n",
893 __func__);
894
895 return;
896 }
897
898 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
899 __func__, rproc_size, (unsigned long)rproc_base);
900
8df40512
CH		 901 ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
902 true);
903 if (ret) {
904 pr_err("%s: dma_contiguous_reserve_area failed %d\n",
905 __func__, ret);
906 return;
907 }
5af63893 908 da8xx_dsp.dev.cma_area = cma;
8df40512 909 rproc_mem_inited = true;
5c71d618 910}
5c71d618
RT		 911#else
912
913void __init da8xx_rproc_reserve_cma(void)
914{
915}
916
917#endif
918
919int __init da8xx_register_rproc(void)
920{
921 int ret;
922
f97f0357
SA		 923 if (!rproc_mem_inited) {
924 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
925 __func__);
926 return -ENOMEM;
927 }
928
5c71d618
RT		 929 ret = platform_device_register(&da8xx_dsp);
930 if (ret)
931 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
932
933 return ret;
934};
935
c51df70b
MG		 936static struct resource da8xx_rtc_resources[] = {
937 {
938 .start = DA8XX_RTC_BASE,
939 .end = DA8XX_RTC_BASE + SZ_4K - 1,
940 .flags = IORESOURCE_MEM,
941 },
942 { /* timer irq */
a98ca73e
BG		 943 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
944 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
c51df70b
MG		 945 .flags = IORESOURCE_IRQ,
946 },
947 { /* alarm irq */
a98ca73e
BG		 948 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
949 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
c51df70b
MG		 950 .flags = IORESOURCE_IRQ,
951 },
952};
953
954static struct platform_device da8xx_rtc_device = {
852168c9 955 .name = "da830-rtc",
c51df70b
MG		 956 .id = -1,
957 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
958 .resource = da8xx_rtc_resources,
959};
960
961int da8xx_register_rtc(void)
962{
79eb1636 963 return platform_device_register(&da8xx_rtc_device);
c51df70b 964}
1960e693 965
948c66df
SN		 966static void __iomem *da8xx_ddr2_ctlr_base;
967void __iomem * __init da8xx_get_mem_ctlr(void)
968{
969 if (da8xx_ddr2_ctlr_base)
970 return da8xx_ddr2_ctlr_base;
971
972 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
973 if (!da8xx_ddr2_ctlr_base)
d2e0c18a 974 pr_warn("%s: Unable to map DDR2 controller", __func__);
948c66df
SN		 975
976 return da8xx_ddr2_ctlr_base;
977}
978
1960e693
SN		 979static struct resource da8xx_cpuidle_resources[] = {
980 {
981 .start = DA8XX_DDR2_CTL_BASE,
982 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
983 .flags = IORESOURCE_MEM,
984 },
985};
986
987/* DA8XX devices support DDR2 power down */
988static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
989 .ddr2_pdown = 1,
990};
991
992
993static struct platform_device da8xx_cpuidle_device = {
994 .name = "cpuidle-davinci",
995 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
996 .resource = da8xx_cpuidle_resources,
997 .dev = {
998 .platform_data = &da8xx_cpuidle_pdata,
999 },
1000};
1001
1002int __init da8xx_register_cpuidle(void)
1003{
948c66df
SN		 1004 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
1005
1960e693
SN		 1006 return platform_device_register(&da8xx_cpuidle_device);
1007}
54ce6883
MW		 1008
1009static struct resource da8xx_spi0_resources[] = {
1010 [0] = {
1011 .start = DA8XX_SPI0_BASE,
1012 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
1013 .flags = IORESOURCE_MEM,
1014 },
1015 [1] = {
a98ca73e
BG		 1016 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1017 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
54ce6883
MW		 1018 .flags = IORESOURCE_IRQ,
1019 },
54ce6883
MW		 1020};
1021
1022static struct resource da8xx_spi1_resources[] = {
1023 [0] = {
9e7d24f6
SS		 1024 .start = DA830_SPI1_BASE,
1025 .end = DA830_SPI1_BASE + SZ_4K - 1,
54ce6883
MW		 1026 .flags = IORESOURCE_MEM,
1027 },
1028 [1] = {
a98ca73e
BG		 1029 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1030 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
54ce6883
MW		 1031 .flags = IORESOURCE_IRQ,
1032 },
54ce6883
MW		 1033};
1034
0273612c 1035static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
54ce6883
MW		 1036 [0] = {
1037 .version = SPI_VERSION_2,
1038 .intr_line = 1,
1039 .dma_event_q = EVENTQ_0,
1b0838b5 1040 .prescaler_limit = 2,
54ce6883
MW		 1041 },
1042 [1] = {
1043 .version = SPI_VERSION_2,
1044 .intr_line = 1,
1045 .dma_event_q = EVENTQ_0,
1b0838b5 1046 .prescaler_limit = 2,
54ce6883
MW		 1047 },
1048};
1049
1050static struct platform_device da8xx_spi_device[] = {
1051 [0] = {
1052 .name = "spi_davinci",
1053 .id = 0,
1054 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1055 .resource = da8xx_spi0_resources,
1056 .dev = {
1057 .platform_data = &da8xx_spi_pdata[0],
1058 },
1059 },
1060 [1] = {
1061 .name = "spi_davinci",
1062 .id = 1,
1063 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1064 .resource = da8xx_spi1_resources,
1065 .dev = {
1066 .platform_data = &da8xx_spi_pdata[1],
1067 },
1068 },
1069};
1070
0273612c 1071int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
54ce6883 1072{
54ce6883
MW		 1073 if (instance < 0 || instance > 1)
1074 return -EINVAL;
1075
0273612c 1076 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
54ce6883 1077
9e7d24f6
SS		 1078 if (instance == 1 && cpu_is_davinci_da850()) {
1079 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1080 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1081 }
1082
54ce6883
MW		 1083 return platform_device_register(&da8xx_spi_device[instance]);
1084}
cbb2c961
SN		 1085
1086#ifdef CONFIG_ARCH_DAVINCI_DA850
aa1da33c
DL		 1087int __init da850_register_sata_refclk(int rate)
1088{
1089 struct clk *clk;
1090
1091 clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
1092 if (IS_ERR(clk))
1093 return PTR_ERR(clk);
1094
1095 return clk_register_clkdev(clk, "refclk", "ahci_da850");
1096}
00bacfbf 1097
cbb2c961
SN		 1098static struct resource da850_sata_resources[] = {
1099 {
1100 .start = DA850_SATA_BASE,
1101 .end = DA850_SATA_BASE + 0x1fff,
1102 .flags = IORESOURCE_MEM,
1103 },
080c492d
BZ		 1104 {
1105 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1106 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1107 .flags = IORESOURCE_MEM,
1108 },
cbb2c961 1109 {
a98ca73e 1110 .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
cbb2c961
SN		 1111 .flags = IORESOURCE_IRQ,
1112 },
1113};
1114
cbb2c961
SN		 1115static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1116
1117static struct platform_device da850_sata_device = {
080c492d 1118 .name = "ahci_da850",
cbb2c961
SN		 1119 .id = -1,
1120 .dev = {
cbb2c961
SN		 1121 .dma_mask = &da850_sata_dmamask,
1122 .coherent_dma_mask = DMA_BIT_MASK(32),
1123 },
1124 .num_resources = ARRAY_SIZE(da850_sata_resources),
1125 .resource = da850_sata_resources,
1126};
1127
1128int __init da850_register_sata(unsigned long refclkpn)
1129{
00bacfbf
BG		 1130 int ret;
1131
00bacfbf
BG		 1132 ret = da850_register_sata_refclk(refclkpn);
1133 if (ret)
1134 return ret;
1135
cbb2c961
SN		 1136 return platform_device_register(&da850_sata_device);
1137}
1138#endif
0fcd5411 1139
bdec5a6b 1140static struct regmap *da8xx_cfgchip;
0fcd5411 1141
bdec5a6b 1142static const struct regmap_config da8xx_cfgchip_config __initconst = {
f6adc9fd 1143 .name = "cfgchip",
bdec5a6b
DL		 1144 .reg_bits = 32,
1145 .val_bits = 32,
1146 .reg_stride = 4,
1147 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
0fcd5411
DL		 1148};
1149
bdec5a6b
DL		 1150/**
1151 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1152 *
1153 * This is for use on non-DT boards only. For DT boards, use
1154 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1155 *
1156 * Returns: Pointer to the CFGCHIP regmap or negative error code.
1157 */
1158struct regmap * __init da8xx_get_cfgchip(void)
0fcd5411 1159{
bdec5a6b
DL		 1160 if (IS_ERR_OR_NULL(da8xx_cfgchip))
1161 da8xx_cfgchip = regmap_init_mmio(NULL,
1162 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
1163 &da8xx_cfgchip_config);
1164
1165 return da8xx_cfgchip;
0fcd5411 1166}
Linux 6.x block layer and io_uring tree(s)