[linux-2.6-block.git] / arch / arm / mach-davinci / davinci.h

/*
 * This file contains the processor specific definitions
 * of the TI DM644x, DM355, DM365, and DM646x.
 *
 * Copyright (C) 2011 Texas Instruments Incorporated
 * Copyright (c) 2007 Deep Root Systems, LLC
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#ifndef __DAVINCI_H
#define __DAVINCI_H

#include <linux/clk.h>
#include <linux/videodev2.h>
#include <linux/davinci_emac.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/platform_data/davinci_asp.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/keyscan-davinci.h>
#include <mach/hardware.h>

#include <media/davinci/vpfe_capture.h>
#include <media/davinci/vpif_types.h>
#include <media/davinci/vpss.h>
#include <media/davinci/vpbe_types.h>
#include <media/davinci/vpbe_venc.h>
#include <media/davinci/vpbe.h>
#include <media/davinci/vpbe_osd.h>

#define DAVINCI_PLL1_BASE		0x01c40800
#define DAVINCI_PLL2_BASE		0x01c40c00
#define DAVINCI_PWR_SLEEP_CNTRL_BASE	0x01c41000

#define DAVINCI_SYSTEM_MODULE_BASE	0x01c40000
#define SYSMOD_VDAC_CONFIG		0x2c
#define SYSMOD_VIDCLKCTL		0x38
#define SYSMOD_VPSS_CLKCTL		0x44
#define SYSMOD_VDD3P3VPWDN		0x48
#define SYSMOD_VSCLKDIS			0x6c
#define SYSMOD_PUPDCTL1			0x7c

/* VPSS CLKCTL bit definitions */
#define VPSS_MUXSEL_EXTCLK_ENABLE	BIT(1)
#define VPSS_VENCCLKEN_ENABLE		BIT(3)
#define VPSS_DACCLKEN_ENABLE		BIT(4)
#define VPSS_PLLC2SYSCLK5_ENABLE	BIT(5)

extern void __iomem *davinci_sysmod_base;
#define DAVINCI_SYSMOD_VIRT(x)	(davinci_sysmod_base + (x))
void davinci_map_sysmod(void);

#define DAVINCI_GPIO_BASE 0x01C67000
int davinci_gpio_register(struct resource *res, int size, void *pdata);

#define DAVINCI_TIMER0_BASE		(IO_PHYS + 0x21400)
#define DAVINCI_WDOG_BASE		(IO_PHYS + 0x21C00)

/* DM355 base addresses */
#define DM355_ASYNC_EMIF_CONTROL_BASE	0x01e10000
#define DM355_ASYNC_EMIF_DATA_CE0_BASE	0x02000000

#define ASP1_TX_EVT_EN	1
#define ASP1_RX_EVT_EN	2

/* DM365 base addresses */
#define DM365_ASYNC_EMIF_CONTROL_BASE	0x01d10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE	0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE	0x04000000

/* DM644x base addresses */
#define DM644X_ASYNC_EMIF_CONTROL_BASE	0x01e00000
#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000

/* DM646x base addresses */
#define DM646X_ASYNC_EMIF_CONTROL_BASE	0x20008000
#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000

int davinci_init_wdt(void);

/* DM355 function declarations */
void dm355_init(void);
void dm355_init_time(void);
void dm355_init_irq(void);
void dm355_register_clocks(void);
void dm355_init_spi0(unsigned chipselect_mask,
		const struct spi_board_info *info, unsigned len);
void dm355_init_asp1(u32 evt_enable);
int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
int dm355_gpio_register(void);

/* DM365 function declarations */
void dm365_init(void);
void dm365_init_irq(void);
void dm365_init_time(void);
void dm365_register_clocks(void);
void dm365_init_asp(void);
void dm365_init_vc(void);
void dm365_init_ks(struct davinci_ks_platform_data *pdata);
void dm365_init_rtc(void);
void dm365_init_spi0(unsigned chipselect_mask,
			const struct spi_board_info *info, unsigned len);
int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
int dm365_gpio_register(void);

/* DM644x function declarations */
void dm644x_init(void);
void dm644x_init_irq(void);
void dm644x_init_devices(void);
void dm644x_init_time(void);
void dm644x_register_clocks(void);
void dm644x_init_asp(void);
int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
int dm644x_gpio_register(void);

/* DM646x function declarations */
void dm646x_init(void);
void dm646x_init_irq(void);
void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
void dm646x_register_clocks(void);
void dm646x_init_mcasp0(struct snd_platform_data *pdata);
void dm646x_init_mcasp1(struct snd_platform_data *pdata);
int dm646x_init_edma(struct edma_rsv_info *rsv);
void dm646x_video_init(void);
void dm646x_setup_vpif(struct vpif_display_config *,
		       struct vpif_capture_config *);
int dm646x_gpio_register(void);

extern struct platform_device dm365_serial_device[];
extern struct platform_device dm355_serial_device[];
extern struct platform_device dm644x_serial_device[];
extern struct platform_device dm646x_serial_device[];
#endif /*__DAVINCI_H */
Commit	Line	Data
39c6d2d1 MH	1	/*
	2	* This file contains the processor specific definitions
	3	* of the TI DM644x, DM355, DM365, and DM646x.
	4	*
	5	* Copyright (C) 2011 Texas Instruments Incorporated
	6	* Copyright (c) 2007 Deep Root Systems, LLC
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation version 2.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17	#ifndef __DAVINCI_H
	18	#define __DAVINCI_H
	19
	20	#include <linux/clk.h>
	21	#include <linux/videodev2.h>
	22	#include <linux/davinci_emac.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/spi/spi.h>
896f66b7	25	#include <linux/platform_data/davinci_asp.h>
3ad7a42d	26	#include <linux/platform_data/edma.h>
ec2a0833	27	#include <linux/platform_data/keyscan-davinci.h>
5cfb19ac	28	#include <mach/hardware.h>
39c6d2d1 MH	29
	30	#include <media/davinci/vpfe_capture.h>
	31	#include <media/davinci/vpif_types.h>
af946f26 MH	32	#include <media/davinci/vpss.h>
	33	#include <media/davinci/vpbe_types.h>
	34	#include <media/davinci/vpbe_venc.h>
	35	#include <media/davinci/vpbe.h>
	36	#include <media/davinci/vpbe_osd.h>
39c6d2d1	37
27823278 DL	38	#define DAVINCI_PLL1_BASE 0x01c40800
	39	#define DAVINCI_PLL2_BASE 0x01c40c00
	40	#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
	41
5cfb19ac	42	#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
120c6604	43	#define SYSMOD_VDAC_CONFIG 0x2c
5cfb19ac	44	#define SYSMOD_VIDCLKCTL 0x38
af946f26	45	#define SYSMOD_VPSS_CLKCTL 0x44
5cfb19ac MH	46	#define SYSMOD_VDD3P3VPWDN 0x48
	47	#define SYSMOD_VSCLKDIS 0x6c
	48	#define SYSMOD_PUPDCTL1 0x7c
	49
120c6604	50	/* VPSS CLKCTL bit definitions */
62a2d6cd	51	#define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1)
120c6604 LP	52	#define VPSS_VENCCLKEN_ENABLE BIT(3)
	53	#define VPSS_DACCLKEN_ENABLE BIT(4)
	54	#define VPSS_PLLC2SYSCLK5_ENABLE BIT(5)
	55
5cfb19ac MH	56	extern void __iomem *davinci_sysmod_base;
	57	#define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x))
	58	void davinci_map_sysmod(void);
	59
9cc1515c PA	60	#define DAVINCI_GPIO_BASE 0x01C67000
	61	int davinci_gpio_register(struct resource res, int size, void pdata);
	62
66ae81dc BG	63	#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
	64	#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
	65
39c6d2d1 MH	66	/* DM355 base addresses */
	67	#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
	68	#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
	69
	70	#define ASP1_TX_EVT_EN 1
	71	#define ASP1_RX_EVT_EN 2
	72
	73	/* DM365 base addresses */
	74	#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
	75	#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
	76	#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
	77
	78	/* DM644x base addresses */
	79	#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000
	80	#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
	81	#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
	82	#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
	83	#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
	84
	85	/* DM646x base addresses */
	86	#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
	87	#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
	88
1233090c SN	89	int davinci_init_wdt(void);
1233090c SN	90
39c6d2d1	91	/* DM355 function declarations */
b464e3cb	92	void dm355_init(void);
96c08173	93	void dm355_init_time(void);
de4f82a2	94	void dm355_init_irq(void);
5b19f66d	95	void dm355_register_clocks(void);
39c6d2d1	96	void dm355_init_spi0(unsigned chipselect_mask,
d65566e5	97	const struct spi_board_info *info, unsigned len);
6bce5efd	98	void dm355_init_asp1(u32 evt_enable);
62a2d6cd	99	int dm355_init_video(struct vpfe_config , struct vpbe_config );
9cc1515c	100	int dm355_gpio_register(void);
39c6d2d1 MH	101
39c6d2d1 MH	102	/* DM365 function declarations */
b464e3cb	103	void dm365_init(void);
de4f82a2	104	void dm365_init_irq(void);
96c08173	105	void dm365_init_time(void);
21c2f477	106	void dm365_register_clocks(void);
6bce5efd	107	void dm365_init_asp(void);
933b11ae	108	void dm365_init_vc(void);
b464e3cb LP	109	void dm365_init_ks(struct davinci_ks_platform_data *pdata);
b464e3cb LP	110	void dm365_init_rtc(void);
39c6d2d1	111	void dm365_init_spi0(unsigned chipselect_mask,
d65566e5	112	const struct spi_board_info *info, unsigned len);
120c6604	113	int dm365_init_video(struct vpfe_config , struct vpbe_config );
9cc1515c	114	int dm365_gpio_register(void);
39c6d2d1 MH	115
39c6d2d1 MH	116	/* DM644x function declarations */
b464e3cb	117	void dm644x_init(void);
de4f82a2	118	void dm644x_init_irq(void);
8e730c7f	119	void dm644x_init_devices(void);
96c08173	120	void dm644x_init_time(void);
a5b1a871	121	void dm644x_register_clocks(void);
6bce5efd	122	void dm644x_init_asp(void);
b464e3cb	123	int dm644x_init_video(struct vpfe_config , struct vpbe_config );
9cc1515c	124	int dm644x_gpio_register(void);
39c6d2d1 MH	125
39c6d2d1 MH	126	/* DM646x function declarations */
b464e3cb	127	void dm646x_init(void);
de4f82a2	128	void dm646x_init_irq(void);
96c08173	129	void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
81df7d85	130	void dm646x_register_clocks(void);
b464e3cb LP	131	void dm646x_init_mcasp0(struct snd_platform_data *pdata);
	132	void dm646x_init_mcasp1(struct snd_platform_data *pdata);
	133	int dm646x_init_edma(struct edma_rsv_info *rsv);
39c6d2d1 MH	134	void dm646x_video_init(void);
	135	void dm646x_setup_vpif(struct vpif_display_config *,
	136	struct vpif_capture_config *);
9cc1515c	137	int dm646x_gpio_register(void);
fcf7157b MP	138
	139	extern struct platform_device dm365_serial_device[];
	140	extern struct platform_device dm355_serial_device[];
	141	extern struct platform_device dm644x_serial_device[];
	142	extern struct platform_device dm646x_serial_device[];
39c6d2d1	143	#endif /__DAVINCI_H /