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ARM: iop13xx: fix iq81340sc_atux_map_irq prototype
[linux-2.6-block.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
2f8163ba 14#include <linux/gpio.h>
e1a8d7e2
SR		 15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/platform_device.h>
683b1e1f 18#include <linux/cpufreq.h>
35f9acd8 19#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 20
21#include <asm/mach/map.h>
22
e1a8d7e2 23#include <mach/psc.h>
e1a8d7e2
SR		 24#include <mach/irqs.h>
25#include <mach/cputype.h>
26#include <mach/common.h>
27#include <mach/time.h>
28#include <mach/da8xx.h>
683b1e1f 29#include <mach/cpufreq.h>
044ca015 30#include <mach/pm.h>
5f3fcf96 31#include <mach/gpio-davinci.h>
e1a8d7e2
SR		 32
33#include "clock.h"
34#include "mux.h"
35
5d36a332
SN		 36/* SoC specific clock flags */
37#define DA850_CLK_ASYNC3 BIT(16)
38
e1a8d7e2
SR		 39#define DA850_PLL1_BASE 0x01e1a000
40#define DA850_TIMER64P2_BASE 0x01f0c000
41#define DA850_TIMER64P3_BASE 0x01f0d000
42
43#define DA850_REF_FREQ 24000000
44
5d36a332 45#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
7aad472b 46#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
683b1e1f
SN		 47#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
48
49static int da850_set_armrate(struct clk *clk, unsigned long rate);
50static int da850_round_armrate(struct clk *clk, unsigned long rate);
51static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 52
e1a8d7e2
SR		 53static struct pll_data pll0_data = {
54 .num = 1,
55 .phys_base = DA8XX_PLL0_BASE,
56 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
57};
58
59static struct clk ref_clk = {
60 .name = "ref_clk",
61 .rate = DA850_REF_FREQ,
8d54297b 62 .set_rate = davinci_simple_set_rate,
e1a8d7e2
SR		 63};
64
65static struct clk pll0_clk = {
66 .name = "pll0",
67 .parent = &ref_clk,
68 .pll_data = &pll0_data,
69 .flags = CLK_PLL,
683b1e1f 70 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 71};
72
73static struct clk pll0_aux_clk = {
74 .name = "pll0_aux_clk",
75 .parent = &pll0_clk,
76 .flags = CLK_PLL | PRE_PLL,
77};
78
79static struct clk pll0_sysclk2 = {
80 .name = "pll0_sysclk2",
81 .parent = &pll0_clk,
82 .flags = CLK_PLL,
83 .div_reg = PLLDIV2,
84};
85
86static struct clk pll0_sysclk3 = {
87 .name = "pll0_sysclk3",
88 .parent = &pll0_clk,
89 .flags = CLK_PLL,
90 .div_reg = PLLDIV3,
b987c4b2
SN		 91 .set_rate = davinci_set_sysclk_rate,
92 .maxrate = 100000000,
e1a8d7e2
SR		 93};
94
95static struct clk pll0_sysclk4 = {
96 .name = "pll0_sysclk4",
97 .parent = &pll0_clk,
98 .flags = CLK_PLL,
99 .div_reg = PLLDIV4,
100};
101
102static struct clk pll0_sysclk5 = {
103 .name = "pll0_sysclk5",
104 .parent = &pll0_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV5,
107};
108
109static struct clk pll0_sysclk6 = {
110 .name = "pll0_sysclk6",
111 .parent = &pll0_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV6,
114};
115
116static struct clk pll0_sysclk7 = {
117 .name = "pll0_sysclk7",
118 .parent = &pll0_clk,
119 .flags = CLK_PLL,
120 .div_reg = PLLDIV7,
121};
122
123static struct pll_data pll1_data = {
124 .num = 2,
125 .phys_base = DA850_PLL1_BASE,
126 .flags = PLL_HAS_POSTDIV,
127};
128
129static struct clk pll1_clk = {
130 .name = "pll1",
131 .parent = &ref_clk,
132 .pll_data = &pll1_data,
133 .flags = CLK_PLL,
134};
135
136static struct clk pll1_aux_clk = {
137 .name = "pll1_aux_clk",
138 .parent = &pll1_clk,
139 .flags = CLK_PLL | PRE_PLL,
140};
141
142static struct clk pll1_sysclk2 = {
143 .name = "pll1_sysclk2",
144 .parent = &pll1_clk,
145 .flags = CLK_PLL,
146 .div_reg = PLLDIV2,
147};
148
149static struct clk pll1_sysclk3 = {
150 .name = "pll1_sysclk3",
151 .parent = &pll1_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV3,
154};
155
e1a8d7e2
SR		 156static struct clk i2c0_clk = {
157 .name = "i2c0",
158 .parent = &pll0_aux_clk,
159};
160
161static struct clk timerp64_0_clk = {
162 .name = "timer0",
163 .parent = &pll0_aux_clk,
164};
165
166static struct clk timerp64_1_clk = {
167 .name = "timer1",
168 .parent = &pll0_aux_clk,
169};
170
171static struct clk arm_rom_clk = {
172 .name = "arm_rom",
173 .parent = &pll0_sysclk2,
174 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
175 .flags = ALWAYS_ENABLED,
176};
177
178static struct clk tpcc0_clk = {
179 .name = "tpcc0",
180 .parent = &pll0_sysclk2,
181 .lpsc = DA8XX_LPSC0_TPCC,
182 .flags = ALWAYS_ENABLED | CLK_PSC,
183};
184
185static struct clk tptc0_clk = {
186 .name = "tptc0",
187 .parent = &pll0_sysclk2,
188 .lpsc = DA8XX_LPSC0_TPTC0,
189 .flags = ALWAYS_ENABLED,
190};
191
192static struct clk tptc1_clk = {
193 .name = "tptc1",
194 .parent = &pll0_sysclk2,
195 .lpsc = DA8XX_LPSC0_TPTC1,
196 .flags = ALWAYS_ENABLED,
197};
198
199static struct clk tpcc1_clk = {
200 .name = "tpcc1",
201 .parent = &pll0_sysclk2,
202 .lpsc = DA850_LPSC1_TPCC1,
789a785e 203 .gpsc = 1,
e1a8d7e2 204 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 205};
206
207static struct clk tptc2_clk = {
208 .name = "tptc2",
209 .parent = &pll0_sysclk2,
210 .lpsc = DA850_LPSC1_TPTC2,
789a785e 211 .gpsc = 1,
e1a8d7e2 212 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 213};
214
215static struct clk uart0_clk = {
216 .name = "uart0",
217 .parent = &pll0_sysclk2,
218 .lpsc = DA8XX_LPSC0_UART0,
219};
220
221static struct clk uart1_clk = {
222 .name = "uart1",
223 .parent = &pll0_sysclk2,
224 .lpsc = DA8XX_LPSC1_UART1,
789a785e 225 .gpsc = 1,
5d36a332 226 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 227};
228
229static struct clk uart2_clk = {
230 .name = "uart2",
231 .parent = &pll0_sysclk2,
232 .lpsc = DA8XX_LPSC1_UART2,
789a785e 233 .gpsc = 1,
5d36a332 234 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 235};
236
237static struct clk aintc_clk = {
238 .name = "aintc",
239 .parent = &pll0_sysclk4,
240 .lpsc = DA8XX_LPSC0_AINTC,
241 .flags = ALWAYS_ENABLED,
242};
243
244static struct clk gpio_clk = {
245 .name = "gpio",
246 .parent = &pll0_sysclk4,
247 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 248 .gpsc = 1,
e1a8d7e2
SR		 249};
250
251static struct clk i2c1_clk = {
252 .name = "i2c1",
253 .parent = &pll0_sysclk4,
254 .lpsc = DA8XX_LPSC1_I2C,
789a785e 255 .gpsc = 1,
e1a8d7e2
SR		 256};
257
258static struct clk emif3_clk = {
259 .name = "emif3",
260 .parent = &pll0_sysclk5,
261 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 262 .gpsc = 1,
e1a8d7e2 263 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 264};
265
266static struct clk arm_clk = {
267 .name = "arm",
268 .parent = &pll0_sysclk6,
269 .lpsc = DA8XX_LPSC0_ARM,
270 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 271 .set_rate = da850_set_armrate,
272 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 273};
274
275static struct clk rmii_clk = {
276 .name = "rmii",
277 .parent = &pll0_sysclk7,
278};
279
5a4b1315
SR		 280static struct clk emac_clk = {
281 .name = "emac",
282 .parent = &pll0_sysclk4,
283 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 284 .gpsc = 1,
5a4b1315
SR		 285};
286
491214e1
C		 287static struct clk mcasp_clk = {
288 .name = "mcasp",
289 .parent = &pll0_sysclk2,
290 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 291 .gpsc = 1,
51157ed8 292 .flags = DA850_CLK_ASYNC3,
491214e1
C		 293};
294
5cbdf276
SR		 295static struct clk lcdc_clk = {
296 .name = "lcdc",
297 .parent = &pll0_sysclk2,
298 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 299 .gpsc = 1,
5cbdf276
SR		 300};
301
051a6687
JK		 302static struct clk mmcsd0_clk = {
303 .name = "mmcsd0",
700691f2
SR		 304 .parent = &pll0_sysclk2,
305 .lpsc = DA8XX_LPSC0_MMC_SD,
306};
307
051a6687
JK		 308static struct clk mmcsd1_clk = {
309 .name = "mmcsd1",
310 .parent = &pll0_sysclk2,
311 .lpsc = DA850_LPSC1_MMC_SD1,
312 .gpsc = 1,
313};
314
38beb929
SR		 315static struct clk aemif_clk = {
316 .name = "aemif",
317 .parent = &pll0_sysclk3,
318 .lpsc = DA8XX_LPSC0_EMIF25,
319 .flags = ALWAYS_ENABLED,
320};
321
5efe330a
VR		 322static struct clk usb11_clk = {
323 .name = "usb11",
324 .parent = &pll0_sysclk4,
325 .lpsc = DA8XX_LPSC1_USB11,
326 .gpsc = 1,
327};
328
329static struct clk usb20_clk = {
330 .name = "usb20",
331 .parent = &pll0_sysclk2,
332 .lpsc = DA8XX_LPSC1_USB20,
333 .gpsc = 1,
334};
335
12d35cf3
MW		 336static struct clk spi0_clk = {
337 .name = "spi0",
338 .parent = &pll0_sysclk2,
339 .lpsc = DA8XX_LPSC0_SPI0,
340};
341
342static struct clk spi1_clk = {
343 .name = "spi1",
344 .parent = &pll0_sysclk2,
345 .lpsc = DA8XX_LPSC1_SPI1,
346 .gpsc = 1,
347 .flags = DA850_CLK_ASYNC3,
348};
349
cbb2c961
SN		 350static struct clk sata_clk = {
351 .name = "sata",
352 .parent = &pll0_sysclk2,
353 .lpsc = DA850_LPSC1_SATA,
354 .gpsc = 1,
355 .flags = PSC_FORCE,
356};
357
08aca087 358static struct clk_lookup da850_clks[] = {
e1a8d7e2
SR		 359 CLK(NULL, "ref", &ref_clk),
360 CLK(NULL, "pll0", &pll0_clk),
361 CLK(NULL, "pll0_aux", &pll0_aux_clk),
362 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
363 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
364 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
365 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
366 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
367 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
368 CLK(NULL, "pll1", &pll1_clk),
369 CLK(NULL, "pll1_aux", &pll1_aux_clk),
370 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
371 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
e1a8d7e2
SR		 372 CLK("i2c_davinci.1", NULL, &i2c0_clk),
373 CLK(NULL, "timer0", &timerp64_0_clk),
374 CLK("watchdog", NULL, &timerp64_1_clk),
375 CLK(NULL, "arm_rom", &arm_rom_clk),
376 CLK(NULL, "tpcc0", &tpcc0_clk),
377 CLK(NULL, "tptc0", &tptc0_clk),
378 CLK(NULL, "tptc1", &tptc1_clk),
379 CLK(NULL, "tpcc1", &tpcc1_clk),
380 CLK(NULL, "tptc2", &tptc2_clk),
381 CLK(NULL, "uart0", &uart0_clk),
382 CLK(NULL, "uart1", &uart1_clk),
383 CLK(NULL, "uart2", &uart2_clk),
384 CLK(NULL, "aintc", &aintc_clk),
385 CLK(NULL, "gpio", &gpio_clk),
386 CLK("i2c_davinci.2", NULL, &i2c1_clk),
387 CLK(NULL, "emif3", &emif3_clk),
388 CLK(NULL, "arm", &arm_clk),
389 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 390 CLK("davinci_emac.1", NULL, &emac_clk),
491214e1 391 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
5cbdf276 392 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
051a6687
JK		 393 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
394 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
38beb929 395 CLK(NULL, "aemif", &aemif_clk),
5efe330a
VR		 396 CLK(NULL, "usb11", &usb11_clk),
397 CLK(NULL, "usb20", &usb20_clk),
12d35cf3
MW		 398 CLK("spi_davinci.0", NULL, &spi0_clk),
399 CLK("spi_davinci.1", NULL, &spi1_clk),
cbb2c961 400 CLK("ahci", NULL, &sata_clk),
e1a8d7e2
SR		 401 CLK(NULL, NULL, NULL),
402};
403
404/*
405 * Device specific mux setup
406 *
407 * soc description mux mode mode mux dbg
408 * reg offset mask mode
409 */
410static const struct mux_config da850_pins[] = {
411#ifdef CONFIG_DAVINCI_MUX
412 /* UART0 function */
413 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
414 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
415 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
416 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
417 /* UART1 function */
418 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
419 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
420 /* UART2 function */
421 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
422 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
423 /* I2C1 function */
424 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
425 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
426 /* I2C0 function */
427 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
428 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 429 /* EMAC function */
430 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
431 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
432 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
433 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
434 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
435 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
436 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
437 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
438 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
439 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
440 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
441 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
442 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
443 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
444 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 445 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
446 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 447 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
448 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
449 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
450 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
451 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
452 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
453 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
454 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 455 /* McASP function */
456 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
457 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
458 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
459 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
460 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
461 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
462 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
463 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
464 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
465 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
466 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
467 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
468 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
469 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
470 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
471 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
472 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
473 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
474 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
475 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
476 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
477 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
478 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 479 /* LCD function */
480 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
481 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
482 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
483 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
484 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
485 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
486 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
487 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
488 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
489 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
490 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
491 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
492 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
493 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
494 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
495 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
496 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
497 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
498 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
499 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 500 /* MMC/SD0 function */
501 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
502 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
503 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
504 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
505 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
506 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
5c4d11b4
IY		 507 /* MMC/SD1 function */
508 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
509 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
510 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
511 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
512 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
513 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
38beb929
SR		 514 /* EMIF2.5/EMIFA function */
515 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
516 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
517 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
518 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
519 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
520 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
521 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
522 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
523 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
524 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
525 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
526 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
527 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
528 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 529 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
530 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
531 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
532 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
533 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
534 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
535 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
536 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
537 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
538 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
539 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
540 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
541 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
542 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
543 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
544 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
545 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
546 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
547 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
548 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
549 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
550 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
551 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
552 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
553 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
554 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
555 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
556 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
557 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
558 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
559 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
560 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
561 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
562 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 563 /* GPIO function */
fe358d6a 564 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
2206771c 565 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 566 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 567 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
fe358d6a
VR		 568 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
569 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
700691f2
SR		 570 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
571 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
6836989c
IY		 572 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
573 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
fe358d6a 574 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
044ca015 575 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
e1a8d7e2
SR		 576#endif
577};
578
e1a8d7e2
SR		 579const short da850_i2c0_pins[] __initdata = {
580 DA850_I2C0_SDA, DA850_I2C0_SCL,
581 -1
582};
583
584const short da850_i2c1_pins[] __initdata = {
585 DA850_I2C1_SCL, DA850_I2C1_SDA,
586 -1
587};
588
5cbdf276 589const short da850_lcdcntl_pins[] __initdata = {
7761ef67
SR		 590 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
591 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
592 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
593 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
594 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 595 -1
596};
597
e1a8d7e2
SR		 598/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
599static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
600 [IRQ_DA8XX_COMMTX] = 7,
601 [IRQ_DA8XX_COMMRX] = 7,
602 [IRQ_DA8XX_NINT] = 7,
603 [IRQ_DA8XX_EVTOUT0] = 7,
604 [IRQ_DA8XX_EVTOUT1] = 7,
605 [IRQ_DA8XX_EVTOUT2] = 7,
606 [IRQ_DA8XX_EVTOUT3] = 7,
607 [IRQ_DA8XX_EVTOUT4] = 7,
608 [IRQ_DA8XX_EVTOUT5] = 7,
609 [IRQ_DA8XX_EVTOUT6] = 7,
e1a8d7e2
SR		 610 [IRQ_DA8XX_EVTOUT7] = 7,
611 [IRQ_DA8XX_CCINT0] = 7,
612 [IRQ_DA8XX_CCERRINT] = 7,
613 [IRQ_DA8XX_TCERRINT0] = 7,
614 [IRQ_DA8XX_AEMIFINT] = 7,
615 [IRQ_DA8XX_I2CINT0] = 7,
616 [IRQ_DA8XX_MMCSDINT0] = 7,
617 [IRQ_DA8XX_MMCSDINT1] = 7,
618 [IRQ_DA8XX_ALLINT0] = 7,
619 [IRQ_DA8XX_RTC] = 7,
620 [IRQ_DA8XX_SPINT0] = 7,
621 [IRQ_DA8XX_TINT12_0] = 7,
622 [IRQ_DA8XX_TINT34_0] = 7,
623 [IRQ_DA8XX_TINT12_1] = 7,
624 [IRQ_DA8XX_TINT34_1] = 7,
625 [IRQ_DA8XX_UARTINT0] = 7,
626 [IRQ_DA8XX_KEYMGRINT] = 7,
e1a8d7e2 627 [IRQ_DA850_MPUADDRERR0] = 7,
e1a8d7e2
SR		 628 [IRQ_DA8XX_CHIPINT0] = 7,
629 [IRQ_DA8XX_CHIPINT1] = 7,
630 [IRQ_DA8XX_CHIPINT2] = 7,
631 [IRQ_DA8XX_CHIPINT3] = 7,
632 [IRQ_DA8XX_TCERRINT1] = 7,
633 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
634 [IRQ_DA8XX_C0_RX_PULSE] = 7,
635 [IRQ_DA8XX_C0_TX_PULSE] = 7,
636 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
637 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
638 [IRQ_DA8XX_C1_RX_PULSE] = 7,
639 [IRQ_DA8XX_C1_TX_PULSE] = 7,
640 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
641 [IRQ_DA8XX_MEMERR] = 7,
642 [IRQ_DA8XX_GPIO0] = 7,
643 [IRQ_DA8XX_GPIO1] = 7,
644 [IRQ_DA8XX_GPIO2] = 7,
645 [IRQ_DA8XX_GPIO3] = 7,
646 [IRQ_DA8XX_GPIO4] = 7,
647 [IRQ_DA8XX_GPIO5] = 7,
648 [IRQ_DA8XX_GPIO6] = 7,
649 [IRQ_DA8XX_GPIO7] = 7,
650 [IRQ_DA8XX_GPIO8] = 7,
651 [IRQ_DA8XX_I2CINT1] = 7,
652 [IRQ_DA8XX_LCDINT] = 7,
653 [IRQ_DA8XX_UARTINT1] = 7,
654 [IRQ_DA8XX_MCASPINT] = 7,
655 [IRQ_DA8XX_ALLINT1] = 7,
656 [IRQ_DA8XX_SPINT1] = 7,
657 [IRQ_DA8XX_UHPI_INT1] = 7,
658 [IRQ_DA8XX_USB_INT] = 7,
659 [IRQ_DA8XX_IRQN] = 7,
660 [IRQ_DA8XX_RWAKEUP] = 7,
661 [IRQ_DA8XX_UARTINT2] = 7,
662 [IRQ_DA8XX_DFTSSINT] = 7,
663 [IRQ_DA8XX_EHRPWM0] = 7,
664 [IRQ_DA8XX_EHRPWM0TZ] = 7,
665 [IRQ_DA8XX_EHRPWM1] = 7,
666 [IRQ_DA8XX_EHRPWM1TZ] = 7,
667 [IRQ_DA850_SATAINT] = 7,
e1a8d7e2
SR		 668 [IRQ_DA850_TINTALL_2] = 7,
669 [IRQ_DA8XX_ECAP0] = 7,
670 [IRQ_DA8XX_ECAP1] = 7,
671 [IRQ_DA8XX_ECAP2] = 7,
672 [IRQ_DA850_MMCSDINT0_1] = 7,
673 [IRQ_DA850_MMCSDINT1_1] = 7,
674 [IRQ_DA850_T12CMPINT0_2] = 7,
675 [IRQ_DA850_T12CMPINT1_2] = 7,
676 [IRQ_DA850_T12CMPINT2_2] = 7,
677 [IRQ_DA850_T12CMPINT3_2] = 7,
678 [IRQ_DA850_T12CMPINT4_2] = 7,
679 [IRQ_DA850_T12CMPINT5_2] = 7,
680 [IRQ_DA850_T12CMPINT6_2] = 7,
681 [IRQ_DA850_T12CMPINT7_2] = 7,
682 [IRQ_DA850_T12CMPINT0_3] = 7,
683 [IRQ_DA850_T12CMPINT1_3] = 7,
684 [IRQ_DA850_T12CMPINT2_3] = 7,
685 [IRQ_DA850_T12CMPINT3_3] = 7,
686 [IRQ_DA850_T12CMPINT4_3] = 7,
687 [IRQ_DA850_T12CMPINT5_3] = 7,
688 [IRQ_DA850_T12CMPINT6_3] = 7,
689 [IRQ_DA850_T12CMPINT7_3] = 7,
690 [IRQ_DA850_RPIINT] = 7,
691 [IRQ_DA850_VPIFINT] = 7,
692 [IRQ_DA850_CCINT1] = 7,
693 [IRQ_DA850_CCERRINT1] = 7,
694 [IRQ_DA850_TCERRINT2] = 7,
e1a8d7e2
SR		 695 [IRQ_DA850_TINTALL_3] = 7,
696 [IRQ_DA850_MCBSP0RINT] = 7,
697 [IRQ_DA850_MCBSP0XINT] = 7,
698 [IRQ_DA850_MCBSP1RINT] = 7,
699 [IRQ_DA850_MCBSP1XINT] = 7,
700 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
701};
702
703static struct map_desc da850_io_desc[] = {
704 {
705 .virtual = IO_VIRT,
706 .pfn = __phys_to_pfn(IO_PHYS),
707 .length = IO_SIZE,
708 .type = MT_DEVICE
709 },
710 {
711 .virtual = DA8XX_CP_INTC_VIRT,
712 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
713 .length = DA8XX_CP_INTC_SIZE,
714 .type = MT_DEVICE
715 },
60cd02e1
SN		 716 {
717 .virtual = SRAM_VIRT,
718 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
719 .length = SZ_8K,
720 .type = MT_DEVICE
721 },
e1a8d7e2
SR		 722};
723
e4c822c7 724static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
e1a8d7e2
SR		 725
726/* Contents of JTAG ID register used to identify exact cpu type */
727static struct davinci_id da850_ids[] = {
728 {
729 .variant = 0x0,
730 .part_no = 0xb7d1,
731 .manufacturer = 0x017, /* 0x02f >> 1 */
732 .cpu_id = DAVINCI_CPU_ID_DA850,
733 .name = "da850/omap-l138",
734 },
cbb691fb
SR		 735 {
736 .variant = 0x1,
737 .part_no = 0xb7d1,
738 .manufacturer = 0x017, /* 0x02f >> 1 */
739 .cpu_id = DAVINCI_CPU_ID_DA850,
740 .name = "da850/omap-l138/am18x",
741 },
e1a8d7e2
SR		 742};
743
744static struct davinci_timer_instance da850_timer_instance[4] = {
745 {
1bcd38ad 746 .base = DA8XX_TIMER64P0_BASE,
e1a8d7e2
SR		 747 .bottom_irq = IRQ_DA8XX_TINT12_0,
748 .top_irq = IRQ_DA8XX_TINT34_0,
749 },
750 {
1bcd38ad 751 .base = DA8XX_TIMER64P1_BASE,
e1a8d7e2
SR		 752 .bottom_irq = IRQ_DA8XX_TINT12_1,
753 .top_irq = IRQ_DA8XX_TINT34_1,
754 },
755 {
1bcd38ad 756 .base = DA850_TIMER64P2_BASE,
e1a8d7e2
SR		 757 .bottom_irq = IRQ_DA850_TINT12_2,
758 .top_irq = IRQ_DA850_TINT34_2,
759 },
760 {
1bcd38ad 761 .base = DA850_TIMER64P3_BASE,
e1a8d7e2
SR		 762 .bottom_irq = IRQ_DA850_TINT12_3,
763 .top_irq = IRQ_DA850_TINT34_3,
764 },
765};
766
767/*
768 * T0_BOT: Timer 0, bottom : Used for clock_event
769 * T0_TOP: Timer 0, top : Used for clocksource
770 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
771 */
772static struct davinci_timer_info da850_timer_info = {
773 .timers = da850_timer_instance,
774 .clockevent_id = T0_BOT,
775 .clocksource_id = T0_TOP,
776};
777
5d36a332
SN		 778static void da850_set_async3_src(int pllnum)
779{
780 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
08aca087 781 struct clk_lookup *c;
5d36a332
SN		 782 unsigned int v;
783 int ret;
784
08aca087
KH		 785 for (c = da850_clks; c->clk; c++) {
786 clk = c->clk;
5d36a332
SN		 787 if (clk->flags & DA850_CLK_ASYNC3) {
788 ret = clk_set_parent(clk, newparent);
789 WARN(ret, "DA850: unable to re-parent clock %s",
790 clk->name);
791 }
792 }
793
d2de0582 794 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 795 if (pllnum)
796 v |= CFGCHIP3_ASYNC3_CLKSRC;
797 else
798 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
d2de0582 799 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 800}
801
683b1e1f
SN		 802#ifdef CONFIG_CPU_FREQ
803/*
804 * Notes:
805 * According to the TRM, minimum PLLM results in maximum power savings.
806 * The OPP definitions below should keep the PLLM as low as possible.
807 *
39e14550 808 * The output of the PLLM must be between 300 to 600 MHz.
683b1e1f
SN		 809 */
810struct da850_opp {
811 unsigned int freq; /* in KHz */
812 unsigned int prediv;
813 unsigned int mult;
814 unsigned int postdiv;
35f9acd8
SN		 815 unsigned int cvdd_min; /* in uV */
816 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 817};
818
39e14550
SN		 819static const struct da850_opp da850_opp_456 = {
820 .freq = 456000,
821 .prediv = 1,
822 .mult = 19,
823 .postdiv = 1,
824 .cvdd_min = 1300000,
825 .cvdd_max = 1350000,
826};
827
828static const struct da850_opp da850_opp_408 = {
829 .freq = 408000,
830 .prediv = 1,
831 .mult = 17,
832 .postdiv = 1,
833 .cvdd_min = 1300000,
834 .cvdd_max = 1350000,
835};
836
837static const struct da850_opp da850_opp_372 = {
838 .freq = 372000,
839 .prediv = 2,
840 .mult = 31,
841 .postdiv = 1,
842 .cvdd_min = 1200000,
843 .cvdd_max = 1320000,
844};
845
683b1e1f
SN		 846static const struct da850_opp da850_opp_300 = {
847 .freq = 300000,
848 .prediv = 1,
849 .mult = 25,
850 .postdiv = 2,
6ef62f82 851 .cvdd_min = 1200000,
35f9acd8 852 .cvdd_max = 1320000,
683b1e1f
SN		 853};
854
855static const struct da850_opp da850_opp_200 = {
856 .freq = 200000,
857 .prediv = 1,
858 .mult = 25,
859 .postdiv = 3,
6ef62f82 860 .cvdd_min = 1100000,
35f9acd8 861 .cvdd_max = 1160000,
683b1e1f
SN		 862};
863
864static const struct da850_opp da850_opp_96 = {
865 .freq = 96000,
866 .prediv = 1,
867 .mult = 20,
868 .postdiv = 5,
6ef62f82 869 .cvdd_min = 1000000,
35f9acd8 870 .cvdd_max = 1050000,
683b1e1f
SN		 871};
872
873#define OPP(freq) \
874 { \
875 .index = (unsigned int) &da850_opp_##freq, \
876 .frequency = freq * 1000, \
877 }
878
879static struct cpufreq_frequency_table da850_freq_table[] = {
39e14550
SN		 880 OPP(456),
881 OPP(408),
882 OPP(372),
683b1e1f
SN		 883 OPP(300),
884 OPP(200),
885 OPP(96),
886 {
887 .index = 0,
888 .frequency = CPUFREQ_TABLE_END,
889 },
890};
891
39e14550
SN		 892#ifdef CONFIG_REGULATOR
893static int da850_set_voltage(unsigned int index);
894static int da850_regulator_init(void);
895#endif
896
897static struct davinci_cpufreq_config cpufreq_info = {
898 .freq_table = da850_freq_table,
899#ifdef CONFIG_REGULATOR
900 .init = da850_regulator_init,
901 .set_voltage = da850_set_voltage,
902#endif
903};
904
13d5e27a
SN		 905#ifdef CONFIG_REGULATOR
906static struct regulator *cvdd;
907
908static int da850_set_voltage(unsigned int index)
909{
910 struct da850_opp *opp;
911
912 if (!cvdd)
913 return -ENODEV;
914
39e14550 915 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
13d5e27a
SN		 916
917 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
918}
919
920static int da850_regulator_init(void)
921{
922 cvdd = regulator_get(NULL, "cvdd");
923 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
924 " voltage scaling unsupported\n")) {
925 return PTR_ERR(cvdd);
926 }
927
928 return 0;
929}
930#endif
931
683b1e1f
SN		 932static struct platform_device da850_cpufreq_device = {
933 .name = "cpufreq-davinci",
934 .dev = {
935 .platform_data = &cpufreq_info,
936 },
b987c4b2 937 .id = -1,
683b1e1f
SN		 938};
939
39e14550
SN		 940unsigned int da850_max_speed = 300000;
941
b987c4b2 942int __init da850_register_cpufreq(char *async_clk)
683b1e1f 943{
39e14550
SN		 944 int i;
945
b987c4b2
SN		 946 /* cpufreq driver can help keep an "async" clock constant */
947 if (async_clk)
948 clk_add_alias("async", da850_cpufreq_device.name,
949 async_clk, NULL);
39e14550
SN		 950 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
951 if (da850_freq_table[i].frequency <= da850_max_speed) {
952 cpufreq_info.freq_table = &da850_freq_table[i];
953 break;
954 }
955 }
b987c4b2 956
683b1e1f
SN		 957 return platform_device_register(&da850_cpufreq_device);
958}
959
960static int da850_round_armrate(struct clk *clk, unsigned long rate)
961{
962 int i, ret = 0, diff;
963 unsigned int best = (unsigned int) -1;
39e14550 964 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
683b1e1f
SN		 965
966 rate /= 1000; /* convert to kHz */
967
39e14550
SN		 968 for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
969 diff = table[i].frequency - rate;
683b1e1f
SN		 970 if (diff < 0)
971 diff = -diff;
972
973 if (diff < best) {
974 best = diff;
39e14550 975 ret = table[i].frequency;
683b1e1f
SN		 976 }
977 }
978
979 return ret * 1000;
980}
981
982static int da850_set_armrate(struct clk *clk, unsigned long index)
983{
984 struct clk *pllclk = &pll0_clk;
985
986 return clk_set_rate(pllclk, index);
987}
988
989static int da850_set_pll0rate(struct clk *clk, unsigned long index)
990{
991 unsigned int prediv, mult, postdiv;
992 struct da850_opp *opp;
993 struct pll_data *pll = clk->pll_data;
683b1e1f
SN		 994 int ret;
995
39e14550 996 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
683b1e1f
SN		 997 prediv = opp->prediv;
998 mult = opp->mult;
999 postdiv = opp->postdiv;
1000
683b1e1f
SN		 1001 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1002 if (WARN_ON(ret))
1003 return ret;
1004
1005 return 0;
1006}
1007#else
fca97b33 1008int __init da850_register_cpufreq(char *async_clk)
683b1e1f
SN		 1009{
1010 return 0;
1011}
1012
1013static int da850_set_armrate(struct clk *clk, unsigned long rate)
1014{
1015 return -EINVAL;
1016}
1017
1018static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1019{
1020 return -EINVAL;
1021}
1022
1023static int da850_round_armrate(struct clk *clk, unsigned long rate)
1024{
1025 return clk->rate;
1026}
1027#endif
1028
30c766bd 1029int __init da850_register_pm(struct platform_device *pdev)
044ca015
SN		 1030{
1031 int ret;
1032 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1033
1034 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1035 if (ret)
1036 return ret;
1037
1038 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1039 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1040 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1041
1042 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1043 if (!pdata->cpupll_reg_base)
1044 return -ENOMEM;
1045
e0c199d0 1046 pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
044ca015
SN		 1047 if (!pdata->ddrpll_reg_base) {
1048 ret = -ENOMEM;
1049 goto no_ddrpll_mem;
1050 }
1051
1052 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1053 if (!pdata->ddrpsc_reg_base) {
1054 ret = -ENOMEM;
1055 goto no_ddrpsc_mem;
1056 }
1057
1058 return platform_device_register(pdev);
1059
1060no_ddrpsc_mem:
1061 iounmap(pdata->ddrpll_reg_base);
1062no_ddrpll_mem:
1063 iounmap(pdata->cpupll_reg_base);
1064 return ret;
1065}
35f9acd8 1066
e1a8d7e2
SR		 1067static struct davinci_soc_info davinci_soc_info_da850 = {
1068 .io_desc = da850_io_desc,
1069 .io_desc_num = ARRAY_SIZE(da850_io_desc),
3347db83 1070 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
e1a8d7e2
SR		 1071 .ids = da850_ids,
1072 .ids_num = ARRAY_SIZE(da850_ids),
1073 .cpu_clks = da850_clks,
1074 .psc_bases = da850_psc_bases,
1075 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
779b0d53 1076 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
e1a8d7e2
SR		 1077 .pinmux_pins = da850_pins,
1078 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
bd808947 1079 .intc_base = DA8XX_CP_INTC_BASE,
e1a8d7e2
SR		 1080 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1081 .intc_irq_prios = da850_default_priorities,
1082 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1083 .timer_info = &da850_timer_info,
686b634a 1084 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 1085 .gpio_base = DA8XX_GPIO_BASE,
5a8d5441 1086 .gpio_num = 144,
e1a8d7e2
SR		 1087 .gpio_irq = IRQ_DA8XX_GPIO0,
1088 .serial_dev = &da8xx_serial_device,
1089 .emac_pdata = &da8xx_emac_pdata,
60cd02e1
SN		 1090 .sram_dma = DA8XX_ARM_RAM_BASE,
1091 .sram_len = SZ_8K,
e1a8d7e2
SR		 1092};
1093
1094void __init da850_init(void)
1095{
7aad472b
SN		 1096 unsigned int v;
1097
bcd6a1c6
CC		 1098 davinci_common_init(&davinci_soc_info_da850);
1099
d2de0582
SN		 1100 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1101 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1102 return;
1103
1104 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1105 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
6a28adef
SN		 1106 return;
1107
5d36a332
SN		 1108 /*
1109 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1110 * This helps keeping the peripherals on this domain insulated
1111 * from CPU frequency changes caused by DVFS. The firmware sets
1112 * both PLL0 and PLL1 to the same frequency so, there should not
25985edc 1113 * be any noticeable change even in non-DVFS use cases.
5d36a332
SN		 1114 */
1115 da850_set_async3_src(1);
7aad472b
SN		 1116
1117 /* Unlock writing to PLL0 registers */
1118 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1119 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1120 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1121
1122 /* Unlock writing to PLL1 registers */
1123 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1124 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1125 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
e1a8d7e2 1126}
Linux 6.x block layer and io_uring tree(s)