projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
davinci: dm646x-evm: Add platform data for NAND
[linux-2.6-block.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
e1a8d7e2
SR		 14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/platform_device.h>
683b1e1f 17#include <linux/cpufreq.h>
35f9acd8 18#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 19
20#include <asm/mach/map.h>
21
e1a8d7e2 22#include <mach/psc.h>
e1a8d7e2
SR		 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/common.h>
26#include <mach/time.h>
27#include <mach/da8xx.h>
683b1e1f 28#include <mach/cpufreq.h>
e1a8d7e2
SR		 29
30#include "clock.h"
31#include "mux.h"
32
5d36a332
SN		 33/* SoC specific clock flags */
34#define DA850_CLK_ASYNC3 BIT(16)
35
e1a8d7e2
SR		 36#define DA850_PLL1_BASE 0x01e1a000
37#define DA850_TIMER64P2_BASE 0x01f0c000
38#define DA850_TIMER64P3_BASE 0x01f0d000
39
40#define DA850_REF_FREQ 24000000
41
5d36a332 42#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
683b1e1f
SN		 43#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
44
45static int da850_set_armrate(struct clk *clk, unsigned long rate);
46static int da850_round_armrate(struct clk *clk, unsigned long rate);
47static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 48
e1a8d7e2
SR		 49static struct pll_data pll0_data = {
50 .num = 1,
51 .phys_base = DA8XX_PLL0_BASE,
52 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
53};
54
55static struct clk ref_clk = {
56 .name = "ref_clk",
57 .rate = DA850_REF_FREQ,
58};
59
60static struct clk pll0_clk = {
61 .name = "pll0",
62 .parent = &ref_clk,
63 .pll_data = &pll0_data,
64 .flags = CLK_PLL,
683b1e1f 65 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 66};
67
68static struct clk pll0_aux_clk = {
69 .name = "pll0_aux_clk",
70 .parent = &pll0_clk,
71 .flags = CLK_PLL | PRE_PLL,
72};
73
74static struct clk pll0_sysclk2 = {
75 .name = "pll0_sysclk2",
76 .parent = &pll0_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV2,
79};
80
81static struct clk pll0_sysclk3 = {
82 .name = "pll0_sysclk3",
83 .parent = &pll0_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV3,
86};
87
88static struct clk pll0_sysclk4 = {
89 .name = "pll0_sysclk4",
90 .parent = &pll0_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV4,
93};
94
95static struct clk pll0_sysclk5 = {
96 .name = "pll0_sysclk5",
97 .parent = &pll0_clk,
98 .flags = CLK_PLL,
99 .div_reg = PLLDIV5,
100};
101
102static struct clk pll0_sysclk6 = {
103 .name = "pll0_sysclk6",
104 .parent = &pll0_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV6,
107};
108
109static struct clk pll0_sysclk7 = {
110 .name = "pll0_sysclk7",
111 .parent = &pll0_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV7,
114};
115
116static struct pll_data pll1_data = {
117 .num = 2,
118 .phys_base = DA850_PLL1_BASE,
119 .flags = PLL_HAS_POSTDIV,
120};
121
122static struct clk pll1_clk = {
123 .name = "pll1",
124 .parent = &ref_clk,
125 .pll_data = &pll1_data,
126 .flags = CLK_PLL,
127};
128
129static struct clk pll1_aux_clk = {
130 .name = "pll1_aux_clk",
131 .parent = &pll1_clk,
132 .flags = CLK_PLL | PRE_PLL,
133};
134
135static struct clk pll1_sysclk2 = {
136 .name = "pll1_sysclk2",
137 .parent = &pll1_clk,
138 .flags = CLK_PLL,
139 .div_reg = PLLDIV2,
140};
141
142static struct clk pll1_sysclk3 = {
143 .name = "pll1_sysclk3",
144 .parent = &pll1_clk,
145 .flags = CLK_PLL,
146 .div_reg = PLLDIV3,
147};
148
149static struct clk pll1_sysclk4 = {
150 .name = "pll1_sysclk4",
151 .parent = &pll1_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV4,
154};
155
156static struct clk pll1_sysclk5 = {
157 .name = "pll1_sysclk5",
158 .parent = &pll1_clk,
159 .flags = CLK_PLL,
160 .div_reg = PLLDIV5,
161};
162
163static struct clk pll1_sysclk6 = {
164 .name = "pll0_sysclk6",
165 .parent = &pll0_clk,
166 .flags = CLK_PLL,
167 .div_reg = PLLDIV6,
168};
169
170static struct clk pll1_sysclk7 = {
171 .name = "pll1_sysclk7",
172 .parent = &pll1_clk,
173 .flags = CLK_PLL,
174 .div_reg = PLLDIV7,
175};
176
177static struct clk i2c0_clk = {
178 .name = "i2c0",
179 .parent = &pll0_aux_clk,
180};
181
182static struct clk timerp64_0_clk = {
183 .name = "timer0",
184 .parent = &pll0_aux_clk,
185};
186
187static struct clk timerp64_1_clk = {
188 .name = "timer1",
189 .parent = &pll0_aux_clk,
190};
191
192static struct clk arm_rom_clk = {
193 .name = "arm_rom",
194 .parent = &pll0_sysclk2,
195 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
196 .flags = ALWAYS_ENABLED,
197};
198
199static struct clk tpcc0_clk = {
200 .name = "tpcc0",
201 .parent = &pll0_sysclk2,
202 .lpsc = DA8XX_LPSC0_TPCC,
203 .flags = ALWAYS_ENABLED | CLK_PSC,
204};
205
206static struct clk tptc0_clk = {
207 .name = "tptc0",
208 .parent = &pll0_sysclk2,
209 .lpsc = DA8XX_LPSC0_TPTC0,
210 .flags = ALWAYS_ENABLED,
211};
212
213static struct clk tptc1_clk = {
214 .name = "tptc1",
215 .parent = &pll0_sysclk2,
216 .lpsc = DA8XX_LPSC0_TPTC1,
217 .flags = ALWAYS_ENABLED,
218};
219
220static struct clk tpcc1_clk = {
221 .name = "tpcc1",
222 .parent = &pll0_sysclk2,
223 .lpsc = DA850_LPSC1_TPCC1,
789a785e 224 .gpsc = 1,
e1a8d7e2 225 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 226};
227
228static struct clk tptc2_clk = {
229 .name = "tptc2",
230 .parent = &pll0_sysclk2,
231 .lpsc = DA850_LPSC1_TPTC2,
789a785e 232 .gpsc = 1,
e1a8d7e2 233 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 234};
235
236static struct clk uart0_clk = {
237 .name = "uart0",
238 .parent = &pll0_sysclk2,
239 .lpsc = DA8XX_LPSC0_UART0,
240};
241
242static struct clk uart1_clk = {
243 .name = "uart1",
244 .parent = &pll0_sysclk2,
245 .lpsc = DA8XX_LPSC1_UART1,
789a785e 246 .gpsc = 1,
5d36a332 247 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 248};
249
250static struct clk uart2_clk = {
251 .name = "uart2",
252 .parent = &pll0_sysclk2,
253 .lpsc = DA8XX_LPSC1_UART2,
789a785e 254 .gpsc = 1,
5d36a332 255 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 256};
257
258static struct clk aintc_clk = {
259 .name = "aintc",
260 .parent = &pll0_sysclk4,
261 .lpsc = DA8XX_LPSC0_AINTC,
262 .flags = ALWAYS_ENABLED,
263};
264
265static struct clk gpio_clk = {
266 .name = "gpio",
267 .parent = &pll0_sysclk4,
268 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 269 .gpsc = 1,
e1a8d7e2
SR		 270};
271
272static struct clk i2c1_clk = {
273 .name = "i2c1",
274 .parent = &pll0_sysclk4,
275 .lpsc = DA8XX_LPSC1_I2C,
789a785e 276 .gpsc = 1,
e1a8d7e2
SR		 277};
278
279static struct clk emif3_clk = {
280 .name = "emif3",
281 .parent = &pll0_sysclk5,
282 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 283 .gpsc = 1,
e1a8d7e2 284 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 285};
286
287static struct clk arm_clk = {
288 .name = "arm",
289 .parent = &pll0_sysclk6,
290 .lpsc = DA8XX_LPSC0_ARM,
291 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 292 .set_rate = da850_set_armrate,
293 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 294};
295
296static struct clk rmii_clk = {
297 .name = "rmii",
298 .parent = &pll0_sysclk7,
299};
300
5a4b1315
SR		 301static struct clk emac_clk = {
302 .name = "emac",
303 .parent = &pll0_sysclk4,
304 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 305 .gpsc = 1,
5a4b1315
SR		 306};
307
491214e1
C		 308static struct clk mcasp_clk = {
309 .name = "mcasp",
310 .parent = &pll0_sysclk2,
311 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 312 .gpsc = 1,
491214e1
C		 313};
314
5cbdf276
SR		 315static struct clk lcdc_clk = {
316 .name = "lcdc",
317 .parent = &pll0_sysclk2,
318 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 319 .gpsc = 1,
5cbdf276
SR		 320};
321
700691f2
SR		 322static struct clk mmcsd_clk = {
323 .name = "mmcsd",
324 .parent = &pll0_sysclk2,
325 .lpsc = DA8XX_LPSC0_MMC_SD,
326};
327
38beb929
SR		 328static struct clk aemif_clk = {
329 .name = "aemif",
330 .parent = &pll0_sysclk3,
331 .lpsc = DA8XX_LPSC0_EMIF25,
332 .flags = ALWAYS_ENABLED,
333};
334
e1a8d7e2
SR		 335static struct davinci_clk da850_clks[] = {
336 CLK(NULL, "ref", &ref_clk),
337 CLK(NULL, "pll0", &pll0_clk),
338 CLK(NULL, "pll0_aux", &pll0_aux_clk),
339 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
340 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
341 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
342 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
343 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
344 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
345 CLK(NULL, "pll1", &pll1_clk),
346 CLK(NULL, "pll1_aux", &pll1_aux_clk),
347 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
348 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
349 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
350 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
351 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
352 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
353 CLK("i2c_davinci.1", NULL, &i2c0_clk),
354 CLK(NULL, "timer0", &timerp64_0_clk),
355 CLK("watchdog", NULL, &timerp64_1_clk),
356 CLK(NULL, "arm_rom", &arm_rom_clk),
357 CLK(NULL, "tpcc0", &tpcc0_clk),
358 CLK(NULL, "tptc0", &tptc0_clk),
359 CLK(NULL, "tptc1", &tptc1_clk),
360 CLK(NULL, "tpcc1", &tpcc1_clk),
361 CLK(NULL, "tptc2", &tptc2_clk),
362 CLK(NULL, "uart0", &uart0_clk),
363 CLK(NULL, "uart1", &uart1_clk),
364 CLK(NULL, "uart2", &uart2_clk),
365 CLK(NULL, "aintc", &aintc_clk),
366 CLK(NULL, "gpio", &gpio_clk),
367 CLK("i2c_davinci.2", NULL, &i2c1_clk),
368 CLK(NULL, "emif3", &emif3_clk),
369 CLK(NULL, "arm", &arm_clk),
370 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 371 CLK("davinci_emac.1", NULL, &emac_clk),
491214e1 372 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
5cbdf276 373 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
700691f2 374 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
38beb929 375 CLK(NULL, "aemif", &aemif_clk),
e1a8d7e2
SR		 376 CLK(NULL, NULL, NULL),
377};
378
379/*
380 * Device specific mux setup
381 *
382 * soc description mux mode mode mux dbg
383 * reg offset mask mode
384 */
385static const struct mux_config da850_pins[] = {
386#ifdef CONFIG_DAVINCI_MUX
387 /* UART0 function */
388 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
389 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
390 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
391 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
392 /* UART1 function */
393 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
394 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
395 /* UART2 function */
396 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
397 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
398 /* I2C1 function */
399 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
400 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
401 /* I2C0 function */
402 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
403 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 404 /* EMAC function */
405 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
406 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
407 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
408 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
409 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
410 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
411 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
412 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
413 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
414 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
415 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
416 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
417 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
418 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
419 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 420 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
421 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 422 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
423 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
424 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
425 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
426 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
427 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
428 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
429 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 430 /* McASP function */
431 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
432 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
433 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
434 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
435 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
436 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
437 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
438 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
439 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
440 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
441 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
442 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
443 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
444 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
445 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
446 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
447 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
448 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
449 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
450 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
451 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
452 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
453 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 454 /* LCD function */
455 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
456 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
457 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
458 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
459 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
460 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
461 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
462 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
463 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
464 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
465 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
466 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
467 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
468 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
469 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
470 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
471 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
472 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
473 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
474 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 475 /* MMC/SD0 function */
476 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
477 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
478 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
479 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
480 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
481 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
38beb929
SR		 482 /* EMIF2.5/EMIFA function */
483 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
484 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
485 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
486 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
487 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
488 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
489 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
490 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
491 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
492 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
493 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
494 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
495 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
496 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 497 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
498 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
499 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
500 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
501 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
503 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
504 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
507 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
508 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
509 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
510 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
518 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
519 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
520 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
521 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
522 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
523 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
524 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
525 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
526 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
527 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
528 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
529 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
530 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 531 /* GPIO function */
2206771c 532 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 533 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 534 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
700691f2
SR		 535 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
536 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
e1a8d7e2
SR		 537#endif
538};
539
540const short da850_uart0_pins[] __initdata = {
541 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
542 -1
543};
544
545const short da850_uart1_pins[] __initdata = {
546 DA850_UART1_RXD, DA850_UART1_TXD,
547 -1
548};
549
550const short da850_uart2_pins[] __initdata = {
551 DA850_UART2_RXD, DA850_UART2_TXD,
552 -1
553};
554
555const short da850_i2c0_pins[] __initdata = {
556 DA850_I2C0_SDA, DA850_I2C0_SCL,
557 -1
558};
559
560const short da850_i2c1_pins[] __initdata = {
561 DA850_I2C1_SCL, DA850_I2C1_SDA,
562 -1
563};
564
5a4b1315
SR		 565const short da850_cpgmac_pins[] __initdata = {
566 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
567 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
568 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
53ca5c91
SR		 569 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
570 DA850_MDIO_D,
5a4b1315
SR		 571 -1
572};
573
2206771c
C		 574const short da850_rmii_pins[] __initdata = {
575 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
576 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
577 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
578 DA850_MDIO_D,
579 -1
580};
581
491214e1
C		 582const short da850_mcasp_pins[] __initdata = {
583 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
584 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
585 DA850_AXR_11, DA850_AXR_12,
586 -1
587};
588
5cbdf276 589const short da850_lcdcntl_pins[] __initdata = {
7761ef67
SR		 590 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
591 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
592 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
593 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
594 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 595 -1
596};
597
700691f2
SR		 598const short da850_mmcsd0_pins[] __initdata = {
599 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
600 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
601 DA850_GPIO4_0, DA850_GPIO4_1,
602 -1
603};
604
38beb929
SR		 605const short da850_nand_pins[] __initdata = {
606 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
607 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
608 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
609 DA850_NEMA_WE, DA850_NEMA_OE,
610 -1
611};
612
7c5ec609
SR		 613const short da850_nor_pins[] __initdata = {
614 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
615 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
616 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
617 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
618 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
619 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
620 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
621 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
622 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
623 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
624 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
625 DA850_EMA_A_22, DA850_EMA_A_23,
626 -1
627};
628
e1a8d7e2
SR		 629/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
630static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
631 [IRQ_DA8XX_COMMTX] = 7,
632 [IRQ_DA8XX_COMMRX] = 7,
633 [IRQ_DA8XX_NINT] = 7,
634 [IRQ_DA8XX_EVTOUT0] = 7,
635 [IRQ_DA8XX_EVTOUT1] = 7,
636 [IRQ_DA8XX_EVTOUT2] = 7,
637 [IRQ_DA8XX_EVTOUT3] = 7,
638 [IRQ_DA8XX_EVTOUT4] = 7,
639 [IRQ_DA8XX_EVTOUT5] = 7,
640 [IRQ_DA8XX_EVTOUT6] = 7,
641 [IRQ_DA8XX_EVTOUT6] = 7,
642 [IRQ_DA8XX_EVTOUT7] = 7,
643 [IRQ_DA8XX_CCINT0] = 7,
644 [IRQ_DA8XX_CCERRINT] = 7,
645 [IRQ_DA8XX_TCERRINT0] = 7,
646 [IRQ_DA8XX_AEMIFINT] = 7,
647 [IRQ_DA8XX_I2CINT0] = 7,
648 [IRQ_DA8XX_MMCSDINT0] = 7,
649 [IRQ_DA8XX_MMCSDINT1] = 7,
650 [IRQ_DA8XX_ALLINT0] = 7,
651 [IRQ_DA8XX_RTC] = 7,
652 [IRQ_DA8XX_SPINT0] = 7,
653 [IRQ_DA8XX_TINT12_0] = 7,
654 [IRQ_DA8XX_TINT34_0] = 7,
655 [IRQ_DA8XX_TINT12_1] = 7,
656 [IRQ_DA8XX_TINT34_1] = 7,
657 [IRQ_DA8XX_UARTINT0] = 7,
658 [IRQ_DA8XX_KEYMGRINT] = 7,
659 [IRQ_DA8XX_SECINT] = 7,
660 [IRQ_DA8XX_SECKEYERR] = 7,
661 [IRQ_DA850_MPUADDRERR0] = 7,
662 [IRQ_DA850_MPUPROTERR0] = 7,
663 [IRQ_DA850_IOPUADDRERR0] = 7,
664 [IRQ_DA850_IOPUPROTERR0] = 7,
665 [IRQ_DA850_IOPUADDRERR1] = 7,
666 [IRQ_DA850_IOPUPROTERR1] = 7,
667 [IRQ_DA850_IOPUADDRERR2] = 7,
668 [IRQ_DA850_IOPUPROTERR2] = 7,
669 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
670 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
671 [IRQ_DA850_MPUADDRERR1] = 7,
672 [IRQ_DA850_MPUPROTERR1] = 7,
673 [IRQ_DA850_IOPUADDRERR3] = 7,
674 [IRQ_DA850_IOPUPROTERR3] = 7,
675 [IRQ_DA850_IOPUADDRERR4] = 7,
676 [IRQ_DA850_IOPUPROTERR4] = 7,
677 [IRQ_DA850_IOPUADDRERR5] = 7,
678 [IRQ_DA850_IOPUPROTERR5] = 7,
679 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
680 [IRQ_DA8XX_CHIPINT0] = 7,
681 [IRQ_DA8XX_CHIPINT1] = 7,
682 [IRQ_DA8XX_CHIPINT2] = 7,
683 [IRQ_DA8XX_CHIPINT3] = 7,
684 [IRQ_DA8XX_TCERRINT1] = 7,
685 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
686 [IRQ_DA8XX_C0_RX_PULSE] = 7,
687 [IRQ_DA8XX_C0_TX_PULSE] = 7,
688 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
689 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
690 [IRQ_DA8XX_C1_RX_PULSE] = 7,
691 [IRQ_DA8XX_C1_TX_PULSE] = 7,
692 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
693 [IRQ_DA8XX_MEMERR] = 7,
694 [IRQ_DA8XX_GPIO0] = 7,
695 [IRQ_DA8XX_GPIO1] = 7,
696 [IRQ_DA8XX_GPIO2] = 7,
697 [IRQ_DA8XX_GPIO3] = 7,
698 [IRQ_DA8XX_GPIO4] = 7,
699 [IRQ_DA8XX_GPIO5] = 7,
700 [IRQ_DA8XX_GPIO6] = 7,
701 [IRQ_DA8XX_GPIO7] = 7,
702 [IRQ_DA8XX_GPIO8] = 7,
703 [IRQ_DA8XX_I2CINT1] = 7,
704 [IRQ_DA8XX_LCDINT] = 7,
705 [IRQ_DA8XX_UARTINT1] = 7,
706 [IRQ_DA8XX_MCASPINT] = 7,
707 [IRQ_DA8XX_ALLINT1] = 7,
708 [IRQ_DA8XX_SPINT1] = 7,
709 [IRQ_DA8XX_UHPI_INT1] = 7,
710 [IRQ_DA8XX_USB_INT] = 7,
711 [IRQ_DA8XX_IRQN] = 7,
712 [IRQ_DA8XX_RWAKEUP] = 7,
713 [IRQ_DA8XX_UARTINT2] = 7,
714 [IRQ_DA8XX_DFTSSINT] = 7,
715 [IRQ_DA8XX_EHRPWM0] = 7,
716 [IRQ_DA8XX_EHRPWM0TZ] = 7,
717 [IRQ_DA8XX_EHRPWM1] = 7,
718 [IRQ_DA8XX_EHRPWM1TZ] = 7,
719 [IRQ_DA850_SATAINT] = 7,
720 [IRQ_DA850_TINT12_2] = 7,
721 [IRQ_DA850_TINT34_2] = 7,
722 [IRQ_DA850_TINTALL_2] = 7,
723 [IRQ_DA8XX_ECAP0] = 7,
724 [IRQ_DA8XX_ECAP1] = 7,
725 [IRQ_DA8XX_ECAP2] = 7,
726 [IRQ_DA850_MMCSDINT0_1] = 7,
727 [IRQ_DA850_MMCSDINT1_1] = 7,
728 [IRQ_DA850_T12CMPINT0_2] = 7,
729 [IRQ_DA850_T12CMPINT1_2] = 7,
730 [IRQ_DA850_T12CMPINT2_2] = 7,
731 [IRQ_DA850_T12CMPINT3_2] = 7,
732 [IRQ_DA850_T12CMPINT4_2] = 7,
733 [IRQ_DA850_T12CMPINT5_2] = 7,
734 [IRQ_DA850_T12CMPINT6_2] = 7,
735 [IRQ_DA850_T12CMPINT7_2] = 7,
736 [IRQ_DA850_T12CMPINT0_3] = 7,
737 [IRQ_DA850_T12CMPINT1_3] = 7,
738 [IRQ_DA850_T12CMPINT2_3] = 7,
739 [IRQ_DA850_T12CMPINT3_3] = 7,
740 [IRQ_DA850_T12CMPINT4_3] = 7,
741 [IRQ_DA850_T12CMPINT5_3] = 7,
742 [IRQ_DA850_T12CMPINT6_3] = 7,
743 [IRQ_DA850_T12CMPINT7_3] = 7,
744 [IRQ_DA850_RPIINT] = 7,
745 [IRQ_DA850_VPIFINT] = 7,
746 [IRQ_DA850_CCINT1] = 7,
747 [IRQ_DA850_CCERRINT1] = 7,
748 [IRQ_DA850_TCERRINT2] = 7,
749 [IRQ_DA850_TINT12_3] = 7,
750 [IRQ_DA850_TINT34_3] = 7,
751 [IRQ_DA850_TINTALL_3] = 7,
752 [IRQ_DA850_MCBSP0RINT] = 7,
753 [IRQ_DA850_MCBSP0XINT] = 7,
754 [IRQ_DA850_MCBSP1RINT] = 7,
755 [IRQ_DA850_MCBSP1XINT] = 7,
756 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
757};
758
759static struct map_desc da850_io_desc[] = {
760 {
761 .virtual = IO_VIRT,
762 .pfn = __phys_to_pfn(IO_PHYS),
763 .length = IO_SIZE,
764 .type = MT_DEVICE
765 },
766 {
767 .virtual = DA8XX_CP_INTC_VIRT,
768 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
769 .length = DA8XX_CP_INTC_SIZE,
770 .type = MT_DEVICE
771 },
772};
773
774static void __iomem *da850_psc_bases[] = {
775 IO_ADDRESS(DA8XX_PSC0_BASE),
776 IO_ADDRESS(DA8XX_PSC1_BASE),
777};
778
779/* Contents of JTAG ID register used to identify exact cpu type */
780static struct davinci_id da850_ids[] = {
781 {
782 .variant = 0x0,
783 .part_no = 0xb7d1,
784 .manufacturer = 0x017, /* 0x02f >> 1 */
785 .cpu_id = DAVINCI_CPU_ID_DA850,
786 .name = "da850/omap-l138",
787 },
788};
789
790static struct davinci_timer_instance da850_timer_instance[4] = {
791 {
792 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
793 .bottom_irq = IRQ_DA8XX_TINT12_0,
794 .top_irq = IRQ_DA8XX_TINT34_0,
795 },
796 {
797 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
798 .bottom_irq = IRQ_DA8XX_TINT12_1,
799 .top_irq = IRQ_DA8XX_TINT34_1,
800 },
801 {
802 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
803 .bottom_irq = IRQ_DA850_TINT12_2,
804 .top_irq = IRQ_DA850_TINT34_2,
805 },
806 {
807 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
808 .bottom_irq = IRQ_DA850_TINT12_3,
809 .top_irq = IRQ_DA850_TINT34_3,
810 },
811};
812
813/*
814 * T0_BOT: Timer 0, bottom : Used for clock_event
815 * T0_TOP: Timer 0, top : Used for clocksource
816 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
817 */
818static struct davinci_timer_info da850_timer_info = {
819 .timers = da850_timer_instance,
820 .clockevent_id = T0_BOT,
821 .clocksource_id = T0_TOP,
822};
823
5d36a332
SN		 824static void da850_set_async3_src(int pllnum)
825{
826 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
827 struct davinci_clk *c;
828 unsigned int v;
829 int ret;
830
831 for (c = da850_clks; c->lk.clk; c++) {
832 clk = c->lk.clk;
833 if (clk->flags & DA850_CLK_ASYNC3) {
834 ret = clk_set_parent(clk, newparent);
835 WARN(ret, "DA850: unable to re-parent clock %s",
836 clk->name);
837 }
838 }
839
840 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
841 if (pllnum)
842 v |= CFGCHIP3_ASYNC3_CLKSRC;
843 else
844 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
845 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
846}
847
683b1e1f
SN		 848#ifdef CONFIG_CPU_FREQ
849/*
850 * Notes:
851 * According to the TRM, minimum PLLM results in maximum power savings.
852 * The OPP definitions below should keep the PLLM as low as possible.
853 *
854 * The output of the PLLM must be between 400 to 600 MHz.
855 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
856 */
857struct da850_opp {
858 unsigned int freq; /* in KHz */
859 unsigned int prediv;
860 unsigned int mult;
861 unsigned int postdiv;
35f9acd8
SN		 862 unsigned int cvdd_min; /* in uV */
863 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 864};
865
866static const struct da850_opp da850_opp_300 = {
867 .freq = 300000,
868 .prediv = 1,
869 .mult = 25,
870 .postdiv = 2,
35f9acd8
SN		 871 .cvdd_min = 1140000,
872 .cvdd_max = 1320000,
683b1e1f
SN		 873};
874
875static const struct da850_opp da850_opp_200 = {
876 .freq = 200000,
877 .prediv = 1,
878 .mult = 25,
879 .postdiv = 3,
35f9acd8
SN		 880 .cvdd_min = 1050000,
881 .cvdd_max = 1160000,
683b1e1f
SN		 882};
883
884static const struct da850_opp da850_opp_96 = {
885 .freq = 96000,
886 .prediv = 1,
887 .mult = 20,
888 .postdiv = 5,
35f9acd8
SN		 889 .cvdd_min = 950000,
890 .cvdd_max = 1050000,
683b1e1f
SN		 891};
892
893#define OPP(freq) \
894 { \
895 .index = (unsigned int) &da850_opp_##freq, \
896 .frequency = freq * 1000, \
897 }
898
899static struct cpufreq_frequency_table da850_freq_table[] = {
900 OPP(300),
901 OPP(200),
902 OPP(96),
903 {
904 .index = 0,
905 .frequency = CPUFREQ_TABLE_END,
906 },
907};
908
909static struct davinci_cpufreq_config cpufreq_info = {
910 .freq_table = &da850_freq_table[0],
911};
912
913static struct platform_device da850_cpufreq_device = {
914 .name = "cpufreq-davinci",
915 .dev = {
916 .platform_data = &cpufreq_info,
917 },
918};
919
920int __init da850_register_cpufreq(void)
921{
922 return platform_device_register(&da850_cpufreq_device);
923}
924
925static int da850_round_armrate(struct clk *clk, unsigned long rate)
926{
927 int i, ret = 0, diff;
928 unsigned int best = (unsigned int) -1;
929
930 rate /= 1000; /* convert to kHz */
931
932 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
933 diff = da850_freq_table[i].frequency - rate;
934 if (diff < 0)
935 diff = -diff;
936
937 if (diff < best) {
938 best = diff;
939 ret = da850_freq_table[i].frequency;
940 }
941 }
942
943 return ret * 1000;
944}
945
946static int da850_set_armrate(struct clk *clk, unsigned long index)
947{
948 struct clk *pllclk = &pll0_clk;
949
950 return clk_set_rate(pllclk, index);
951}
952
953static int da850_set_pll0rate(struct clk *clk, unsigned long index)
954{
955 unsigned int prediv, mult, postdiv;
956 struct da850_opp *opp;
957 struct pll_data *pll = clk->pll_data;
958 unsigned int v;
959 int ret;
960
961 opp = (struct da850_opp *) da850_freq_table[index].index;
962 prediv = opp->prediv;
963 mult = opp->mult;
964 postdiv = opp->postdiv;
965
966 /* Unlock writing to PLL registers */
967 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
968 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
969 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
970
971 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
972 if (WARN_ON(ret))
973 return ret;
974
975 return 0;
976}
977#else
978int __init da850_register_cpufreq(void)
979{
980 return 0;
981}
982
983static int da850_set_armrate(struct clk *clk, unsigned long rate)
984{
985 return -EINVAL;
986}
987
988static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
989{
990 return -EINVAL;
991}
992
993static int da850_round_armrate(struct clk *clk, unsigned long rate)
994{
995 return clk->rate;
996}
997#endif
998
35f9acd8
SN		 999#ifdef CONFIG_REGULATOR
1000static struct regulator *cvdd;
1001
1002static int da850_set_voltage(unsigned int index)
1003{
1004 struct da850_opp *opp;
1005
1006 if (!cvdd)
1007 return -ENODEV;
1008
1009 opp = (struct da850_opp *) da850_freq_table[index].index;
1010
1011 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1012}
1013
1014static int __init da850_regulator_init(void)
1015{
1016 int ret = 0;
1017
1018 cvdd = regulator_get(NULL, "cvdd");
1019 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1020 " voltage scaling unsupported\n")) {
1021 ret = PTR_ERR(cvdd);
1022 goto out;
1023 }
1024
1025 cpufreq_info.set_voltage = da850_set_voltage;
1026
1027out:
1028 return ret;
1029}
1030device_initcall(da850_regulator_init);
1031#endif
1032
e1a8d7e2
SR		 1033static struct davinci_soc_info davinci_soc_info_da850 = {
1034 .io_desc = da850_io_desc,
1035 .io_desc_num = ARRAY_SIZE(da850_io_desc),
e1a8d7e2
SR		 1036 .ids = da850_ids,
1037 .ids_num = ARRAY_SIZE(da850_ids),
1038 .cpu_clks = da850_clks,
1039 .psc_bases = da850_psc_bases,
1040 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
e1a8d7e2
SR		 1041 .pinmux_pins = da850_pins,
1042 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1043 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
1044 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1045 .intc_irq_prios = da850_default_priorities,
1046 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1047 .timer_info = &da850_timer_info,
1048 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
5a8d5441 1049 .gpio_num = 144,
e1a8d7e2
SR		 1050 .gpio_irq = IRQ_DA8XX_GPIO0,
1051 .serial_dev = &da8xx_serial_device,
1052 .emac_pdata = &da8xx_emac_pdata,
1053};
1054
1055void __init da850_init(void)
1056{
6a28adef
SN		 1057 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
1058 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
1059 return;
1060
cd874448
SN		 1061 davinci_soc_info_da850.jtag_id_base =
1062 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
6a28adef
SN		 1063 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
1064
e1a8d7e2 1065 davinci_common_init(&davinci_soc_info_da850);
5d36a332
SN		 1066
1067 /*
1068 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1069 * This helps keeping the peripherals on this domain insulated
1070 * from CPU frequency changes caused by DVFS. The firmware sets
1071 * both PLL0 and PLL1 to the same frequency so, there should not
1072 * be any noticible change even in non-DVFS use cases.
1073 */
1074 da850_set_async3_src(1);
e1a8d7e2 1075}
Linux 6.x block layer and io_uring tree(s)