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Merge tag 'kvm-ppc-fixes-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
482db889
DL		 14
15#include <linux/clk-provider.h>
16#include <linux/clk/davinci.h>
2d34e507 17#include <linux/clkdev.h>
482db889 18#include <linux/cpufreq.h>
2f8163ba 19#include <linux/gpio.h>
e1a8d7e2 20#include <linux/init.h>
62e59c4e 21#include <linux/io.h>
47b7c619 22#include <linux/irqchip/irq-davinci-cp-intc.h>
482db889
DL		 23#include <linux/mfd/da8xx-cfgchip.h>
24#include <linux/platform_data/clk-da8xx-cfgchip.h>
25#include <linux/platform_data/clk-davinci-pll.h>
40b46b3b 26#include <linux/platform_data/davinci-cpufreq.h>
482db889 27#include <linux/platform_data/gpio-davinci.h>
e1a8d7e2 28#include <linux/platform_device.h>
482db889 29#include <linux/regmap.h>
35f9acd8 30#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 31
32#include <asm/mach/map.h>
33
e1a8d7e2 34#include <mach/common.h>
482db889
DL		 35#include <mach/cputype.h>
36#include <mach/da8xx.h>
044ca015 37#include <mach/pm.h>
482db889 38#include <mach/time.h>
e1a8d7e2 39
544ca0b0 40#include "irqs.h"
e1a8d7e2
SR		 41#include "mux.h"
42
43#define DA850_PLL1_BASE 0x01e1a000
44#define DA850_TIMER64P2_BASE 0x01f0c000
45#define DA850_TIMER64P3_BASE 0x01f0d000
46
47#define DA850_REF_FREQ 24000000
48
e1a8d7e2
SR		 49/*
50 * Device specific mux setup
51 *
52 * soc description mux mode mode mux dbg
53 * reg offset mask mode
54 */
55static const struct mux_config da850_pins[] = {
56#ifdef CONFIG_DAVINCI_MUX
57 /* UART0 function */
58 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
59 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
60 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
61 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
62 /* UART1 function */
63 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
64 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
65 /* UART2 function */
66 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
67 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
68 /* I2C1 function */
69 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
70 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
71 /* I2C0 function */
72 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
73 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 74 /* EMAC function */
75 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
76 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
77 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
78 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
79 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
80 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
81 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
82 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
83 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
84 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
85 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
86 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
87 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
88 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
89 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 90 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
91 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 92 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
93 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
94 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
95 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
96 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
97 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
98 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
99 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 100 /* McASP function */
101 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
102 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
103 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
104 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
105 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
106 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
107 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
108 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
109 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
110 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
111 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
112 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
113 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
114 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
115 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
116 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
117 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
118 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
119 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
120 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
121 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
122 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
123 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 124 /* LCD function */
125 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
126 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
127 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
128 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
129 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
130 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
131 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
132 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
133 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
134 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
135 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
136 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
137 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
138 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
139 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
140 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
141 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
142 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
143 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
144 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 145 /* MMC/SD0 function */
146 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
147 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
148 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
149 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
150 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
151 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
5c4d11b4
IY		 152 /* MMC/SD1 function */
153 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
154 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
155 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
156 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
157 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
158 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
38beb929
SR		 159 /* EMIF2.5/EMIFA function */
160 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
161 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
162 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
163 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
164 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
165 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
166 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
167 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
168 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
169 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
170 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
171 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
172 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
173 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 174 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
175 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
176 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
177 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
178 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
179 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
180 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
181 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
182 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
183 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
184 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
185 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
186 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
187 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
188 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
189 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
190 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
191 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
192 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
193 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
194 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
195 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
196 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
197 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
198 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
199 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
200 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
201 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
202 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
203 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
204 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
205 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
206 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
207 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 208 /* GPIO function */
fe358d6a 209 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
2206771c 210 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 211 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 212 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
fe358d6a
VR		 213 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
214 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
700691f2
SR		 215 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
216 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
6836989c
IY		 217 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
218 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
fe358d6a 219 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
044ca015 220 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
154d54a8
MH		 221 /* VPIF Capture */
222 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
223 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
224 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
225 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
226 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
227 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
228 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
229 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
230 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
231 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
232 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
233 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
234 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
235 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
236 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
237 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
238 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
239 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
240 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
241 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
242 /* VPIF Display */
243 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
244 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
245 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
246 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
247 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
248 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
249 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
250 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
251 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
252 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
253 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
254 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
255 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
256 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
257 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
258 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
259 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
260 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
e1a8d7e2
SR		 261#endif
262};
263
bcad6dc3 264const short da850_i2c0_pins[] __initconst = {
e1a8d7e2
SR		 265 DA850_I2C0_SDA, DA850_I2C0_SCL,
266 -1
267};
268
bcad6dc3 269const short da850_i2c1_pins[] __initconst = {
e1a8d7e2
SR		 270 DA850_I2C1_SCL, DA850_I2C1_SDA,
271 -1
272};
273
bcad6dc3 274const short da850_lcdcntl_pins[] __initconst = {
7761ef67
SR		 275 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
276 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
277 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
278 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
279 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 280 -1
281};
282
19c233b7 283const short da850_vpif_capture_pins[] __initconst = {
154d54a8
MH		 284 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
285 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
286 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
287 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
288 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
289 DA850_VPIF_CLKIN3,
290 -1
291};
292
19c233b7 293const short da850_vpif_display_pins[] __initconst = {
154d54a8
MH		 294 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
295 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
296 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
297 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
298 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
299 DA850_VPIF_CLKO3,
300 -1
301};
302
e1a8d7e2
SR		 303static struct map_desc da850_io_desc[] = {
304 {
305 .virtual = IO_VIRT,
306 .pfn = __phys_to_pfn(IO_PHYS),
307 .length = IO_SIZE,
308 .type = MT_DEVICE
309 },
310 {
311 .virtual = DA8XX_CP_INTC_VIRT,
312 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
313 .length = DA8XX_CP_INTC_SIZE,
314 .type = MT_DEVICE
315 },
316};
317
e1a8d7e2
SR		 318/* Contents of JTAG ID register used to identify exact cpu type */
319static struct davinci_id da850_ids[] = {
320 {
321 .variant = 0x0,
322 .part_no = 0xb7d1,
323 .manufacturer = 0x017, /* 0x02f >> 1 */
324 .cpu_id = DAVINCI_CPU_ID_DA850,
325 .name = "da850/omap-l138",
326 },
cbb691fb
SR		 327 {
328 .variant = 0x1,
329 .part_no = 0xb7d1,
330 .manufacturer = 0x017, /* 0x02f >> 1 */
331 .cpu_id = DAVINCI_CPU_ID_DA850,
332 .name = "da850/omap-l138/am18x",
333 },
e1a8d7e2
SR		 334};
335
336static struct davinci_timer_instance da850_timer_instance[4] = {
337 {
1bcd38ad 338 .base = DA8XX_TIMER64P0_BASE,
a98ca73e
BG		 339 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
340 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
e1a8d7e2
SR		 341 },
342 {
1bcd38ad 343 .base = DA8XX_TIMER64P1_BASE,
a98ca73e
BG		 344 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
345 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
e1a8d7e2
SR		 346 },
347 {
1bcd38ad 348 .base = DA850_TIMER64P2_BASE,
a98ca73e
BG		 349 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2),
350 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2),
e1a8d7e2
SR		 351 },
352 {
1bcd38ad 353 .base = DA850_TIMER64P3_BASE,
a98ca73e
BG		 354 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3),
355 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3),
e1a8d7e2
SR		 356 },
357};
358
359/*
360 * T0_BOT: Timer 0, bottom : Used for clock_event
361 * T0_TOP: Timer 0, top : Used for clocksource
362 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
363 */
364static struct davinci_timer_info da850_timer_info = {
365 .timers = da850_timer_instance,
366 .clockevent_id = T0_BOT,
367 .clocksource_id = T0_TOP,
368};
369
683b1e1f
SN		 370#ifdef CONFIG_CPU_FREQ
371/*
372 * Notes:
373 * According to the TRM, minimum PLLM results in maximum power savings.
374 * The OPP definitions below should keep the PLLM as low as possible.
375 *
39e14550 376 * The output of the PLLM must be between 300 to 600 MHz.
683b1e1f
SN		 377 */
378struct da850_opp {
379 unsigned int freq; /* in KHz */
380 unsigned int prediv;
381 unsigned int mult;
382 unsigned int postdiv;
35f9acd8
SN		 383 unsigned int cvdd_min; /* in uV */
384 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 385};
386
39e14550
SN		 387static const struct da850_opp da850_opp_456 = {
388 .freq = 456000,
389 .prediv = 1,
390 .mult = 19,
391 .postdiv = 1,
392 .cvdd_min = 1300000,
393 .cvdd_max = 1350000,
394};
395
396static const struct da850_opp da850_opp_408 = {
397 .freq = 408000,
398 .prediv = 1,
399 .mult = 17,
400 .postdiv = 1,
401 .cvdd_min = 1300000,
402 .cvdd_max = 1350000,
403};
404
405static const struct da850_opp da850_opp_372 = {
406 .freq = 372000,
407 .prediv = 2,
408 .mult = 31,
409 .postdiv = 1,
410 .cvdd_min = 1200000,
411 .cvdd_max = 1320000,
412};
413
683b1e1f
SN		 414static const struct da850_opp da850_opp_300 = {
415 .freq = 300000,
416 .prediv = 1,
417 .mult = 25,
418 .postdiv = 2,
6ef62f82 419 .cvdd_min = 1200000,
35f9acd8 420 .cvdd_max = 1320000,
683b1e1f
SN		 421};
422
423static const struct da850_opp da850_opp_200 = {
424 .freq = 200000,
425 .prediv = 1,
426 .mult = 25,
427 .postdiv = 3,
6ef62f82 428 .cvdd_min = 1100000,
35f9acd8 429 .cvdd_max = 1160000,
683b1e1f
SN		 430};
431
432static const struct da850_opp da850_opp_96 = {
433 .freq = 96000,
434 .prediv = 1,
435 .mult = 20,
436 .postdiv = 5,
6ef62f82 437 .cvdd_min = 1000000,
35f9acd8 438 .cvdd_max = 1050000,
683b1e1f
SN		 439};
440
441#define OPP(freq) \
442 { \
50701588 443 .driver_data = (unsigned int) &da850_opp_##freq, \
683b1e1f
SN		 444 .frequency = freq * 1000, \
445 }
446
447static struct cpufreq_frequency_table da850_freq_table[] = {
39e14550
SN		 448 OPP(456),
449 OPP(408),
450 OPP(372),
683b1e1f
SN		 451 OPP(300),
452 OPP(200),
453 OPP(96),
454 {
50701588 455 .driver_data = 0,
683b1e1f
SN		 456 .frequency = CPUFREQ_TABLE_END,
457 },
458};
459
39e14550
SN		 460#ifdef CONFIG_REGULATOR
461static int da850_set_voltage(unsigned int index);
462static int da850_regulator_init(void);
463#endif
464
465static struct davinci_cpufreq_config cpufreq_info = {
466 .freq_table = da850_freq_table,
467#ifdef CONFIG_REGULATOR
468 .init = da850_regulator_init,
469 .set_voltage = da850_set_voltage,
470#endif
471};
472
13d5e27a
SN		 473#ifdef CONFIG_REGULATOR
474static struct regulator *cvdd;
475
476static int da850_set_voltage(unsigned int index)
477{
478 struct da850_opp *opp;
479
480 if (!cvdd)
481 return -ENODEV;
482
50701588 483 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
13d5e27a
SN		 484
485 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
486}
487
488static int da850_regulator_init(void)
489{
490 cvdd = regulator_get(NULL, "cvdd");
491 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
492 " voltage scaling unsupported\n")) {
493 return PTR_ERR(cvdd);
494 }
495
496 return 0;
497}
498#endif
499
683b1e1f
SN		 500static struct platform_device da850_cpufreq_device = {
501 .name = "cpufreq-davinci",
502 .dev = {
503 .platform_data = &cpufreq_info,
504 },
b987c4b2 505 .id = -1,
683b1e1f
SN		 506};
507
39e14550
SN		 508unsigned int da850_max_speed = 300000;
509
5063557a 510int da850_register_cpufreq(char *async_clk)
683b1e1f 511{
39e14550
SN		 512 int i;
513
b987c4b2
SN		 514 /* cpufreq driver can help keep an "async" clock constant */
515 if (async_clk)
516 clk_add_alias("async", da850_cpufreq_device.name,
517 async_clk, NULL);
39e14550
SN		 518 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
519 if (da850_freq_table[i].frequency <= da850_max_speed) {
520 cpufreq_info.freq_table = &da850_freq_table[i];
521 break;
522 }
523 }
b987c4b2 524
683b1e1f
SN		 525 return platform_device_register(&da850_cpufreq_device);
526}
683b1e1f 527#else
fca97b33 528int __init da850_register_cpufreq(char *async_clk)
683b1e1f
SN		 529{
530 return 0;
531}
683b1e1f
SN		 532#endif
533
154d54a8
MH		 534/* VPIF resource, platform data */
535static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
536
537static struct resource da850_vpif_resource[] = {
538 {
539 .start = DA8XX_VPIF_BASE,
540 .end = DA8XX_VPIF_BASE + 0xfff,
541 .flags = IORESOURCE_MEM,
542 }
543};
544
545static struct platform_device da850_vpif_dev = {
546 .name = "vpif",
547 .id = -1,
548 .dev = {
549 .dma_mask = &da850_vpif_dma_mask,
550 .coherent_dma_mask = DMA_BIT_MASK(32),
551 },
552 .resource = da850_vpif_resource,
553 .num_resources = ARRAY_SIZE(da850_vpif_resource),
554};
555
556static struct resource da850_vpif_display_resource[] = {
557 {
a98ca73e
BG		 558 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
559 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
154d54a8
MH		 560 .flags = IORESOURCE_IRQ,
561 },
562};
563
564static struct platform_device da850_vpif_display_dev = {
565 .name = "vpif_display",
566 .id = -1,
567 .dev = {
568 .dma_mask = &da850_vpif_dma_mask,
569 .coherent_dma_mask = DMA_BIT_MASK(32),
570 },
571 .resource = da850_vpif_display_resource,
572 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
573};
574
575static struct resource da850_vpif_capture_resource[] = {
576 {
a98ca73e
BG		 577 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
578 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
154d54a8
MH		 579 .flags = IORESOURCE_IRQ,
580 },
581 {
a98ca73e
BG		 582 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
583 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
154d54a8
MH		 584 .flags = IORESOURCE_IRQ,
585 },
586};
587
588static struct platform_device da850_vpif_capture_dev = {
589 .name = "vpif_capture",
590 .id = -1,
591 .dev = {
592 .dma_mask = &da850_vpif_dma_mask,
593 .coherent_dma_mask = DMA_BIT_MASK(32),
594 },
595 .resource = da850_vpif_capture_resource,
596 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
597};
598
599int __init da850_register_vpif(void)
600{
601 return platform_device_register(&da850_vpif_dev);
602}
603
604int __init da850_register_vpif_display(struct vpif_display_config
605 *display_config)
606{
607 da850_vpif_display_dev.dev.platform_data = display_config;
608 return platform_device_register(&da850_vpif_display_dev);
609}
610
611int __init da850_register_vpif_capture(struct vpif_capture_config
612 *capture_config)
613{
614 da850_vpif_capture_dev.dev.platform_data = capture_config;
615 return platform_device_register(&da850_vpif_capture_dev);
616}
617
f606d38d 618static struct davinci_gpio_platform_data da850_gpio_platform_data = {
45ed94b9
BG		 619 .no_auto_base = true,
620 .base = 0,
621 .ngpio = 144,
f606d38d
KS		 622};
623
624int __init da850_register_gpio(void)
625{
626 return da8xx_register_gpio(&da850_gpio_platform_data);
627}
628
ab41910d 629static const struct davinci_soc_info davinci_soc_info_da850 = {
e1a8d7e2
SR		 630 .io_desc = da850_io_desc,
631 .io_desc_num = ARRAY_SIZE(da850_io_desc),
3347db83 632 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
e1a8d7e2
SR		 633 .ids = da850_ids,
634 .ids_num = ARRAY_SIZE(da850_ids),
779b0d53 635 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
e1a8d7e2
SR		 636 .pinmux_pins = da850_pins,
637 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
e1a8d7e2 638 .timer_info = &da850_timer_info,
e1a8d7e2 639 .emac_pdata = &da8xx_emac_pdata,
c94472d4
SG		 640 .sram_dma = DA8XX_SHARED_RAM_BASE,
641 .sram_len = SZ_128K,
e1a8d7e2
SR		 642};
643
644void __init da850_init(void)
645{
bcd6a1c6
CC		 646 davinci_common_init(&davinci_soc_info_da850);
647
d2de0582
SN		 648 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
649 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
650 return;
651
652 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
9cc247b8 653 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
96c08173 654}
6fc9ebbd 655
47b7c619
BG		 656static const struct davinci_cp_intc_config da850_cp_intc_config = {
657 .reg = {
658 .start = DA8XX_CP_INTC_BASE,
659 .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
660 .flags = IORESOURCE_MEM,
661 },
662 .num_irqs = DA850_N_CP_INTC_IRQ,
663};
664
f451ca3e
BG		 665void __init da850_init_irq(void)
666{
6567954b 667 davinci_cp_intc_init(&da850_cp_intc_config);
f451ca3e
BG		 668}
669
96c08173
DL		 670void __init da850_init_time(void)
671{
482db889
DL		 672 void __iomem *pll0;
673 struct regmap *cfgchip;
674 struct clk *clk;
675
676 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
677
678 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
679 cfgchip = da8xx_get_cfgchip();
680
681 da850_pll0_init(NULL, pll0, cfgchip);
682
683 clk = clk_get(NULL, "timer0");
684
685 davinci_timer_init(clk);
482db889
DL		 686}
687
688static struct resource da850_pll1_resources[] = {
689 {
690 .start = DA850_PLL1_BASE,
691 .end = DA850_PLL1_BASE + SZ_4K - 1,
692 .flags = IORESOURCE_MEM,
693 },
694};
695
696static struct davinci_pll_platform_data da850_pll1_pdata;
697
698static struct platform_device da850_pll1_device = {
699 .name = "da850-pll1",
700 .id = -1,
701 .resource = da850_pll1_resources,
702 .num_resources = ARRAY_SIZE(da850_pll1_resources),
703 .dev = {
704 .platform_data = &da850_pll1_pdata,
705 },
706};
707
708static struct resource da850_psc0_resources[] = {
709 {
710 .start = DA8XX_PSC0_BASE,
711 .end = DA8XX_PSC0_BASE + SZ_4K - 1,
712 .flags = IORESOURCE_MEM,
713 },
714};
715
716static struct platform_device da850_psc0_device = {
717 .name = "da850-psc0",
718 .id = -1,
719 .resource = da850_psc0_resources,
720 .num_resources = ARRAY_SIZE(da850_psc0_resources),
721};
722
723static struct resource da850_psc1_resources[] = {
724 {
725 .start = DA8XX_PSC1_BASE,
726 .end = DA8XX_PSC1_BASE + SZ_4K - 1,
727 .flags = IORESOURCE_MEM,
728 },
729};
730
731static struct platform_device da850_psc1_device = {
732 .name = "da850-psc1",
733 .id = -1,
734 .resource = da850_psc1_resources,
735 .num_resources = ARRAY_SIZE(da850_psc1_resources),
736};
737
738static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
739
740static struct platform_device da850_async1_clksrc_device = {
741 .name = "da850-async1-clksrc",
742 .id = -1,
743 .dev = {
744 .platform_data = &da850_async1_pdata,
745 },
746};
747
748static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
749
750static struct platform_device da850_async3_clksrc_device = {
751 .name = "da850-async3-clksrc",
752 .id = -1,
753 .dev = {
754 .platform_data = &da850_async3_pdata,
755 },
756};
757
758static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
759
760static struct platform_device da850_tbclksync_device = {
761 .name = "da830-tbclksync",
762 .id = -1,
763 .dev = {
764 .platform_data = &da850_tbclksync_pdata,
765 },
766};
767
768void __init da850_register_clocks(void)
769{
770 /* PLL0 is registered in da850_init_time() */
771
772 da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
773 platform_device_register(&da850_pll1_device);
774
775 da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
776 platform_device_register(&da850_async1_clksrc_device);
777
778 da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
779 platform_device_register(&da850_async3_clksrc_device);
780
781 platform_device_register(&da850_psc0_device);
782
783 platform_device_register(&da850_psc1_device);
784
785 da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
786 platform_device_register(&da850_tbclksync_device);
e1a8d7e2 787}
Linux 6.x block layer and io_uring tree(s)