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e1a8d7e2 SR |
1 | /* |
2 | * TI DA850/OMAP-L138 chip specific setup | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * Derived from: arch/arm/mach-davinci/da830.c | |
7 | * Original Copyrights follow: | |
8 | * | |
9 | * 2009 (c) MontaVista Software, Inc. This file is licensed under | |
10 | * the terms of the GNU General Public License version 2. This program | |
11 | * is licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | */ | |
2d34e507 | 14 | #include <linux/clkdev.h> |
2f8163ba | 15 | #include <linux/gpio.h> |
e1a8d7e2 SR |
16 | #include <linux/init.h> |
17 | #include <linux/clk.h> | |
18 | #include <linux/platform_device.h> | |
683b1e1f | 19 | #include <linux/cpufreq.h> |
35f9acd8 | 20 | #include <linux/regulator/consumer.h> |
f606d38d | 21 | #include <linux/platform_data/gpio-davinci.h> |
e1a8d7e2 SR |
22 | |
23 | #include <asm/mach/map.h> | |
24 | ||
e1a8d7e2 | 25 | #include <mach/psc.h> |
e1a8d7e2 SR |
26 | #include <mach/irqs.h> |
27 | #include <mach/cputype.h> | |
28 | #include <mach/common.h> | |
29 | #include <mach/time.h> | |
30 | #include <mach/da8xx.h> | |
683b1e1f | 31 | #include <mach/cpufreq.h> |
044ca015 | 32 | #include <mach/pm.h> |
e1a8d7e2 SR |
33 | |
34 | #include "clock.h" | |
35 | #include "mux.h" | |
36 | ||
5d36a332 SN |
37 | /* SoC specific clock flags */ |
38 | #define DA850_CLK_ASYNC3 BIT(16) | |
39 | ||
e1a8d7e2 SR |
40 | #define DA850_PLL1_BASE 0x01e1a000 |
41 | #define DA850_TIMER64P2_BASE 0x01f0c000 | |
42 | #define DA850_TIMER64P3_BASE 0x01f0d000 | |
43 | ||
44 | #define DA850_REF_FREQ 24000000 | |
45 | ||
5d36a332 | 46 | #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) |
7aad472b | 47 | #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) |
683b1e1f SN |
48 | #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) |
49 | ||
50 | static int da850_set_armrate(struct clk *clk, unsigned long rate); | |
51 | static int da850_round_armrate(struct clk *clk, unsigned long rate); | |
52 | static int da850_set_pll0rate(struct clk *clk, unsigned long armrate); | |
5d36a332 | 53 | |
e1a8d7e2 SR |
54 | static struct pll_data pll0_data = { |
55 | .num = 1, | |
56 | .phys_base = DA8XX_PLL0_BASE, | |
57 | .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, | |
58 | }; | |
59 | ||
60 | static struct clk ref_clk = { | |
61 | .name = "ref_clk", | |
62 | .rate = DA850_REF_FREQ, | |
8d54297b | 63 | .set_rate = davinci_simple_set_rate, |
e1a8d7e2 SR |
64 | }; |
65 | ||
66 | static struct clk pll0_clk = { | |
67 | .name = "pll0", | |
68 | .parent = &ref_clk, | |
69 | .pll_data = &pll0_data, | |
70 | .flags = CLK_PLL, | |
683b1e1f | 71 | .set_rate = da850_set_pll0rate, |
e1a8d7e2 SR |
72 | }; |
73 | ||
74 | static struct clk pll0_aux_clk = { | |
75 | .name = "pll0_aux_clk", | |
76 | .parent = &pll0_clk, | |
77 | .flags = CLK_PLL | PRE_PLL, | |
78 | }; | |
79 | ||
09810a85 RT |
80 | static struct clk pll0_sysclk1 = { |
81 | .name = "pll0_sysclk1", | |
82 | .parent = &pll0_clk, | |
83 | .flags = CLK_PLL, | |
84 | .div_reg = PLLDIV1, | |
85 | }; | |
86 | ||
e1a8d7e2 SR |
87 | static struct clk pll0_sysclk2 = { |
88 | .name = "pll0_sysclk2", | |
89 | .parent = &pll0_clk, | |
90 | .flags = CLK_PLL, | |
91 | .div_reg = PLLDIV2, | |
92 | }; | |
93 | ||
94 | static struct clk pll0_sysclk3 = { | |
95 | .name = "pll0_sysclk3", | |
96 | .parent = &pll0_clk, | |
97 | .flags = CLK_PLL, | |
98 | .div_reg = PLLDIV3, | |
b987c4b2 SN |
99 | .set_rate = davinci_set_sysclk_rate, |
100 | .maxrate = 100000000, | |
e1a8d7e2 SR |
101 | }; |
102 | ||
103 | static struct clk pll0_sysclk4 = { | |
104 | .name = "pll0_sysclk4", | |
105 | .parent = &pll0_clk, | |
106 | .flags = CLK_PLL, | |
107 | .div_reg = PLLDIV4, | |
108 | }; | |
109 | ||
110 | static struct clk pll0_sysclk5 = { | |
111 | .name = "pll0_sysclk5", | |
112 | .parent = &pll0_clk, | |
113 | .flags = CLK_PLL, | |
114 | .div_reg = PLLDIV5, | |
115 | }; | |
116 | ||
117 | static struct clk pll0_sysclk6 = { | |
118 | .name = "pll0_sysclk6", | |
119 | .parent = &pll0_clk, | |
120 | .flags = CLK_PLL, | |
121 | .div_reg = PLLDIV6, | |
122 | }; | |
123 | ||
124 | static struct clk pll0_sysclk7 = { | |
125 | .name = "pll0_sysclk7", | |
126 | .parent = &pll0_clk, | |
127 | .flags = CLK_PLL, | |
128 | .div_reg = PLLDIV7, | |
129 | }; | |
130 | ||
131 | static struct pll_data pll1_data = { | |
132 | .num = 2, | |
133 | .phys_base = DA850_PLL1_BASE, | |
134 | .flags = PLL_HAS_POSTDIV, | |
135 | }; | |
136 | ||
137 | static struct clk pll1_clk = { | |
138 | .name = "pll1", | |
139 | .parent = &ref_clk, | |
140 | .pll_data = &pll1_data, | |
141 | .flags = CLK_PLL, | |
142 | }; | |
143 | ||
144 | static struct clk pll1_aux_clk = { | |
145 | .name = "pll1_aux_clk", | |
146 | .parent = &pll1_clk, | |
147 | .flags = CLK_PLL | PRE_PLL, | |
148 | }; | |
149 | ||
150 | static struct clk pll1_sysclk2 = { | |
151 | .name = "pll1_sysclk2", | |
152 | .parent = &pll1_clk, | |
153 | .flags = CLK_PLL, | |
154 | .div_reg = PLLDIV2, | |
155 | }; | |
156 | ||
157 | static struct clk pll1_sysclk3 = { | |
158 | .name = "pll1_sysclk3", | |
159 | .parent = &pll1_clk, | |
160 | .flags = CLK_PLL, | |
161 | .div_reg = PLLDIV3, | |
162 | }; | |
163 | ||
e1a8d7e2 SR |
164 | static struct clk i2c0_clk = { |
165 | .name = "i2c0", | |
166 | .parent = &pll0_aux_clk, | |
167 | }; | |
168 | ||
169 | static struct clk timerp64_0_clk = { | |
170 | .name = "timer0", | |
171 | .parent = &pll0_aux_clk, | |
172 | }; | |
173 | ||
174 | static struct clk timerp64_1_clk = { | |
175 | .name = "timer1", | |
176 | .parent = &pll0_aux_clk, | |
177 | }; | |
178 | ||
179 | static struct clk arm_rom_clk = { | |
180 | .name = "arm_rom", | |
181 | .parent = &pll0_sysclk2, | |
182 | .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, | |
183 | .flags = ALWAYS_ENABLED, | |
184 | }; | |
185 | ||
186 | static struct clk tpcc0_clk = { | |
187 | .name = "tpcc0", | |
188 | .parent = &pll0_sysclk2, | |
189 | .lpsc = DA8XX_LPSC0_TPCC, | |
190 | .flags = ALWAYS_ENABLED | CLK_PSC, | |
191 | }; | |
192 | ||
193 | static struct clk tptc0_clk = { | |
194 | .name = "tptc0", | |
195 | .parent = &pll0_sysclk2, | |
196 | .lpsc = DA8XX_LPSC0_TPTC0, | |
197 | .flags = ALWAYS_ENABLED, | |
198 | }; | |
199 | ||
200 | static struct clk tptc1_clk = { | |
201 | .name = "tptc1", | |
202 | .parent = &pll0_sysclk2, | |
203 | .lpsc = DA8XX_LPSC0_TPTC1, | |
204 | .flags = ALWAYS_ENABLED, | |
205 | }; | |
206 | ||
207 | static struct clk tpcc1_clk = { | |
208 | .name = "tpcc1", | |
209 | .parent = &pll0_sysclk2, | |
210 | .lpsc = DA850_LPSC1_TPCC1, | |
789a785e | 211 | .gpsc = 1, |
e1a8d7e2 | 212 | .flags = CLK_PSC | ALWAYS_ENABLED, |
e1a8d7e2 SR |
213 | }; |
214 | ||
215 | static struct clk tptc2_clk = { | |
216 | .name = "tptc2", | |
217 | .parent = &pll0_sysclk2, | |
218 | .lpsc = DA850_LPSC1_TPTC2, | |
789a785e | 219 | .gpsc = 1, |
e1a8d7e2 | 220 | .flags = ALWAYS_ENABLED, |
e1a8d7e2 SR |
221 | }; |
222 | ||
8e0d72d2 MP |
223 | static struct clk pruss_clk = { |
224 | .name = "pruss", | |
225 | .parent = &pll0_sysclk2, | |
226 | .lpsc = DA8XX_LPSC0_PRUSS, | |
227 | }; | |
228 | ||
e1a8d7e2 SR |
229 | static struct clk uart0_clk = { |
230 | .name = "uart0", | |
231 | .parent = &pll0_sysclk2, | |
232 | .lpsc = DA8XX_LPSC0_UART0, | |
233 | }; | |
234 | ||
235 | static struct clk uart1_clk = { | |
236 | .name = "uart1", | |
237 | .parent = &pll0_sysclk2, | |
238 | .lpsc = DA8XX_LPSC1_UART1, | |
789a785e | 239 | .gpsc = 1, |
5d36a332 | 240 | .flags = DA850_CLK_ASYNC3, |
e1a8d7e2 SR |
241 | }; |
242 | ||
243 | static struct clk uart2_clk = { | |
244 | .name = "uart2", | |
245 | .parent = &pll0_sysclk2, | |
246 | .lpsc = DA8XX_LPSC1_UART2, | |
789a785e | 247 | .gpsc = 1, |
5d36a332 | 248 | .flags = DA850_CLK_ASYNC3, |
e1a8d7e2 SR |
249 | }; |
250 | ||
251 | static struct clk aintc_clk = { | |
252 | .name = "aintc", | |
253 | .parent = &pll0_sysclk4, | |
254 | .lpsc = DA8XX_LPSC0_AINTC, | |
255 | .flags = ALWAYS_ENABLED, | |
256 | }; | |
257 | ||
258 | static struct clk gpio_clk = { | |
259 | .name = "gpio", | |
260 | .parent = &pll0_sysclk4, | |
261 | .lpsc = DA8XX_LPSC1_GPIO, | |
789a785e | 262 | .gpsc = 1, |
e1a8d7e2 SR |
263 | }; |
264 | ||
265 | static struct clk i2c1_clk = { | |
266 | .name = "i2c1", | |
267 | .parent = &pll0_sysclk4, | |
268 | .lpsc = DA8XX_LPSC1_I2C, | |
789a785e | 269 | .gpsc = 1, |
e1a8d7e2 SR |
270 | }; |
271 | ||
272 | static struct clk emif3_clk = { | |
273 | .name = "emif3", | |
274 | .parent = &pll0_sysclk5, | |
275 | .lpsc = DA8XX_LPSC1_EMIF3C, | |
789a785e | 276 | .gpsc = 1, |
e1a8d7e2 | 277 | .flags = ALWAYS_ENABLED, |
e1a8d7e2 SR |
278 | }; |
279 | ||
280 | static struct clk arm_clk = { | |
281 | .name = "arm", | |
282 | .parent = &pll0_sysclk6, | |
283 | .lpsc = DA8XX_LPSC0_ARM, | |
284 | .flags = ALWAYS_ENABLED, | |
683b1e1f SN |
285 | .set_rate = da850_set_armrate, |
286 | .round_rate = da850_round_armrate, | |
e1a8d7e2 SR |
287 | }; |
288 | ||
289 | static struct clk rmii_clk = { | |
290 | .name = "rmii", | |
291 | .parent = &pll0_sysclk7, | |
292 | }; | |
293 | ||
5a4b1315 SR |
294 | static struct clk emac_clk = { |
295 | .name = "emac", | |
296 | .parent = &pll0_sysclk4, | |
297 | .lpsc = DA8XX_LPSC1_CPGMAC, | |
789a785e | 298 | .gpsc = 1, |
5a4b1315 SR |
299 | }; |
300 | ||
491214e1 C |
301 | static struct clk mcasp_clk = { |
302 | .name = "mcasp", | |
303 | .parent = &pll0_sysclk2, | |
304 | .lpsc = DA8XX_LPSC1_McASP0, | |
789a785e | 305 | .gpsc = 1, |
51157ed8 | 306 | .flags = DA850_CLK_ASYNC3, |
491214e1 C |
307 | }; |
308 | ||
5cbdf276 SR |
309 | static struct clk lcdc_clk = { |
310 | .name = "lcdc", | |
311 | .parent = &pll0_sysclk2, | |
312 | .lpsc = DA8XX_LPSC1_LCDC, | |
789a785e | 313 | .gpsc = 1, |
5cbdf276 SR |
314 | }; |
315 | ||
051a6687 JK |
316 | static struct clk mmcsd0_clk = { |
317 | .name = "mmcsd0", | |
700691f2 SR |
318 | .parent = &pll0_sysclk2, |
319 | .lpsc = DA8XX_LPSC0_MMC_SD, | |
320 | }; | |
321 | ||
051a6687 JK |
322 | static struct clk mmcsd1_clk = { |
323 | .name = "mmcsd1", | |
324 | .parent = &pll0_sysclk2, | |
325 | .lpsc = DA850_LPSC1_MMC_SD1, | |
326 | .gpsc = 1, | |
327 | }; | |
328 | ||
38beb929 SR |
329 | static struct clk aemif_clk = { |
330 | .name = "aemif", | |
331 | .parent = &pll0_sysclk3, | |
332 | .lpsc = DA8XX_LPSC0_EMIF25, | |
333 | .flags = ALWAYS_ENABLED, | |
334 | }; | |
335 | ||
5efe330a VR |
336 | static struct clk usb11_clk = { |
337 | .name = "usb11", | |
338 | .parent = &pll0_sysclk4, | |
339 | .lpsc = DA8XX_LPSC1_USB11, | |
340 | .gpsc = 1, | |
341 | }; | |
342 | ||
343 | static struct clk usb20_clk = { | |
344 | .name = "usb20", | |
345 | .parent = &pll0_sysclk2, | |
346 | .lpsc = DA8XX_LPSC1_USB20, | |
347 | .gpsc = 1, | |
348 | }; | |
349 | ||
12d35cf3 MW |
350 | static struct clk spi0_clk = { |
351 | .name = "spi0", | |
352 | .parent = &pll0_sysclk2, | |
353 | .lpsc = DA8XX_LPSC0_SPI0, | |
354 | }; | |
355 | ||
356 | static struct clk spi1_clk = { | |
357 | .name = "spi1", | |
358 | .parent = &pll0_sysclk2, | |
359 | .lpsc = DA8XX_LPSC1_SPI1, | |
360 | .gpsc = 1, | |
361 | .flags = DA850_CLK_ASYNC3, | |
362 | }; | |
363 | ||
154d54a8 MH |
364 | static struct clk vpif_clk = { |
365 | .name = "vpif", | |
366 | .parent = &pll0_sysclk2, | |
367 | .lpsc = DA850_LPSC1_VPIF, | |
368 | .gpsc = 1, | |
369 | }; | |
370 | ||
cbb2c961 SN |
371 | static struct clk sata_clk = { |
372 | .name = "sata", | |
373 | .parent = &pll0_sysclk2, | |
374 | .lpsc = DA850_LPSC1_SATA, | |
375 | .gpsc = 1, | |
376 | .flags = PSC_FORCE, | |
377 | }; | |
378 | ||
09810a85 RT |
379 | static struct clk dsp_clk = { |
380 | .name = "dsp", | |
381 | .parent = &pll0_sysclk1, | |
382 | .domain = DAVINCI_GPSC_DSPDOMAIN, | |
383 | .lpsc = DA8XX_LPSC0_GEM, | |
384 | .flags = PSC_LRST | PSC_FORCE, | |
385 | }; | |
386 | ||
bb170e61 PA |
387 | static struct clk ehrpwm_clk = { |
388 | .name = "ehrpwm", | |
389 | .parent = &pll0_sysclk2, | |
390 | .lpsc = DA8XX_LPSC1_PWM, | |
391 | .gpsc = 1, | |
392 | .flags = DA850_CLK_ASYNC3, | |
393 | }; | |
394 | ||
395 | #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) | |
396 | ||
397 | static void ehrpwm_tblck_enable(struct clk *clk) | |
398 | { | |
399 | u32 val; | |
400 | ||
401 | val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | |
402 | val |= DA8XX_EHRPWM_TBCLKSYNC; | |
403 | writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | |
404 | } | |
405 | ||
406 | static void ehrpwm_tblck_disable(struct clk *clk) | |
407 | { | |
408 | u32 val; | |
409 | ||
410 | val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | |
411 | val &= ~DA8XX_EHRPWM_TBCLKSYNC; | |
412 | writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | |
413 | } | |
414 | ||
415 | static struct clk ehrpwm_tbclk = { | |
416 | .name = "ehrpwm_tbclk", | |
417 | .parent = &ehrpwm_clk, | |
418 | .clk_enable = ehrpwm_tblck_enable, | |
419 | .clk_disable = ehrpwm_tblck_disable, | |
420 | }; | |
421 | ||
422 | static struct clk ecap_clk = { | |
423 | .name = "ecap", | |
424 | .parent = &pll0_sysclk2, | |
425 | .lpsc = DA8XX_LPSC1_ECAP, | |
426 | .gpsc = 1, | |
427 | .flags = DA850_CLK_ASYNC3, | |
428 | }; | |
429 | ||
08aca087 | 430 | static struct clk_lookup da850_clks[] = { |
e1a8d7e2 SR |
431 | CLK(NULL, "ref", &ref_clk), |
432 | CLK(NULL, "pll0", &pll0_clk), | |
433 | CLK(NULL, "pll0_aux", &pll0_aux_clk), | |
09810a85 | 434 | CLK(NULL, "pll0_sysclk1", &pll0_sysclk1), |
e1a8d7e2 SR |
435 | CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), |
436 | CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), | |
437 | CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), | |
438 | CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), | |
439 | CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), | |
440 | CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), | |
441 | CLK(NULL, "pll1", &pll1_clk), | |
442 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
443 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | |
444 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | |
e1a8d7e2 SR |
445 | CLK("i2c_davinci.1", NULL, &i2c0_clk), |
446 | CLK(NULL, "timer0", &timerp64_0_clk), | |
84374812 | 447 | CLK("davinci-wdt", NULL, &timerp64_1_clk), |
e1a8d7e2 SR |
448 | CLK(NULL, "arm_rom", &arm_rom_clk), |
449 | CLK(NULL, "tpcc0", &tpcc0_clk), | |
450 | CLK(NULL, "tptc0", &tptc0_clk), | |
451 | CLK(NULL, "tptc1", &tptc1_clk), | |
452 | CLK(NULL, "tpcc1", &tpcc1_clk), | |
453 | CLK(NULL, "tptc2", &tptc2_clk), | |
8e0d72d2 | 454 | CLK("pruss_uio", "pruss", &pruss_clk), |
19955c3d MP |
455 | CLK("serial8250.0", NULL, &uart0_clk), |
456 | CLK("serial8250.1", NULL, &uart1_clk), | |
457 | CLK("serial8250.2", NULL, &uart2_clk), | |
e1a8d7e2 SR |
458 | CLK(NULL, "aintc", &aintc_clk), |
459 | CLK(NULL, "gpio", &gpio_clk), | |
460 | CLK("i2c_davinci.2", NULL, &i2c1_clk), | |
461 | CLK(NULL, "emif3", &emif3_clk), | |
462 | CLK(NULL, "arm", &arm_clk), | |
463 | CLK(NULL, "rmii", &rmii_clk), | |
5a4b1315 | 464 | CLK("davinci_emac.1", NULL, &emac_clk), |
46c18334 | 465 | CLK("davinci_mdio.0", "fck", &emac_clk), |
491214e1 | 466 | CLK("davinci-mcasp.0", NULL, &mcasp_clk), |
81cec3c7 | 467 | CLK("da8xx_lcdc.0", "fck", &lcdc_clk), |
d7ca4c75 MP |
468 | CLK("da830-mmc.0", NULL, &mmcsd0_clk), |
469 | CLK("da830-mmc.1", NULL, &mmcsd1_clk), | |
38beb929 | 470 | CLK(NULL, "aemif", &aemif_clk), |
5efe330a VR |
471 | CLK(NULL, "usb11", &usb11_clk), |
472 | CLK(NULL, "usb20", &usb20_clk), | |
12d35cf3 MW |
473 | CLK("spi_davinci.0", NULL, &spi0_clk), |
474 | CLK("spi_davinci.1", NULL, &spi1_clk), | |
154d54a8 | 475 | CLK("vpif", NULL, &vpif_clk), |
080c492d | 476 | CLK("ahci_da850", NULL, &sata_clk), |
09810a85 | 477 | CLK("davinci-rproc.0", NULL, &dsp_clk), |
bb170e61 PA |
478 | CLK("ehrpwm", "fck", &ehrpwm_clk), |
479 | CLK("ehrpwm", "tbclk", &ehrpwm_tbclk), | |
480 | CLK("ecap", "fck", &ecap_clk), | |
e1a8d7e2 SR |
481 | CLK(NULL, NULL, NULL), |
482 | }; | |
483 | ||
484 | /* | |
485 | * Device specific mux setup | |
486 | * | |
487 | * soc description mux mode mode mux dbg | |
488 | * reg offset mask mode | |
489 | */ | |
490 | static const struct mux_config da850_pins[] = { | |
491 | #ifdef CONFIG_DAVINCI_MUX | |
492 | /* UART0 function */ | |
493 | MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) | |
494 | MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) | |
495 | MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) | |
496 | MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) | |
497 | /* UART1 function */ | |
498 | MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) | |
499 | MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) | |
500 | /* UART2 function */ | |
501 | MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) | |
502 | MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) | |
503 | /* I2C1 function */ | |
504 | MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) | |
505 | MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) | |
506 | /* I2C0 function */ | |
507 | MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) | |
508 | MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) | |
5a4b1315 SR |
509 | /* EMAC function */ |
510 | MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) | |
511 | MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) | |
512 | MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) | |
513 | MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) | |
514 | MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) | |
515 | MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) | |
516 | MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) | |
517 | MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) | |
518 | MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) | |
519 | MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) | |
520 | MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) | |
521 | MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) | |
522 | MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) | |
523 | MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) | |
524 | MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) | |
53ca5c91 SR |
525 | MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) |
526 | MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) | |
2206771c C |
527 | MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) |
528 | MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) | |
529 | MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) | |
530 | MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) | |
531 | MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) | |
532 | MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) | |
533 | MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) | |
534 | MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) | |
491214e1 C |
535 | /* McASP function */ |
536 | MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) | |
537 | MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) | |
538 | MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) | |
539 | MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) | |
540 | MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) | |
541 | MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) | |
542 | MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) | |
543 | MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) | |
544 | MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) | |
545 | MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) | |
546 | MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) | |
547 | MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) | |
548 | MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) | |
549 | MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) | |
550 | MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) | |
551 | MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) | |
552 | MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) | |
553 | MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) | |
554 | MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) | |
555 | MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) | |
556 | MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) | |
557 | MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) | |
558 | MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) | |
5cbdf276 SR |
559 | /* LCD function */ |
560 | MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) | |
561 | MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) | |
562 | MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) | |
563 | MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) | |
564 | MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) | |
565 | MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) | |
566 | MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) | |
567 | MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) | |
568 | MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) | |
569 | MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) | |
570 | MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) | |
571 | MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) | |
572 | MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) | |
573 | MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) | |
574 | MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) | |
575 | MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) | |
576 | MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) | |
577 | MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) | |
578 | MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) | |
579 | MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) | |
700691f2 SR |
580 | /* MMC/SD0 function */ |
581 | MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) | |
582 | MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) | |
583 | MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) | |
584 | MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) | |
585 | MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) | |
586 | MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) | |
5c4d11b4 IY |
587 | /* MMC/SD1 function */ |
588 | MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false) | |
589 | MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false) | |
590 | MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false) | |
591 | MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false) | |
592 | MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false) | |
593 | MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false) | |
38beb929 SR |
594 | /* EMIF2.5/EMIFA function */ |
595 | MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) | |
596 | MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) | |
597 | MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) | |
598 | MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) | |
599 | MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) | |
600 | MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) | |
601 | MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) | |
602 | MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) | |
603 | MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) | |
604 | MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) | |
605 | MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) | |
606 | MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) | |
607 | MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) | |
608 | MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) | |
7c5ec609 SR |
609 | MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) |
610 | MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) | |
611 | MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) | |
612 | MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) | |
613 | MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) | |
614 | MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) | |
615 | MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) | |
616 | MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) | |
617 | MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) | |
618 | MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) | |
619 | MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) | |
620 | MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) | |
621 | MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) | |
622 | MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) | |
623 | MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) | |
624 | MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) | |
625 | MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) | |
626 | MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) | |
627 | MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) | |
628 | MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) | |
629 | MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) | |
630 | MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) | |
631 | MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) | |
632 | MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) | |
633 | MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) | |
634 | MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) | |
635 | MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) | |
636 | MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) | |
637 | MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) | |
638 | MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) | |
639 | MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) | |
640 | MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) | |
641 | MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) | |
642 | MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) | |
5cbdf276 | 643 | /* GPIO function */ |
fe358d6a | 644 | MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) |
2206771c | 645 | MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) |
7761ef67 | 646 | MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) |
5cbdf276 | 647 | MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) |
fe358d6a VR |
648 | MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) |
649 | MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) | |
700691f2 SR |
650 | MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) |
651 | MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) | |
6836989c IY |
652 | MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false) |
653 | MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) | |
fe358d6a | 654 | MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) |
044ca015 | 655 | MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) |
154d54a8 MH |
656 | /* VPIF Capture */ |
657 | MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) | |
658 | MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) | |
659 | MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) | |
660 | MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) | |
661 | MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) | |
662 | MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) | |
663 | MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) | |
664 | MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) | |
665 | MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) | |
666 | MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) | |
667 | MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) | |
668 | MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) | |
669 | MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) | |
670 | MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) | |
671 | MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) | |
672 | MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) | |
673 | MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) | |
674 | MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) | |
675 | MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) | |
676 | MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) | |
677 | /* VPIF Display */ | |
678 | MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) | |
679 | MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) | |
680 | MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) | |
681 | MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) | |
682 | MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) | |
683 | MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) | |
684 | MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) | |
685 | MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) | |
686 | MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) | |
687 | MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) | |
688 | MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) | |
689 | MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) | |
690 | MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) | |
691 | MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) | |
692 | MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) | |
693 | MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) | |
694 | MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) | |
695 | MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) | |
e1a8d7e2 SR |
696 | #endif |
697 | }; | |
698 | ||
bcad6dc3 | 699 | const short da850_i2c0_pins[] __initconst = { |
e1a8d7e2 SR |
700 | DA850_I2C0_SDA, DA850_I2C0_SCL, |
701 | -1 | |
702 | }; | |
703 | ||
bcad6dc3 | 704 | const short da850_i2c1_pins[] __initconst = { |
e1a8d7e2 SR |
705 | DA850_I2C1_SCL, DA850_I2C1_SDA, |
706 | -1 | |
707 | }; | |
708 | ||
bcad6dc3 | 709 | const short da850_lcdcntl_pins[] __initconst = { |
7761ef67 SR |
710 | DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, |
711 | DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, | |
712 | DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, | |
713 | DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, | |
714 | DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, | |
5cbdf276 SR |
715 | -1 |
716 | }; | |
717 | ||
19c233b7 | 718 | const short da850_vpif_capture_pins[] __initconst = { |
154d54a8 MH |
719 | DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, |
720 | DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, | |
721 | DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, | |
722 | DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, | |
723 | DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, | |
724 | DA850_VPIF_CLKIN3, | |
725 | -1 | |
726 | }; | |
727 | ||
19c233b7 | 728 | const short da850_vpif_display_pins[] __initconst = { |
154d54a8 MH |
729 | DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, |
730 | DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, | |
731 | DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, | |
732 | DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, | |
733 | DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, | |
734 | DA850_VPIF_CLKO3, | |
735 | -1 | |
736 | }; | |
737 | ||
e1a8d7e2 SR |
738 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ |
739 | static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { | |
740 | [IRQ_DA8XX_COMMTX] = 7, | |
741 | [IRQ_DA8XX_COMMRX] = 7, | |
742 | [IRQ_DA8XX_NINT] = 7, | |
743 | [IRQ_DA8XX_EVTOUT0] = 7, | |
744 | [IRQ_DA8XX_EVTOUT1] = 7, | |
745 | [IRQ_DA8XX_EVTOUT2] = 7, | |
746 | [IRQ_DA8XX_EVTOUT3] = 7, | |
747 | [IRQ_DA8XX_EVTOUT4] = 7, | |
748 | [IRQ_DA8XX_EVTOUT5] = 7, | |
749 | [IRQ_DA8XX_EVTOUT6] = 7, | |
e1a8d7e2 SR |
750 | [IRQ_DA8XX_EVTOUT7] = 7, |
751 | [IRQ_DA8XX_CCINT0] = 7, | |
752 | [IRQ_DA8XX_CCERRINT] = 7, | |
753 | [IRQ_DA8XX_TCERRINT0] = 7, | |
754 | [IRQ_DA8XX_AEMIFINT] = 7, | |
755 | [IRQ_DA8XX_I2CINT0] = 7, | |
756 | [IRQ_DA8XX_MMCSDINT0] = 7, | |
757 | [IRQ_DA8XX_MMCSDINT1] = 7, | |
758 | [IRQ_DA8XX_ALLINT0] = 7, | |
759 | [IRQ_DA8XX_RTC] = 7, | |
760 | [IRQ_DA8XX_SPINT0] = 7, | |
761 | [IRQ_DA8XX_TINT12_0] = 7, | |
762 | [IRQ_DA8XX_TINT34_0] = 7, | |
763 | [IRQ_DA8XX_TINT12_1] = 7, | |
764 | [IRQ_DA8XX_TINT34_1] = 7, | |
765 | [IRQ_DA8XX_UARTINT0] = 7, | |
766 | [IRQ_DA8XX_KEYMGRINT] = 7, | |
e1a8d7e2 | 767 | [IRQ_DA850_MPUADDRERR0] = 7, |
e1a8d7e2 SR |
768 | [IRQ_DA8XX_CHIPINT0] = 7, |
769 | [IRQ_DA8XX_CHIPINT1] = 7, | |
770 | [IRQ_DA8XX_CHIPINT2] = 7, | |
771 | [IRQ_DA8XX_CHIPINT3] = 7, | |
772 | [IRQ_DA8XX_TCERRINT1] = 7, | |
773 | [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, | |
774 | [IRQ_DA8XX_C0_RX_PULSE] = 7, | |
775 | [IRQ_DA8XX_C0_TX_PULSE] = 7, | |
776 | [IRQ_DA8XX_C0_MISC_PULSE] = 7, | |
777 | [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, | |
778 | [IRQ_DA8XX_C1_RX_PULSE] = 7, | |
779 | [IRQ_DA8XX_C1_TX_PULSE] = 7, | |
780 | [IRQ_DA8XX_C1_MISC_PULSE] = 7, | |
781 | [IRQ_DA8XX_MEMERR] = 7, | |
782 | [IRQ_DA8XX_GPIO0] = 7, | |
783 | [IRQ_DA8XX_GPIO1] = 7, | |
784 | [IRQ_DA8XX_GPIO2] = 7, | |
785 | [IRQ_DA8XX_GPIO3] = 7, | |
786 | [IRQ_DA8XX_GPIO4] = 7, | |
787 | [IRQ_DA8XX_GPIO5] = 7, | |
788 | [IRQ_DA8XX_GPIO6] = 7, | |
789 | [IRQ_DA8XX_GPIO7] = 7, | |
790 | [IRQ_DA8XX_GPIO8] = 7, | |
791 | [IRQ_DA8XX_I2CINT1] = 7, | |
792 | [IRQ_DA8XX_LCDINT] = 7, | |
793 | [IRQ_DA8XX_UARTINT1] = 7, | |
794 | [IRQ_DA8XX_MCASPINT] = 7, | |
795 | [IRQ_DA8XX_ALLINT1] = 7, | |
796 | [IRQ_DA8XX_SPINT1] = 7, | |
797 | [IRQ_DA8XX_UHPI_INT1] = 7, | |
798 | [IRQ_DA8XX_USB_INT] = 7, | |
799 | [IRQ_DA8XX_IRQN] = 7, | |
800 | [IRQ_DA8XX_RWAKEUP] = 7, | |
801 | [IRQ_DA8XX_UARTINT2] = 7, | |
802 | [IRQ_DA8XX_DFTSSINT] = 7, | |
803 | [IRQ_DA8XX_EHRPWM0] = 7, | |
804 | [IRQ_DA8XX_EHRPWM0TZ] = 7, | |
805 | [IRQ_DA8XX_EHRPWM1] = 7, | |
806 | [IRQ_DA8XX_EHRPWM1TZ] = 7, | |
807 | [IRQ_DA850_SATAINT] = 7, | |
e1a8d7e2 SR |
808 | [IRQ_DA850_TINTALL_2] = 7, |
809 | [IRQ_DA8XX_ECAP0] = 7, | |
810 | [IRQ_DA8XX_ECAP1] = 7, | |
811 | [IRQ_DA8XX_ECAP2] = 7, | |
812 | [IRQ_DA850_MMCSDINT0_1] = 7, | |
813 | [IRQ_DA850_MMCSDINT1_1] = 7, | |
814 | [IRQ_DA850_T12CMPINT0_2] = 7, | |
815 | [IRQ_DA850_T12CMPINT1_2] = 7, | |
816 | [IRQ_DA850_T12CMPINT2_2] = 7, | |
817 | [IRQ_DA850_T12CMPINT3_2] = 7, | |
818 | [IRQ_DA850_T12CMPINT4_2] = 7, | |
819 | [IRQ_DA850_T12CMPINT5_2] = 7, | |
820 | [IRQ_DA850_T12CMPINT6_2] = 7, | |
821 | [IRQ_DA850_T12CMPINT7_2] = 7, | |
822 | [IRQ_DA850_T12CMPINT0_3] = 7, | |
823 | [IRQ_DA850_T12CMPINT1_3] = 7, | |
824 | [IRQ_DA850_T12CMPINT2_3] = 7, | |
825 | [IRQ_DA850_T12CMPINT3_3] = 7, | |
826 | [IRQ_DA850_T12CMPINT4_3] = 7, | |
827 | [IRQ_DA850_T12CMPINT5_3] = 7, | |
828 | [IRQ_DA850_T12CMPINT6_3] = 7, | |
829 | [IRQ_DA850_T12CMPINT7_3] = 7, | |
830 | [IRQ_DA850_RPIINT] = 7, | |
831 | [IRQ_DA850_VPIFINT] = 7, | |
832 | [IRQ_DA850_CCINT1] = 7, | |
833 | [IRQ_DA850_CCERRINT1] = 7, | |
834 | [IRQ_DA850_TCERRINT2] = 7, | |
e1a8d7e2 SR |
835 | [IRQ_DA850_TINTALL_3] = 7, |
836 | [IRQ_DA850_MCBSP0RINT] = 7, | |
837 | [IRQ_DA850_MCBSP0XINT] = 7, | |
838 | [IRQ_DA850_MCBSP1RINT] = 7, | |
839 | [IRQ_DA850_MCBSP1XINT] = 7, | |
840 | [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, | |
841 | }; | |
842 | ||
843 | static struct map_desc da850_io_desc[] = { | |
844 | { | |
845 | .virtual = IO_VIRT, | |
846 | .pfn = __phys_to_pfn(IO_PHYS), | |
847 | .length = IO_SIZE, | |
848 | .type = MT_DEVICE | |
849 | }, | |
850 | { | |
851 | .virtual = DA8XX_CP_INTC_VIRT, | |
852 | .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), | |
853 | .length = DA8XX_CP_INTC_SIZE, | |
854 | .type = MT_DEVICE | |
855 | }, | |
856 | }; | |
857 | ||
e4c822c7 | 858 | static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; |
e1a8d7e2 SR |
859 | |
860 | /* Contents of JTAG ID register used to identify exact cpu type */ | |
861 | static struct davinci_id da850_ids[] = { | |
862 | { | |
863 | .variant = 0x0, | |
864 | .part_no = 0xb7d1, | |
865 | .manufacturer = 0x017, /* 0x02f >> 1 */ | |
866 | .cpu_id = DAVINCI_CPU_ID_DA850, | |
867 | .name = "da850/omap-l138", | |
868 | }, | |
cbb691fb SR |
869 | { |
870 | .variant = 0x1, | |
871 | .part_no = 0xb7d1, | |
872 | .manufacturer = 0x017, /* 0x02f >> 1 */ | |
873 | .cpu_id = DAVINCI_CPU_ID_DA850, | |
874 | .name = "da850/omap-l138/am18x", | |
875 | }, | |
e1a8d7e2 SR |
876 | }; |
877 | ||
878 | static struct davinci_timer_instance da850_timer_instance[4] = { | |
879 | { | |
1bcd38ad | 880 | .base = DA8XX_TIMER64P0_BASE, |
e1a8d7e2 SR |
881 | .bottom_irq = IRQ_DA8XX_TINT12_0, |
882 | .top_irq = IRQ_DA8XX_TINT34_0, | |
883 | }, | |
884 | { | |
1bcd38ad | 885 | .base = DA8XX_TIMER64P1_BASE, |
e1a8d7e2 SR |
886 | .bottom_irq = IRQ_DA8XX_TINT12_1, |
887 | .top_irq = IRQ_DA8XX_TINT34_1, | |
888 | }, | |
889 | { | |
1bcd38ad | 890 | .base = DA850_TIMER64P2_BASE, |
e1a8d7e2 SR |
891 | .bottom_irq = IRQ_DA850_TINT12_2, |
892 | .top_irq = IRQ_DA850_TINT34_2, | |
893 | }, | |
894 | { | |
1bcd38ad | 895 | .base = DA850_TIMER64P3_BASE, |
e1a8d7e2 SR |
896 | .bottom_irq = IRQ_DA850_TINT12_3, |
897 | .top_irq = IRQ_DA850_TINT34_3, | |
898 | }, | |
899 | }; | |
900 | ||
901 | /* | |
902 | * T0_BOT: Timer 0, bottom : Used for clock_event | |
903 | * T0_TOP: Timer 0, top : Used for clocksource | |
904 | * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer | |
905 | */ | |
906 | static struct davinci_timer_info da850_timer_info = { | |
907 | .timers = da850_timer_instance, | |
908 | .clockevent_id = T0_BOT, | |
909 | .clocksource_id = T0_TOP, | |
910 | }; | |
911 | ||
5d36a332 SN |
912 | static void da850_set_async3_src(int pllnum) |
913 | { | |
914 | struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; | |
08aca087 | 915 | struct clk_lookup *c; |
5d36a332 SN |
916 | unsigned int v; |
917 | int ret; | |
918 | ||
08aca087 KH |
919 | for (c = da850_clks; c->clk; c++) { |
920 | clk = c->clk; | |
5d36a332 SN |
921 | if (clk->flags & DA850_CLK_ASYNC3) { |
922 | ret = clk_set_parent(clk, newparent); | |
923 | WARN(ret, "DA850: unable to re-parent clock %s", | |
924 | clk->name); | |
925 | } | |
926 | } | |
927 | ||
d2de0582 | 928 | v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); |
5d36a332 SN |
929 | if (pllnum) |
930 | v |= CFGCHIP3_ASYNC3_CLKSRC; | |
931 | else | |
932 | v &= ~CFGCHIP3_ASYNC3_CLKSRC; | |
d2de0582 | 933 | __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); |
5d36a332 SN |
934 | } |
935 | ||
683b1e1f SN |
936 | #ifdef CONFIG_CPU_FREQ |
937 | /* | |
938 | * Notes: | |
939 | * According to the TRM, minimum PLLM results in maximum power savings. | |
940 | * The OPP definitions below should keep the PLLM as low as possible. | |
941 | * | |
39e14550 | 942 | * The output of the PLLM must be between 300 to 600 MHz. |
683b1e1f SN |
943 | */ |
944 | struct da850_opp { | |
945 | unsigned int freq; /* in KHz */ | |
946 | unsigned int prediv; | |
947 | unsigned int mult; | |
948 | unsigned int postdiv; | |
35f9acd8 SN |
949 | unsigned int cvdd_min; /* in uV */ |
950 | unsigned int cvdd_max; /* in uV */ | |
683b1e1f SN |
951 | }; |
952 | ||
39e14550 SN |
953 | static const struct da850_opp da850_opp_456 = { |
954 | .freq = 456000, | |
955 | .prediv = 1, | |
956 | .mult = 19, | |
957 | .postdiv = 1, | |
958 | .cvdd_min = 1300000, | |
959 | .cvdd_max = 1350000, | |
960 | }; | |
961 | ||
962 | static const struct da850_opp da850_opp_408 = { | |
963 | .freq = 408000, | |
964 | .prediv = 1, | |
965 | .mult = 17, | |
966 | .postdiv = 1, | |
967 | .cvdd_min = 1300000, | |
968 | .cvdd_max = 1350000, | |
969 | }; | |
970 | ||
971 | static const struct da850_opp da850_opp_372 = { | |
972 | .freq = 372000, | |
973 | .prediv = 2, | |
974 | .mult = 31, | |
975 | .postdiv = 1, | |
976 | .cvdd_min = 1200000, | |
977 | .cvdd_max = 1320000, | |
978 | }; | |
979 | ||
683b1e1f SN |
980 | static const struct da850_opp da850_opp_300 = { |
981 | .freq = 300000, | |
982 | .prediv = 1, | |
983 | .mult = 25, | |
984 | .postdiv = 2, | |
6ef62f82 | 985 | .cvdd_min = 1200000, |
35f9acd8 | 986 | .cvdd_max = 1320000, |
683b1e1f SN |
987 | }; |
988 | ||
989 | static const struct da850_opp da850_opp_200 = { | |
990 | .freq = 200000, | |
991 | .prediv = 1, | |
992 | .mult = 25, | |
993 | .postdiv = 3, | |
6ef62f82 | 994 | .cvdd_min = 1100000, |
35f9acd8 | 995 | .cvdd_max = 1160000, |
683b1e1f SN |
996 | }; |
997 | ||
998 | static const struct da850_opp da850_opp_96 = { | |
999 | .freq = 96000, | |
1000 | .prediv = 1, | |
1001 | .mult = 20, | |
1002 | .postdiv = 5, | |
6ef62f82 | 1003 | .cvdd_min = 1000000, |
35f9acd8 | 1004 | .cvdd_max = 1050000, |
683b1e1f SN |
1005 | }; |
1006 | ||
1007 | #define OPP(freq) \ | |
1008 | { \ | |
50701588 | 1009 | .driver_data = (unsigned int) &da850_opp_##freq, \ |
683b1e1f SN |
1010 | .frequency = freq * 1000, \ |
1011 | } | |
1012 | ||
1013 | static struct cpufreq_frequency_table da850_freq_table[] = { | |
39e14550 SN |
1014 | OPP(456), |
1015 | OPP(408), | |
1016 | OPP(372), | |
683b1e1f SN |
1017 | OPP(300), |
1018 | OPP(200), | |
1019 | OPP(96), | |
1020 | { | |
50701588 | 1021 | .driver_data = 0, |
683b1e1f SN |
1022 | .frequency = CPUFREQ_TABLE_END, |
1023 | }, | |
1024 | }; | |
1025 | ||
39e14550 SN |
1026 | #ifdef CONFIG_REGULATOR |
1027 | static int da850_set_voltage(unsigned int index); | |
1028 | static int da850_regulator_init(void); | |
1029 | #endif | |
1030 | ||
1031 | static struct davinci_cpufreq_config cpufreq_info = { | |
1032 | .freq_table = da850_freq_table, | |
1033 | #ifdef CONFIG_REGULATOR | |
1034 | .init = da850_regulator_init, | |
1035 | .set_voltage = da850_set_voltage, | |
1036 | #endif | |
1037 | }; | |
1038 | ||
13d5e27a SN |
1039 | #ifdef CONFIG_REGULATOR |
1040 | static struct regulator *cvdd; | |
1041 | ||
1042 | static int da850_set_voltage(unsigned int index) | |
1043 | { | |
1044 | struct da850_opp *opp; | |
1045 | ||
1046 | if (!cvdd) | |
1047 | return -ENODEV; | |
1048 | ||
50701588 | 1049 | opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; |
13d5e27a SN |
1050 | |
1051 | return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); | |
1052 | } | |
1053 | ||
1054 | static int da850_regulator_init(void) | |
1055 | { | |
1056 | cvdd = regulator_get(NULL, "cvdd"); | |
1057 | if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" | |
1058 | " voltage scaling unsupported\n")) { | |
1059 | return PTR_ERR(cvdd); | |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | #endif | |
1065 | ||
683b1e1f SN |
1066 | static struct platform_device da850_cpufreq_device = { |
1067 | .name = "cpufreq-davinci", | |
1068 | .dev = { | |
1069 | .platform_data = &cpufreq_info, | |
1070 | }, | |
b987c4b2 | 1071 | .id = -1, |
683b1e1f SN |
1072 | }; |
1073 | ||
39e14550 SN |
1074 | unsigned int da850_max_speed = 300000; |
1075 | ||
5063557a | 1076 | int da850_register_cpufreq(char *async_clk) |
683b1e1f | 1077 | { |
39e14550 SN |
1078 | int i; |
1079 | ||
b987c4b2 SN |
1080 | /* cpufreq driver can help keep an "async" clock constant */ |
1081 | if (async_clk) | |
1082 | clk_add_alias("async", da850_cpufreq_device.name, | |
1083 | async_clk, NULL); | |
39e14550 SN |
1084 | for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { |
1085 | if (da850_freq_table[i].frequency <= da850_max_speed) { | |
1086 | cpufreq_info.freq_table = &da850_freq_table[i]; | |
1087 | break; | |
1088 | } | |
1089 | } | |
b987c4b2 | 1090 | |
683b1e1f SN |
1091 | return platform_device_register(&da850_cpufreq_device); |
1092 | } | |
1093 | ||
1094 | static int da850_round_armrate(struct clk *clk, unsigned long rate) | |
1095 | { | |
499f8ad5 | 1096 | int ret = 0, diff; |
683b1e1f | 1097 | unsigned int best = (unsigned int) -1; |
39e14550 | 1098 | struct cpufreq_frequency_table *table = cpufreq_info.freq_table; |
499f8ad5 | 1099 | struct cpufreq_frequency_table *pos; |
683b1e1f SN |
1100 | |
1101 | rate /= 1000; /* convert to kHz */ | |
1102 | ||
499f8ad5 SK |
1103 | cpufreq_for_each_entry(pos, table) { |
1104 | diff = pos->frequency - rate; | |
683b1e1f SN |
1105 | if (diff < 0) |
1106 | diff = -diff; | |
1107 | ||
1108 | if (diff < best) { | |
1109 | best = diff; | |
499f8ad5 | 1110 | ret = pos->frequency; |
683b1e1f SN |
1111 | } |
1112 | } | |
1113 | ||
1114 | return ret * 1000; | |
1115 | } | |
1116 | ||
1117 | static int da850_set_armrate(struct clk *clk, unsigned long index) | |
1118 | { | |
1119 | struct clk *pllclk = &pll0_clk; | |
1120 | ||
1121 | return clk_set_rate(pllclk, index); | |
1122 | } | |
1123 | ||
1124 | static int da850_set_pll0rate(struct clk *clk, unsigned long index) | |
1125 | { | |
1126 | unsigned int prediv, mult, postdiv; | |
1127 | struct da850_opp *opp; | |
1128 | struct pll_data *pll = clk->pll_data; | |
683b1e1f SN |
1129 | int ret; |
1130 | ||
50701588 | 1131 | opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; |
683b1e1f SN |
1132 | prediv = opp->prediv; |
1133 | mult = opp->mult; | |
1134 | postdiv = opp->postdiv; | |
1135 | ||
683b1e1f SN |
1136 | ret = davinci_set_pllrate(pll, prediv, mult, postdiv); |
1137 | if (WARN_ON(ret)) | |
1138 | return ret; | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | #else | |
fca97b33 | 1143 | int __init da850_register_cpufreq(char *async_clk) |
683b1e1f SN |
1144 | { |
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | static int da850_set_armrate(struct clk *clk, unsigned long rate) | |
1149 | { | |
1150 | return -EINVAL; | |
1151 | } | |
1152 | ||
1153 | static int da850_set_pll0rate(struct clk *clk, unsigned long armrate) | |
1154 | { | |
1155 | return -EINVAL; | |
1156 | } | |
1157 | ||
1158 | static int da850_round_armrate(struct clk *clk, unsigned long rate) | |
1159 | { | |
1160 | return clk->rate; | |
1161 | } | |
1162 | #endif | |
1163 | ||
30c766bd | 1164 | int __init da850_register_pm(struct platform_device *pdev) |
044ca015 SN |
1165 | { |
1166 | int ret; | |
1167 | struct davinci_pm_config *pdata = pdev->dev.platform_data; | |
1168 | ||
1169 | ret = davinci_cfg_reg(DA850_RTC_ALARM); | |
1170 | if (ret) | |
1171 | return ret; | |
1172 | ||
1173 | pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr(); | |
1174 | pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); | |
1175 | pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C; | |
1176 | ||
1177 | pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); | |
1178 | if (!pdata->cpupll_reg_base) | |
1179 | return -ENOMEM; | |
1180 | ||
e0c199d0 | 1181 | pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); |
044ca015 SN |
1182 | if (!pdata->ddrpll_reg_base) { |
1183 | ret = -ENOMEM; | |
1184 | goto no_ddrpll_mem; | |
1185 | } | |
1186 | ||
1187 | pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); | |
1188 | if (!pdata->ddrpsc_reg_base) { | |
1189 | ret = -ENOMEM; | |
1190 | goto no_ddrpsc_mem; | |
1191 | } | |
1192 | ||
1193 | return platform_device_register(pdev); | |
1194 | ||
1195 | no_ddrpsc_mem: | |
1196 | iounmap(pdata->ddrpll_reg_base); | |
1197 | no_ddrpll_mem: | |
1198 | iounmap(pdata->cpupll_reg_base); | |
1199 | return ret; | |
1200 | } | |
35f9acd8 | 1201 | |
154d54a8 MH |
1202 | /* VPIF resource, platform data */ |
1203 | static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); | |
1204 | ||
1205 | static struct resource da850_vpif_resource[] = { | |
1206 | { | |
1207 | .start = DA8XX_VPIF_BASE, | |
1208 | .end = DA8XX_VPIF_BASE + 0xfff, | |
1209 | .flags = IORESOURCE_MEM, | |
1210 | } | |
1211 | }; | |
1212 | ||
1213 | static struct platform_device da850_vpif_dev = { | |
1214 | .name = "vpif", | |
1215 | .id = -1, | |
1216 | .dev = { | |
1217 | .dma_mask = &da850_vpif_dma_mask, | |
1218 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1219 | }, | |
1220 | .resource = da850_vpif_resource, | |
1221 | .num_resources = ARRAY_SIZE(da850_vpif_resource), | |
1222 | }; | |
1223 | ||
1224 | static struct resource da850_vpif_display_resource[] = { | |
1225 | { | |
1226 | .start = IRQ_DA850_VPIFINT, | |
1227 | .end = IRQ_DA850_VPIFINT, | |
1228 | .flags = IORESOURCE_IRQ, | |
1229 | }, | |
1230 | }; | |
1231 | ||
1232 | static struct platform_device da850_vpif_display_dev = { | |
1233 | .name = "vpif_display", | |
1234 | .id = -1, | |
1235 | .dev = { | |
1236 | .dma_mask = &da850_vpif_dma_mask, | |
1237 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1238 | }, | |
1239 | .resource = da850_vpif_display_resource, | |
1240 | .num_resources = ARRAY_SIZE(da850_vpif_display_resource), | |
1241 | }; | |
1242 | ||
1243 | static struct resource da850_vpif_capture_resource[] = { | |
1244 | { | |
1245 | .start = IRQ_DA850_VPIFINT, | |
1246 | .end = IRQ_DA850_VPIFINT, | |
1247 | .flags = IORESOURCE_IRQ, | |
1248 | }, | |
1249 | { | |
1250 | .start = IRQ_DA850_VPIFINT, | |
1251 | .end = IRQ_DA850_VPIFINT, | |
1252 | .flags = IORESOURCE_IRQ, | |
1253 | }, | |
1254 | }; | |
1255 | ||
1256 | static struct platform_device da850_vpif_capture_dev = { | |
1257 | .name = "vpif_capture", | |
1258 | .id = -1, | |
1259 | .dev = { | |
1260 | .dma_mask = &da850_vpif_dma_mask, | |
1261 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1262 | }, | |
1263 | .resource = da850_vpif_capture_resource, | |
1264 | .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), | |
1265 | }; | |
1266 | ||
1267 | int __init da850_register_vpif(void) | |
1268 | { | |
1269 | return platform_device_register(&da850_vpif_dev); | |
1270 | } | |
1271 | ||
1272 | int __init da850_register_vpif_display(struct vpif_display_config | |
1273 | *display_config) | |
1274 | { | |
1275 | da850_vpif_display_dev.dev.platform_data = display_config; | |
1276 | return platform_device_register(&da850_vpif_display_dev); | |
1277 | } | |
1278 | ||
1279 | int __init da850_register_vpif_capture(struct vpif_capture_config | |
1280 | *capture_config) | |
1281 | { | |
1282 | da850_vpif_capture_dev.dev.platform_data = capture_config; | |
1283 | return platform_device_register(&da850_vpif_capture_dev); | |
1284 | } | |
1285 | ||
f606d38d KS |
1286 | static struct davinci_gpio_platform_data da850_gpio_platform_data = { |
1287 | .ngpio = 144, | |
f606d38d KS |
1288 | }; |
1289 | ||
1290 | int __init da850_register_gpio(void) | |
1291 | { | |
1292 | return da8xx_register_gpio(&da850_gpio_platform_data); | |
1293 | } | |
1294 | ||
e1a8d7e2 SR |
1295 | static struct davinci_soc_info davinci_soc_info_da850 = { |
1296 | .io_desc = da850_io_desc, | |
1297 | .io_desc_num = ARRAY_SIZE(da850_io_desc), | |
3347db83 | 1298 | .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, |
e1a8d7e2 SR |
1299 | .ids = da850_ids, |
1300 | .ids_num = ARRAY_SIZE(da850_ids), | |
1301 | .cpu_clks = da850_clks, | |
1302 | .psc_bases = da850_psc_bases, | |
1303 | .psc_bases_num = ARRAY_SIZE(da850_psc_bases), | |
779b0d53 | 1304 | .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, |
e1a8d7e2 SR |
1305 | .pinmux_pins = da850_pins, |
1306 | .pinmux_pins_num = ARRAY_SIZE(da850_pins), | |
bd808947 | 1307 | .intc_base = DA8XX_CP_INTC_BASE, |
e1a8d7e2 SR |
1308 | .intc_type = DAVINCI_INTC_TYPE_CP_INTC, |
1309 | .intc_irq_prios = da850_default_priorities, | |
1310 | .intc_irq_num = DA850_N_CP_INTC_IRQ, | |
1311 | .timer_info = &da850_timer_info, | |
e1a8d7e2 | 1312 | .emac_pdata = &da8xx_emac_pdata, |
c94472d4 SG |
1313 | .sram_dma = DA8XX_SHARED_RAM_BASE, |
1314 | .sram_len = SZ_128K, | |
e1a8d7e2 SR |
1315 | }; |
1316 | ||
1317 | void __init da850_init(void) | |
1318 | { | |
7aad472b SN |
1319 | unsigned int v; |
1320 | ||
bcd6a1c6 CC |
1321 | davinci_common_init(&davinci_soc_info_da850); |
1322 | ||
d2de0582 SN |
1323 | da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); |
1324 | if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module")) | |
1325 | return; | |
1326 | ||
1327 | da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); | |
1328 | if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) | |
6a28adef SN |
1329 | return; |
1330 | ||
5d36a332 SN |
1331 | /* |
1332 | * Move the clock source of Async3 domain to PLL1 SYSCLK2. | |
1333 | * This helps keeping the peripherals on this domain insulated | |
1334 | * from CPU frequency changes caused by DVFS. The firmware sets | |
1335 | * both PLL0 and PLL1 to the same frequency so, there should not | |
25985edc | 1336 | * be any noticeable change even in non-DVFS use cases. |
5d36a332 SN |
1337 | */ |
1338 | da850_set_async3_src(1); | |
7aad472b SN |
1339 | |
1340 | /* Unlock writing to PLL0 registers */ | |
1341 | v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); | |
1342 | v &= ~CFGCHIP0_PLL_MASTER_LOCK; | |
1343 | __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); | |
1344 | ||
1345 | /* Unlock writing to PLL1 registers */ | |
1346 | v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); | |
1347 | v &= ~CFGCHIP3_PLL1_MASTER_LOCK; | |
1348 | __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); | |
e1a8d7e2 | 1349 | } |