Commit | Line | Data |
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a6c0f6ec SN |
1 | /* |
2 | * CPU idle for DaVinci SoCs | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/ | |
5 | * | |
6 | * Derived from Marvell Kirkwood CPU idle code | |
7 | * (arch/arm/mach-kirkwood/cpuidle.c) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/cpuidle.h> | |
18 | #include <linux/io.h> | |
dc28094b | 19 | #include <linux/export.h> |
a6c0f6ec | 20 | #include <asm/proc-fns.h> |
19976c2a | 21 | #include <asm/cpuidle.h> |
a6c0f6ec SN |
22 | |
23 | #include <mach/cpuidle.h> | |
0020afb3 | 24 | #include <mach/ddr2.h> |
a6c0f6ec SN |
25 | |
26 | #define DAVINCI_CPUIDLE_MAX_STATES 2 | |
27 | ||
a6c0f6ec | 28 | static void __iomem *ddr2_reg_base; |
5af4a21c | 29 | static bool ddr2_pdown; |
a6c0f6ec | 30 | |
a6c0f6ec SN |
31 | static void davinci_save_ddr_power(int enter, bool pdown) |
32 | { | |
33 | u32 val; | |
34 | ||
35 | val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); | |
36 | ||
37 | if (enter) { | |
38 | if (pdown) | |
39 | val |= DDR2_SRPD_BIT; | |
40 | else | |
41 | val &= ~DDR2_SRPD_BIT; | |
42 | val |= DDR2_LPMODEN_BIT; | |
43 | } else { | |
44 | val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); | |
45 | } | |
46 | ||
47 | __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); | |
48 | } | |
49 | ||
8d60143a DL |
50 | /* Actual code that puts the SoC in different idle states */ |
51 | static int davinci_enter_idle(struct cpuidle_device *dev, | |
c062d443 | 52 | struct cpuidle_driver *drv, int index) |
8d60143a | 53 | { |
36ce8d4f | 54 | davinci_save_ddr_power(1, ddr2_pdown); |
c062d443 | 55 | cpu_do_idle(); |
36ce8d4f | 56 | davinci_save_ddr_power(0, ddr2_pdown); |
8d60143a DL |
57 | |
58 | return index; | |
59 | } | |
60 | ||
61 | static struct cpuidle_driver davinci_idle_driver = { | |
62 | .name = "cpuidle-davinci", | |
63 | .owner = THIS_MODULE, | |
8d60143a DL |
64 | .states[0] = ARM_CPUIDLE_WFI_STATE, |
65 | .states[1] = { | |
66 | .enter = davinci_enter_idle, | |
67 | .exit_latency = 10, | |
68 | .target_residency = 100000, | |
69 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
70 | .name = "DDR SR", | |
71 | .desc = "WFI and DDR Self Refresh", | |
72 | }, | |
73 | .state_count = DAVINCI_CPUIDLE_MAX_STATES, | |
74 | }; | |
75 | ||
a6c0f6ec SN |
76 | static int __init davinci_cpuidle_probe(struct platform_device *pdev) |
77 | { | |
a6c0f6ec | 78 | struct davinci_cpuidle_config *pdata = pdev->dev.platform_data; |
a6c0f6ec | 79 | |
a6c0f6ec SN |
80 | if (!pdata) { |
81 | dev_err(&pdev->dev, "cannot get platform data\n"); | |
82 | return -ENOENT; | |
83 | } | |
84 | ||
948c66df | 85 | ddr2_reg_base = pdata->ddr2_ctlr_base; |
a6c0f6ec | 86 | |
5af4a21c | 87 | ddr2_pdown = pdata->ddr2_pdown; |
a6c0f6ec | 88 | |
3aec0345 | 89 | return cpuidle_register(&davinci_idle_driver, NULL); |
a6c0f6ec SN |
90 | } |
91 | ||
92 | static struct platform_driver davinci_cpuidle_driver = { | |
93 | .driver = { | |
94 | .name = "cpuidle-davinci", | |
95 | .owner = THIS_MODULE, | |
96 | }, | |
97 | }; | |
98 | ||
99 | static int __init davinci_cpuidle_init(void) | |
100 | { | |
101 | return platform_driver_probe(&davinci_cpuidle_driver, | |
102 | davinci_cpuidle_probe); | |
103 | } | |
104 | device_initcall(davinci_cpuidle_init); | |
105 |