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0521444d SS |
1 | /* |
2 | * TI Common Platform Interrupt Controller (cp_intc) driver | |
3 | * | |
4 | * Author: Steve Chen <schen@mvista.com> | |
5 | * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com> | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
0521444d SS |
13 | #include <linux/irq.h> |
14 | #include <linux/io.h> | |
15 | ||
16 | #include <mach/cp_intc.h> | |
17 | ||
18 | static void __iomem *cp_intc_base; | |
19 | ||
20 | static inline unsigned int cp_intc_read(unsigned offset) | |
21 | { | |
22 | return __raw_readl(cp_intc_base + offset); | |
23 | } | |
24 | ||
25 | static inline void cp_intc_write(unsigned long value, unsigned offset) | |
26 | { | |
27 | __raw_writel(value, cp_intc_base + offset); | |
28 | } | |
29 | ||
30 | static void cp_intc_ack_irq(unsigned int irq) | |
31 | { | |
32 | cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR); | |
33 | } | |
34 | ||
35 | /* Disable interrupt */ | |
36 | static void cp_intc_mask_irq(unsigned int irq) | |
37 | { | |
38 | /* XXX don't know why we need to disable nIRQ here... */ | |
39 | cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); | |
40 | cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR); | |
41 | cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); | |
42 | } | |
43 | ||
44 | /* Enable interrupt */ | |
45 | static void cp_intc_unmask_irq(unsigned int irq) | |
46 | { | |
47 | cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET); | |
48 | } | |
49 | ||
50 | static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type) | |
51 | { | |
52 | unsigned reg = BIT_WORD(irq); | |
53 | unsigned mask = BIT_MASK(irq); | |
54 | unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); | |
55 | unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); | |
56 | ||
57 | switch (flow_type) { | |
58 | case IRQ_TYPE_EDGE_RISING: | |
59 | polarity |= mask; | |
60 | type |= mask; | |
61 | break; | |
62 | case IRQ_TYPE_EDGE_FALLING: | |
63 | polarity &= ~mask; | |
64 | type |= mask; | |
65 | break; | |
66 | case IRQ_TYPE_LEVEL_HIGH: | |
67 | polarity |= mask; | |
68 | type &= ~mask; | |
69 | break; | |
70 | case IRQ_TYPE_LEVEL_LOW: | |
71 | polarity &= ~mask; | |
72 | type &= ~mask; | |
73 | break; | |
74 | default: | |
75 | return -EINVAL; | |
76 | } | |
77 | ||
78 | cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg)); | |
79 | cp_intc_write(type, CP_INTC_SYS_TYPE(reg)); | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
2d3f5950 SN |
84 | /* |
85 | * Faking this allows us to to work with suspend functions of | |
86 | * generic drivers which call {enable|disable}_irq_wake for | |
87 | * wake up interrupt sources (eg RTC on DA850). | |
88 | */ | |
89 | static int cp_intc_set_wake(unsigned int irq, unsigned int on) | |
90 | { | |
91 | return 0; | |
92 | } | |
93 | ||
0521444d SS |
94 | static struct irq_chip cp_intc_irq_chip = { |
95 | .name = "cp_intc", | |
96 | .ack = cp_intc_ack_irq, | |
97 | .mask = cp_intc_mask_irq, | |
98 | .unmask = cp_intc_unmask_irq, | |
99 | .set_type = cp_intc_set_irq_type, | |
2d3f5950 | 100 | .set_wake = cp_intc_set_wake, |
0521444d SS |
101 | }; |
102 | ||
103 | void __init cp_intc_init(void __iomem *base, unsigned short num_irq, | |
104 | u8 *irq_prio) | |
105 | { | |
106 | unsigned num_reg = BITS_TO_LONGS(num_irq); | |
107 | int i; | |
108 | ||
109 | cp_intc_base = base; | |
110 | ||
111 | cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); | |
112 | ||
113 | /* Disable all host interrupts */ | |
114 | cp_intc_write(0, CP_INTC_HOST_ENABLE(0)); | |
115 | ||
116 | /* Disable system interrupts */ | |
117 | for (i = 0; i < num_reg; i++) | |
118 | cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i)); | |
119 | ||
120 | /* Set to normal mode, no nesting, no priority hold */ | |
121 | cp_intc_write(0, CP_INTC_CTRL); | |
122 | cp_intc_write(0, CP_INTC_HOST_CTRL); | |
123 | ||
124 | /* Clear system interrupt status */ | |
125 | for (i = 0; i < num_reg; i++) | |
126 | cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i)); | |
127 | ||
128 | /* Enable nIRQ (what about nFIQ?) */ | |
129 | cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); | |
130 | ||
131 | /* | |
132 | * Priority is determined by host channel: lower channel number has | |
133 | * higher priority i.e. channel 0 has highest priority and channel 31 | |
134 | * had the lowest priority. | |
135 | */ | |
136 | num_reg = (num_irq + 3) >> 2; /* 4 channels per register */ | |
137 | if (irq_prio) { | |
138 | unsigned j, k; | |
139 | u32 val; | |
140 | ||
141 | for (k = i = 0; i < num_reg; i++) { | |
142 | for (val = j = 0; j < 4; j++, k++) { | |
143 | val >>= 8; | |
144 | if (k < num_irq) | |
145 | val |= irq_prio[k] << 24; | |
146 | } | |
147 | ||
148 | cp_intc_write(val, CP_INTC_CHAN_MAP(i)); | |
149 | } | |
150 | } else { | |
151 | /* | |
152 | * Default everything to channel 15 if priority not specified. | |
153 | * Note that channel 0-1 are mapped to nFIQ and channels 2-31 | |
154 | * are mapped to nIRQ. | |
155 | */ | |
156 | for (i = 0; i < num_reg; i++) | |
157 | cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); | |
158 | } | |
159 | ||
160 | /* Set up genirq dispatching for cp_intc */ | |
161 | for (i = 0; i < num_irq; i++) { | |
162 | set_irq_chip(i, &cp_intc_irq_chip); | |
163 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | |
164 | set_irq_handler(i, handle_edge_irq); | |
165 | } | |
166 | ||
167 | /* Enable global interrupt */ | |
168 | cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); | |
169 | } |