[linux-2.6-block.git] / arch / arm / mach-davinci / cp_intc.c

/*
 * TI Common Platform Interrupt Controller (cp_intc) driver
 *
 * Author: Steve Chen <schen@mvista.com>
 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/export.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <mach/common.h>
#include <mach/cp_intc.h>

static inline unsigned int cp_intc_read(unsigned offset)
{
	return __raw_readl(davinci_intc_base + offset);
}

static inline void cp_intc_write(unsigned long value, unsigned offset)
{
	__raw_writel(value, davinci_intc_base + offset);
}

static void cp_intc_ack_irq(struct irq_data *d)
{
	cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
}

/* Disable interrupt */
static void cp_intc_mask_irq(struct irq_data *d)
{
	/* XXX don't know why we need to disable nIRQ here... */
	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
}

/* Enable interrupt */
static void cp_intc_unmask_irq(struct irq_data *d)
{
	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
}

static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
	unsigned reg		= BIT_WORD(d->hwirq);
	unsigned mask		= BIT_MASK(d->hwirq);
	unsigned polarity	= cp_intc_read(CP_INTC_SYS_POLARITY(reg));
	unsigned type		= cp_intc_read(CP_INTC_SYS_TYPE(reg));

	switch (flow_type) {
	case IRQ_TYPE_EDGE_RISING:
		polarity |= mask;
		type |= mask;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		polarity &= ~mask;
		type |= mask;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		polarity |= mask;
		type &= ~mask;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		polarity &= ~mask;
		type &= ~mask;
		break;
	default:
		return -EINVAL;
	}

	cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
	cp_intc_write(type, CP_INTC_SYS_TYPE(reg));

	return 0;
}

/*
 * Faking this allows us to to work with suspend functions of
 * generic drivers which call {enable|disable}_irq_wake for
 * wake up interrupt sources (eg RTC on DA850).
 */
static int cp_intc_set_wake(struct irq_data *d, unsigned int on)
{
	return 0;
}

static struct irq_chip cp_intc_irq_chip = {
	.name		= "cp_intc",
	.irq_ack	= cp_intc_ack_irq,
	.irq_mask	= cp_intc_mask_irq,
	.irq_unmask	= cp_intc_unmask_irq,
	.irq_set_type	= cp_intc_set_irq_type,
	.irq_set_wake	= cp_intc_set_wake,
};

static struct irq_domain *cp_intc_domain;

static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);

	irq_set_chip(virq, &cp_intc_irq_chip);
	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
	irq_set_handler(virq, handle_edge_irq);
	return 0;
}

static const struct irq_domain_ops cp_intc_host_ops = {
	.map = cp_intc_host_map,
	.xlate = irq_domain_xlate_onetwocell,
};

int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
{
	u32 num_irq		= davinci_soc_info.intc_irq_num;
	u8 *irq_prio		= davinci_soc_info.intc_irq_prios;
	u32 *host_map		= davinci_soc_info.intc_host_map;
	unsigned num_reg	= BITS_TO_LONGS(num_irq);
	int i, irq_base;

	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
	if (node) {
		davinci_intc_base = of_iomap(node, 0);
		if (of_property_read_u32(node, "ti,intc-size", &num_irq))
			pr_warn("unable to get intc-size, default to %d\n",
				num_irq);
	} else {
		davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
	}
	if (WARN_ON(!davinci_intc_base))
		return -EINVAL;

	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);

	/* Disable all host interrupts */
	cp_intc_write(0, CP_INTC_HOST_ENABLE(0));

	/* Disable system interrupts */
	for (i = 0; i < num_reg; i++)
		cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));

	/* Set to normal mode, no nesting, no priority hold */
	cp_intc_write(0, CP_INTC_CTRL);
	cp_intc_write(0, CP_INTC_HOST_CTRL);

	/* Clear system interrupt status */
	for (i = 0; i < num_reg; i++)
		cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));

	/* Enable nIRQ (what about nFIQ?) */
	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);

	/*
	 * Priority is determined by host channel: lower channel number has
	 * higher priority i.e. channel 0 has highest priority and channel 31
	 * had the lowest priority.
	 */
	num_reg = (num_irq + 3) >> 2;	/* 4 channels per register */
	if (irq_prio) {
		unsigned j, k;
		u32 val;

		for (k = i = 0; i < num_reg; i++) {
			for (val = j = 0; j < 4; j++, k++) {
				val >>= 8;
				if (k < num_irq)
					val |= irq_prio[k] << 24;
			}

			cp_intc_write(val, CP_INTC_CHAN_MAP(i));
		}
	} else	{
		/*
		 * Default everything to channel 15 if priority not specified.
		 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
		 * are mapped to nIRQ.
		 */
		for (i = 0; i < num_reg; i++)
			cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
	}

	if (host_map)
		for (i = 0; host_map[i] != -1; i++)
			cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));

	irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	/* create a legacy host */
	cp_intc_domain = irq_domain_add_legacy(node, num_irq,
					irq_base, 0, &cp_intc_host_ops, NULL);

	if (!cp_intc_domain) {
		pr_err("cp_intc: failed to allocate irq host!\n");
		return -EINVAL;
	}

	/* Enable global interrupt */
	cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);

	return 0;
}

void __init cp_intc_init(void)
{
	cp_intc_of_init(NULL, NULL);
}
Commit	Line	Data
0521444d SS	1	/*
	2	* TI Common Platform Interrupt Controller (cp_intc) driver
	3	*
	4	* Author: Steve Chen <schen@mvista.com>
	5	* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
07caba96	12	#include <linux/export.h>
0521444d	13	#include <linux/init.h>
0521444d	14	#include <linux/irq.h>
07caba96	15	#include <linux/irqdomain.h>
0521444d	16	#include <linux/io.h>
961e657f HS	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of_irq.h>
0521444d	20
bd808947	21	#include <mach/common.h>
0521444d SS	22	#include <mach/cp_intc.h>
0521444d SS	23
0521444d SS	24	static inline unsigned int cp_intc_read(unsigned offset)
0521444d SS	25	{
bd808947	26	return __raw_readl(davinci_intc_base + offset);
0521444d SS	27	}
	28
	29	static inline void cp_intc_write(unsigned long value, unsigned offset)
	30	{
bd808947	31	__raw_writel(value, davinci_intc_base + offset);
0521444d SS	32	}
0521444d SS	33
23265442	34	static void cp_intc_ack_irq(struct irq_data *d)
0521444d	35	{
07caba96	36	cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
0521444d SS	37	}
	38
	39	/* Disable interrupt */
23265442	40	static void cp_intc_mask_irq(struct irq_data *d)
0521444d SS	41	{
	42	/* XXX don't know why we need to disable nIRQ here... */
	43	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
07caba96	44	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
0521444d SS	45	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
	46	}
	47
	48	/* Enable interrupt */
23265442	49	static void cp_intc_unmask_irq(struct irq_data *d)
0521444d	50	{
07caba96	51	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
0521444d SS	52	}
0521444d SS	53
23265442	54	static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
0521444d	55	{
07caba96 HS	56	unsigned reg = BIT_WORD(d->hwirq);
07caba96 HS	57	unsigned mask = BIT_MASK(d->hwirq);
0521444d SS	58	unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
	59	unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
	60
	61	switch (flow_type) {
	62	case IRQ_TYPE_EDGE_RISING:
	63	polarity \|= mask;
	64	type \|= mask;
	65	break;
	66	case IRQ_TYPE_EDGE_FALLING:
	67	polarity &= ~mask;
	68	type \|= mask;
	69	break;
	70	case IRQ_TYPE_LEVEL_HIGH:
	71	polarity \|= mask;
	72	type &= ~mask;
	73	break;
	74	case IRQ_TYPE_LEVEL_LOW:
	75	polarity &= ~mask;
	76	type &= ~mask;
	77	break;
	78	default:
	79	return -EINVAL;
	80	}
	81
	82	cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
	83	cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
	84
	85	return 0;
	86	}
	87
2d3f5950 SN	88	/*
	89	* Faking this allows us to to work with suspend functions of
	90	* generic drivers which call {enable\|disable}_irq_wake for
	91	* wake up interrupt sources (eg RTC on DA850).
	92	*/
23265442	93	static int cp_intc_set_wake(struct irq_data *d, unsigned int on)
2d3f5950 SN	94	{
	95	return 0;
	96	}
	97
0521444d SS	98	static struct irq_chip cp_intc_irq_chip = {
0521444d SS	99	.name = "cp_intc",
23265442 LB	100	.irq_ack = cp_intc_ack_irq,
	101	.irq_mask = cp_intc_mask_irq,
	102	.irq_unmask = cp_intc_unmask_irq,
	103	.irq_set_type = cp_intc_set_irq_type,
	104	.irq_set_wake = cp_intc_set_wake,
0521444d SS	105	};
0521444d SS	106
07caba96 HS	107	static struct irq_domain *cp_intc_domain;
	108
	109	static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
	110	irq_hw_number_t hw)
	111	{
	112	pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
	113
	114	irq_set_chip(virq, &cp_intc_irq_chip);
	115	set_irq_flags(virq, IRQF_VALID \| IRQF_PROBE);
	116	irq_set_handler(virq, handle_edge_irq);
	117	return 0;
	118	}
	119
	120	static const struct irq_domain_ops cp_intc_host_ops = {
	121	.map = cp_intc_host_map,
	122	.xlate = irq_domain_xlate_onetwocell,
	123	};
	124
961e657f	125	int __init cp_intc_of_init(struct device_node node, struct device_node parent)
0521444d	126	{
07caba96	127	u32 num_irq = davinci_soc_info.intc_irq_num;
bd808947 CC	128	u8 *irq_prio = davinci_soc_info.intc_irq_prios;
bd808947 CC	129	u32 *host_map = davinci_soc_info.intc_host_map;
0521444d	130	unsigned num_reg = BITS_TO_LONGS(num_irq);
07caba96	131	int i, irq_base;
0521444d	132
bd808947	133	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
961e657f HS	134	if (node) {
	135	davinci_intc_base = of_iomap(node, 0);
	136	if (of_property_read_u32(node, "ti,intc-size", &num_irq))
	137	pr_warn("unable to get intc-size, default to %d\n",
	138	num_irq);
	139	} else {
	140	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
	141	}
bd808947	142	if (WARN_ON(!davinci_intc_base))
07caba96	143	return -EINVAL;
0521444d SS	144
	145	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
	146
	147	/* Disable all host interrupts */
	148	cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
	149
	150	/* Disable system interrupts */
	151	for (i = 0; i < num_reg; i++)
	152	cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
	153
	154	/* Set to normal mode, no nesting, no priority hold */
	155	cp_intc_write(0, CP_INTC_CTRL);
	156	cp_intc_write(0, CP_INTC_HOST_CTRL);
	157
	158	/* Clear system interrupt status */
	159	for (i = 0; i < num_reg; i++)
	160	cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
	161
	162	/* Enable nIRQ (what about nFIQ?) */
	163	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
	164
	165	/*
	166	* Priority is determined by host channel: lower channel number has
	167	* higher priority i.e. channel 0 has highest priority and channel 31
	168	* had the lowest priority.
	169	*/
	170	num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
	171	if (irq_prio) {
	172	unsigned j, k;
	173	u32 val;
	174
	175	for (k = i = 0; i < num_reg; i++) {
	176	for (val = j = 0; j < 4; j++, k++) {
	177	val >>= 8;
	178	if (k < num_irq)
	179	val \|= irq_prio[k] << 24;
	180	}
	181
	182	cp_intc_write(val, CP_INTC_CHAN_MAP(i));
	183	}
	184	} else {
	185	/*
	186	* Default everything to channel 15 if priority not specified.
	187	* Note that channel 0-1 are mapped to nFIQ and channels 2-31
	188	* are mapped to nIRQ.
	189	*/
	190	for (i = 0; i < num_reg; i++)
	191	cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
	192	}
	193
449ef7f6 CC	194	if (host_map)
	195	for (i = 0; host_map[i] != -1; i++)
	196	cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
	197
07caba96 HS	198	irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
	199	if (irq_base < 0) {
	200	pr_warn("Couldn't allocate IRQ numbers\n");
	201	irq_base = 0;
	202	}
	203
	204	/* create a legacy host */
	205	cp_intc_domain = irq_domain_add_legacy(node, num_irq,
	206	irq_base, 0, &cp_intc_host_ops, NULL);
	207
	208	if (!cp_intc_domain) {
	209	pr_err("cp_intc: failed to allocate irq host!\n");
	210	return -EINVAL;
0521444d SS	211	}
	212
	213	/* Enable global interrupt */
	214	cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
07caba96 HS	215
	216	return 0;
	217	}
	218
	219	void __init cp_intc_init(void)
	220	{
961e657f	221	cp_intc_of_init(NULL, NULL);
0521444d	222	}