Commit | Line | Data |
---|---|---|
3e062b07 VB |
1 | /* |
2 | * TI DaVinci clock definitions | |
3 | * | |
c5b736d0 KH |
4 | * Copyright (C) 2006-2007 Texas Instruments. |
5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
3e062b07 VB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef __ARCH_ARM_DAVINCI_CLOCK_H | |
13 | #define __ARCH_ARM_DAVINCI_CLOCK_H | |
14 | ||
c5b736d0 KH |
15 | #define DAVINCI_PLL1_BASE 0x01c40800 |
16 | #define DAVINCI_PLL2_BASE 0x01c40c00 | |
17 | #define MAX_PLL 2 | |
18 | ||
19 | /* PLL/Reset register offsets */ | |
20 | #define PLLCTL 0x100 | |
21 | #define PLLCTL_PLLEN BIT(0) | |
d6a61563 SN |
22 | #define PLLCTL_PLLPWRDN BIT(1) |
23 | #define PLLCTL_PLLRST BIT(3) | |
24 | #define PLLCTL_PLLDIS BIT(4) | |
25 | #define PLLCTL_PLLENSRC BIT(5) | |
c5b736d0 KH |
26 | #define PLLCTL_CLKMODE BIT(8) |
27 | ||
28 | #define PLLM 0x110 | |
29 | #define PLLM_PLLM_MASK 0xff | |
30 | ||
31 | #define PREDIV 0x114 | |
32 | #define PLLDIV1 0x118 | |
33 | #define PLLDIV2 0x11c | |
34 | #define PLLDIV3 0x120 | |
35 | #define POSTDIV 0x128 | |
36 | #define BPDIV 0x12c | |
37 | #define PLLCMD 0x138 | |
38 | #define PLLSTAT 0x13c | |
39 | #define PLLALNCTL 0x140 | |
40 | #define PLLDCHANGE 0x144 | |
41 | #define PLLCKEN 0x148 | |
42 | #define PLLCKSTAT 0x14c | |
43 | #define PLLSYSTAT 0x150 | |
44 | #define PLLDIV4 0x160 | |
45 | #define PLLDIV5 0x164 | |
46 | #define PLLDIV6 0x168 | |
47 | #define PLLDIV7 0x16c | |
48 | #define PLLDIV8 0x170 | |
49 | #define PLLDIV9 0x174 | |
50 | #define PLLDIV_EN BIT(15) | |
51 | #define PLLDIV_RATIO_MASK 0x1f | |
52 | ||
9a219a9e SN |
53 | /* |
54 | * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN | |
55 | * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us | |
56 | * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input | |
57 | * is ~25MHz. Units are micro seconds. | |
58 | */ | |
59 | #define PLL_BYPASS_TIME 1 | |
60 | /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ | |
61 | #define PLL_RESET_TIME 1 | |
62 | /* | |
63 | * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 | |
64 | * Units are micro seconds. | |
65 | */ | |
66 | #define PLL_LOCK_TIME 20 | |
67 | ||
e2da3aaa SN |
68 | #ifndef __ASSEMBLER__ |
69 | ||
70 | #include <linux/list.h> | |
71 | #include <asm/clkdev.h> | |
72 | ||
c5b736d0 KH |
73 | struct pll_data { |
74 | u32 phys_base; | |
75 | void __iomem *base; | |
76 | u32 num; | |
77 | u32 flags; | |
78 | u32 input_rate; | |
79 | }; | |
80 | #define PLL_HAS_PREDIV 0x01 | |
81 | #define PLL_HAS_POSTDIV 0x02 | |
82 | ||
3e062b07 VB |
83 | struct clk { |
84 | struct list_head node; | |
85 | struct module *owner; | |
86 | const char *name; | |
c5b736d0 KH |
87 | unsigned long rate; |
88 | u8 usecount; | |
c5b736d0 | 89 | u8 lpsc; |
789a785e | 90 | u8 gpsc; |
5d36a332 | 91 | u32 flags; |
c5b736d0 | 92 | struct clk *parent; |
f02bf3b3 SN |
93 | struct list_head children; /* list of children */ |
94 | struct list_head childnode; /* parent's child list node */ | |
c5b736d0 KH |
95 | struct pll_data *pll_data; |
96 | u32 div_reg; | |
de381a91 | 97 | unsigned long (*recalc) (struct clk *); |
d6a61563 SN |
98 | int (*set_rate) (struct clk *clk, unsigned long rate); |
99 | int (*round_rate) (struct clk *clk, unsigned long rate); | |
3e062b07 VB |
100 | }; |
101 | ||
5d36a332 | 102 | /* Clock flags: SoC-specific flags start at BIT(16) */ |
c5b736d0 KH |
103 | #define ALWAYS_ENABLED BIT(1) |
104 | #define CLK_PSC BIT(2) | |
105 | #define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ | |
106 | #define CLK_PLL BIT(4) /* PLL-derived clock */ | |
107 | #define PRE_PLL BIT(5) /* source is before PLL mult/div */ | |
108 | ||
109 | struct davinci_clk { | |
110 | struct clk_lookup lk; | |
111 | }; | |
112 | ||
113 | #define CLK(dev, con, ck) \ | |
114 | { \ | |
115 | .lk = { \ | |
116 | .dev_id = dev, \ | |
117 | .con_id = con, \ | |
118 | .clk = ck, \ | |
119 | }, \ | |
120 | } | |
3e062b07 | 121 | |
c5b736d0 | 122 | int davinci_clk_init(struct davinci_clk *clocks); |
d6a61563 SN |
123 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, |
124 | unsigned int mult, unsigned int postdiv); | |
fb631387 KH |
125 | |
126 | extern struct platform_device davinci_wdt_device; | |
127 | ||
3e062b07 | 128 | #endif |
e2da3aaa SN |
129 | |
130 | #endif |