[linux-2.6-block.git] / arch / arm / mach-davinci / clock.h

/*
 * TI DaVinci clock definitions
 *
 * Copyright (C) 2006-2007 Texas Instruments.
 * Copyright (C) 2008-2009 Deep Root Systems, LLC
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
#define __ARCH_ARM_DAVINCI_CLOCK_H

#include <linux/list.h>
#include <asm/clkdev.h>

#define DAVINCI_PLL1_BASE 0x01c40800
#define DAVINCI_PLL2_BASE 0x01c40c00
#define MAX_PLL 2

/* PLL/Reset register offsets */
#define PLLCTL          0x100
#define PLLCTL_PLLEN    BIT(0)
#define PLLCTL_PLLPWRDN	BIT(1)
#define PLLCTL_PLLRST	BIT(3)
#define PLLCTL_PLLDIS	BIT(4)
#define PLLCTL_PLLENSRC	BIT(5)
#define PLLCTL_CLKMODE  BIT(8)

#define PLLM		0x110
#define PLLM_PLLM_MASK  0xff

#define PREDIV          0x114
#define PLLDIV1         0x118
#define PLLDIV2         0x11c
#define PLLDIV3         0x120
#define POSTDIV         0x128
#define BPDIV           0x12c
#define PLLCMD		0x138
#define PLLSTAT		0x13c
#define PLLALNCTL	0x140
#define PLLDCHANGE	0x144
#define PLLCKEN		0x148
#define PLLCKSTAT	0x14c
#define PLLSYSTAT	0x150
#define PLLDIV4         0x160
#define PLLDIV5         0x164
#define PLLDIV6         0x168
#define PLLDIV7         0x16c
#define PLLDIV8         0x170
#define PLLDIV9         0x174
#define PLLDIV_EN       BIT(15)
#define PLLDIV_RATIO_MASK 0x1f

struct pll_data {
	u32 phys_base;
	void __iomem *base;
	u32 num;
	u32 flags;
	u32 input_rate;
};
#define PLL_HAS_PREDIV          0x01
#define PLL_HAS_POSTDIV         0x02

struct clk {
	struct list_head	node;
	struct module		*owner;
	const char		*name;
	unsigned long		rate;
	u8			usecount;
	u8			lpsc;
	u8			psc_ctlr;
	u32			flags;
	struct clk              *parent;
	struct list_head	children; 	/* list of children */
	struct list_head	childnode;	/* parent's child list node */
	struct pll_data         *pll_data;
	u32                     div_reg;
	unsigned long (*recalc) (struct clk *);
	int (*set_rate) (struct clk *clk, unsigned long rate);
	int (*round_rate) (struct clk *clk, unsigned long rate);
};

/* Clock flags: SoC-specific flags start at BIT(16) */
#define ALWAYS_ENABLED		BIT(1)
#define CLK_PSC                 BIT(2)
#define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
#define CLK_PLL			BIT(4) /* PLL-derived clock */
#define PRE_PLL                 BIT(5) /* source is before PLL mult/div */

struct davinci_clk {
	struct clk_lookup lk;
};

#define CLK(dev, con, ck) 		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
			.clk = ck,	\
		},			\
	}

int davinci_clk_init(struct davinci_clk *clocks);
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
				unsigned int mult, unsigned int postdiv);

extern struct platform_device davinci_wdt_device;

#endif
Commit	Line	Data
3e062b07 VB	1	/*
	2	* TI DaVinci clock definitions
	3	*
c5b736d0 KH	4	* Copyright (C) 2006-2007 Texas Instruments.
c5b736d0 KH	5	* Copyright (C) 2008-2009 Deep Root Systems, LLC
3e062b07 VB	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
	13	#define __ARCH_ARM_DAVINCI_CLOCK_H
	14
c5b736d0 KH	15	#include <linux/list.h>
	16	#include <asm/clkdev.h>
	17
	18	#define DAVINCI_PLL1_BASE 0x01c40800
	19	#define DAVINCI_PLL2_BASE 0x01c40c00
	20	#define MAX_PLL 2
	21
	22	/* PLL/Reset register offsets */
	23	#define PLLCTL 0x100
	24	#define PLLCTL_PLLEN BIT(0)
d6a61563 SN	25	#define PLLCTL_PLLPWRDN BIT(1)
	26	#define PLLCTL_PLLRST BIT(3)
	27	#define PLLCTL_PLLDIS BIT(4)
	28	#define PLLCTL_PLLENSRC BIT(5)
c5b736d0 KH	29	#define PLLCTL_CLKMODE BIT(8)
	30
	31	#define PLLM 0x110
	32	#define PLLM_PLLM_MASK 0xff
	33
	34	#define PREDIV 0x114
	35	#define PLLDIV1 0x118
	36	#define PLLDIV2 0x11c
	37	#define PLLDIV3 0x120
	38	#define POSTDIV 0x128
	39	#define BPDIV 0x12c
	40	#define PLLCMD 0x138
	41	#define PLLSTAT 0x13c
	42	#define PLLALNCTL 0x140
	43	#define PLLDCHANGE 0x144
	44	#define PLLCKEN 0x148
	45	#define PLLCKSTAT 0x14c
	46	#define PLLSYSTAT 0x150
	47	#define PLLDIV4 0x160
	48	#define PLLDIV5 0x164
	49	#define PLLDIV6 0x168
	50	#define PLLDIV7 0x16c
	51	#define PLLDIV8 0x170
	52	#define PLLDIV9 0x174
	53	#define PLLDIV_EN BIT(15)
	54	#define PLLDIV_RATIO_MASK 0x1f
	55
	56	struct pll_data {
	57	u32 phys_base;
	58	void __iomem *base;
	59	u32 num;
	60	u32 flags;
	61	u32 input_rate;
	62	};
	63	#define PLL_HAS_PREDIV 0x01
	64	#define PLL_HAS_POSTDIV 0x02
	65
3e062b07 VB	66	struct clk {
	67	struct list_head node;
	68	struct module *owner;
	69	const char *name;
c5b736d0 KH	70	unsigned long rate;
c5b736d0 KH	71	u8 usecount;
c5b736d0	72	u8 lpsc;
d81d188c	73	u8 psc_ctlr;
5d36a332	74	u32 flags;
c5b736d0	75	struct clk *parent;
f02bf3b3 SN	76	struct list_head children; /* list of children */
f02bf3b3 SN	77	struct list_head childnode; /* parent's child list node */
c5b736d0 KH	78	struct pll_data *pll_data;
c5b736d0 KH	79	u32 div_reg;
de381a91	80	unsigned long (recalc) (struct clk );
d6a61563 SN	81	int (set_rate) (struct clk clk, unsigned long rate);
d6a61563 SN	82	int (round_rate) (struct clk clk, unsigned long rate);
3e062b07 VB	83	};
3e062b07 VB	84
5d36a332	85	/* Clock flags: SoC-specific flags start at BIT(16) */
c5b736d0 KH	86	#define ALWAYS_ENABLED BIT(1)
	87	#define CLK_PSC BIT(2)
	88	#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
	89	#define CLK_PLL BIT(4) /* PLL-derived clock */
	90	#define PRE_PLL BIT(5) /* source is before PLL mult/div */
	91
	92	struct davinci_clk {
	93	struct clk_lookup lk;
	94	};
	95
	96	#define CLK(dev, con, ck) \
	97	{ \
	98	.lk = { \
	99	.dev_id = dev, \
	100	.con_id = con, \
	101	.clk = ck, \
	102	}, \
	103	}
3e062b07	104
c5b736d0	105	int davinci_clk_init(struct davinci_clk *clocks);
d6a61563 SN	106	int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
d6a61563 SN	107	unsigned int mult, unsigned int postdiv);
fb631387 KH	108
	109	extern struct platform_device davinci_wdt_device;
	110
3e062b07	111	#endif