[linux-2.6-block.git] / arch / arm / mach-davinci / clock.c

/*
 * Clock and PLL control for DaVinci devices
 *
 * Copyright (C) 2006-2007 Texas Instruments.
 * Copyright (C) 2008-2009 Deep Root Systems, LLC
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <mach/hardware.h>

#include <mach/clock.h>
#include "psc.h"
#include <mach/cputype.h>
#include "clock.h"

static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
static DEFINE_SPINLOCK(clockfw_lock);

void davinci_clk_enable(struct clk *clk)
{
	if (clk->parent)
		davinci_clk_enable(clk->parent);
	if (clk->usecount++ == 0) {
		if (clk->flags & CLK_PSC)
			davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
					   true, clk->flags);
		else if (clk->clk_enable)
			clk->clk_enable(clk);
	}
}

void davinci_clk_disable(struct clk *clk)
{
	if (WARN_ON(clk->usecount == 0))
		return;
	if (--clk->usecount == 0) {
		if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
			davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
					   false, clk->flags);
		else if (clk->clk_disable)
			clk->clk_disable(clk);
	}
	if (clk->parent)
		davinci_clk_disable(clk->parent);
}

int davinci_clk_reset(struct clk *clk, bool reset)
{
	unsigned long flags;

	if (clk == NULL || IS_ERR(clk))
		return -EINVAL;

	spin_lock_irqsave(&clockfw_lock, flags);
	if (clk->flags & CLK_PSC)
		davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(davinci_clk_reset);

int davinci_clk_reset_assert(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk) || !clk->reset)
		return -EINVAL;

	return clk->reset(clk, true);
}
EXPORT_SYMBOL(davinci_clk_reset_assert);

int davinci_clk_reset_deassert(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk) || !clk->reset)
		return -EINVAL;

	return clk->reset(clk, false);
}
EXPORT_SYMBOL(davinci_clk_reset_deassert);

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return 0;
	else if (IS_ERR(clk))
		return -EINVAL;

	spin_lock_irqsave(&clockfw_lock, flags);
	davinci_clk_enable(clk);
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_enable);

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	if (clk == NULL || IS_ERR(clk))
		return;

	spin_lock_irqsave(&clockfw_lock, flags);
	davinci_clk_disable(clk);
	spin_unlock_irqrestore(&clockfw_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk))
		return 0;

	return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	if (clk == NULL || IS_ERR(clk))
		return 0;

	if (clk->round_rate)
		return clk->round_rate(clk, rate);

	return clk->rate;
}
EXPORT_SYMBOL(clk_round_rate);

/* Propagate rate to children */
static void propagate_rate(struct clk *root)
{
	struct clk *clk;

	list_for_each_entry(clk, &root->children, childnode) {
		if (clk->recalc)
			clk->rate = clk->recalc(clk);
		propagate_rate(clk);
	}
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long flags;
	int ret = -EINVAL;

	if (!clk)
		return 0;
	else if (IS_ERR(clk))
		return -EINVAL;

	if (clk->set_rate)
		ret = clk->set_rate(clk, rate);

	spin_lock_irqsave(&clockfw_lock, flags);
	if (ret == 0) {
		if (clk->recalc)
			clk->rate = clk->recalc(clk);
		propagate_rate(clk);
	}
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return ret;
}
EXPORT_SYMBOL(clk_set_rate);

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	unsigned long flags;

	if (!clk)
		return 0;
	else if (IS_ERR(clk))
		return -EINVAL;

	/* Cannot change parent on enabled clock */
	if (WARN_ON(clk->usecount))
		return -EINVAL;

	mutex_lock(&clocks_mutex);
	if (clk->set_parent) {
		int ret = clk->set_parent(clk, parent);

		if (ret) {
			mutex_unlock(&clocks_mutex);
			return ret;
		}
	}
	clk->parent = parent;
	list_del_init(&clk->childnode);
	list_add(&clk->childnode, &clk->parent->children);
	mutex_unlock(&clocks_mutex);

	spin_lock_irqsave(&clockfw_lock, flags);
	if (clk->recalc)
		clk->rate = clk->recalc(clk);
	propagate_rate(clk);
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_set_parent);

int clk_register(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk))
		return -EINVAL;

	if (WARN(clk->parent && !clk->parent->rate,
			"CLK: %s parent %s has no rate!\n",
			clk->name, clk->parent->name))
		return -EINVAL;

	INIT_LIST_HEAD(&clk->children);

	mutex_lock(&clocks_mutex);
	list_add_tail(&clk->node, &clocks);
	if (clk->parent) {
		if (clk->set_parent) {
			int ret = clk->set_parent(clk, clk->parent);

			if (ret) {
				mutex_unlock(&clocks_mutex);
				return ret;
			}
		}
		list_add_tail(&clk->childnode, &clk->parent->children);
	}
	mutex_unlock(&clocks_mutex);

	/* If rate is already set, use it */
	if (clk->rate)
		return 0;

	/* Else, see if there is a way to calculate it */
	if (clk->recalc)
		clk->rate = clk->recalc(clk);

	/* Otherwise, default to parent rate */
	else if (clk->parent)
		clk->rate = clk->parent->rate;

	return 0;
}
EXPORT_SYMBOL(clk_register);

void clk_unregister(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk))
		return;

	mutex_lock(&clocks_mutex);
	list_del(&clk->node);
	list_del(&clk->childnode);
	mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_unregister);

#ifdef CONFIG_DAVINCI_RESET_CLOCKS
/*
 * Disable any unused clocks left on by the bootloader
 */
int __init davinci_clk_disable_unused(void)
{
	struct clk *ck;

	spin_lock_irq(&clockfw_lock);
	list_for_each_entry(ck, &clocks, node) {
		if (ck->usecount > 0)
			continue;
		if (!(ck->flags & CLK_PSC))
			continue;

		/* ignore if in Disabled or SwRstDisable states */
		if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
			continue;

		pr_debug("Clocks: disable unused %s\n", ck->name);

		davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
				false, ck->flags);
	}
	spin_unlock_irq(&clockfw_lock);

	return 0;
}
#endif

static unsigned long clk_sysclk_recalc(struct clk *clk)
{
	u32 v, plldiv;
	struct pll_data *pll;
	unsigned long rate = clk->rate;

	/* If this is the PLL base clock, no more calculations needed */
	if (clk->pll_data)
		return rate;

	if (WARN_ON(!clk->parent))
		return rate;

	rate = clk->parent->rate;

	/* Otherwise, the parent must be a PLL */
	if (WARN_ON(!clk->parent->pll_data))
		return rate;

	pll = clk->parent->pll_data;

	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	if (clk->flags & PRE_PLL)
		rate = pll->input_rate;

	if (!clk->div_reg)
		return rate;

	v = __raw_readl(pll->base + clk->div_reg);
	if (v & PLLDIV_EN) {
		plldiv = (v & pll->div_ratio_mask) + 1;
		if (plldiv)
			rate /= plldiv;
	}

	return rate;
}

int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
{
	unsigned v;
	struct pll_data *pll;
	unsigned long input;
	unsigned ratio = 0;

	/* If this is the PLL base clock, wrong function to call */
	if (clk->pll_data)
		return -EINVAL;

	/* There must be a parent... */
	if (WARN_ON(!clk->parent))
		return -EINVAL;

	/* ... the parent must be a PLL... */
	if (WARN_ON(!clk->parent->pll_data))
		return -EINVAL;

	/* ... and this clock must have a divider. */
	if (WARN_ON(!clk->div_reg))
		return -EINVAL;

	pll = clk->parent->pll_data;

	input = clk->parent->rate;

	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	if (clk->flags & PRE_PLL)
		input = pll->input_rate;

	if (input > rate) {
		/*
		 * Can afford to provide an output little higher than requested
		 * only if maximum rate supported by hardware on this sysclk
		 * is known.
		 */
		if (clk->maxrate) {
			ratio = DIV_ROUND_CLOSEST(input, rate);
			if (input / ratio > clk->maxrate)
				ratio = 0;
		}

		if (ratio == 0)
			ratio = DIV_ROUND_UP(input, rate);

		ratio--;
	}

	if (ratio > pll->div_ratio_mask)
		return -EINVAL;

	do {
		v = __raw_readl(pll->base + PLLSTAT);
	} while (v & PLLSTAT_GOSTAT);

	v = __raw_readl(pll->base + clk->div_reg);
	v &= ~pll->div_ratio_mask;
	v |= ratio | PLLDIV_EN;
	__raw_writel(v, pll->base + clk->div_reg);

	v = __raw_readl(pll->base + PLLCMD);
	v |= PLLCMD_GOSET;
	__raw_writel(v, pll->base + PLLCMD);

	do {
		v = __raw_readl(pll->base + PLLSTAT);
	} while (v & PLLSTAT_GOSTAT);

	return 0;
}
EXPORT_SYMBOL(davinci_set_sysclk_rate);

static unsigned long clk_leafclk_recalc(struct clk *clk)
{
	if (WARN_ON(!clk->parent))
		return clk->rate;

	return clk->parent->rate;
}

int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
{
	clk->rate = rate;
	return 0;
}

static unsigned long clk_pllclk_recalc(struct clk *clk)
{
	u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
	u8 bypass;
	struct pll_data *pll = clk->pll_data;
	unsigned long rate = clk->rate;

	ctrl = __raw_readl(pll->base + PLLCTL);
	rate = pll->input_rate = clk->parent->rate;

	if (ctrl & PLLCTL_PLLEN) {
		bypass = 0;
		mult = __raw_readl(pll->base + PLLM);
		if (cpu_is_davinci_dm365())
			mult = 2 * (mult & PLLM_PLLM_MASK);
		else
			mult = (mult & PLLM_PLLM_MASK) + 1;
	} else
		bypass = 1;

	if (pll->flags & PLL_HAS_PREDIV) {
		prediv = __raw_readl(pll->base + PREDIV);
		if (prediv & PLLDIV_EN)
			prediv = (prediv & pll->div_ratio_mask) + 1;
		else
			prediv = 1;
	}

	/* pre-divider is fixed, but (some?) chips won't report that */
	if (cpu_is_davinci_dm355() && pll->num == 1)
		prediv = 8;

	if (pll->flags & PLL_HAS_POSTDIV) {
		postdiv = __raw_readl(pll->base + POSTDIV);
		if (postdiv & PLLDIV_EN)
			postdiv = (postdiv & pll->div_ratio_mask) + 1;
		else
			postdiv = 1;
	}

	if (!bypass) {
		rate /= prediv;
		rate *= mult;
		rate /= postdiv;
	}

	pr_debug("PLL%d: input = %lu MHz [ ",
		 pll->num, clk->parent->rate / 1000000);
	if (bypass)
		pr_debug("bypass ");
	if (prediv > 1)
		pr_debug("/ %d ", prediv);
	if (mult > 1)
		pr_debug("* %d ", mult);
	if (postdiv > 1)
		pr_debug("/ %d ", postdiv);
	pr_debug("] --> %lu MHz output.\n", rate / 1000000);

	return rate;
}

/**
 * davinci_set_pllrate - set the output rate of a given PLL.
 *
 * Note: Currently tested to work with OMAP-L138 only.
 *
 * @pll: pll whose rate needs to be changed.
 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
 * @postdiv: The post divider value. Passing 0 disables the post-divider.
 */
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
					unsigned int mult, unsigned int postdiv)
{
	u32 ctrl;
	unsigned int locktime;
	unsigned long flags;

	if (pll->base == NULL)
		return -EINVAL;

	/*
	 *  PLL lock time required per OMAP-L138 datasheet is
	 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
	 * as 4 and OSCIN cycle as 25 MHz.
	 */
	if (prediv) {
		locktime = ((2000 * prediv) / 100);
		prediv = (prediv - 1) | PLLDIV_EN;
	} else {
		locktime = PLL_LOCK_TIME;
	}
	if (postdiv)
		postdiv = (postdiv - 1) | PLLDIV_EN;
	if (mult)
		mult = mult - 1;

	/* Protect against simultaneous calls to PLL setting seqeunce */
	spin_lock_irqsave(&clockfw_lock, flags);

	ctrl = __raw_readl(pll->base + PLLCTL);

	/* Switch the PLL to bypass mode */
	ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
	__raw_writel(ctrl, pll->base + PLLCTL);

	udelay(PLL_BYPASS_TIME);

	/* Reset and enable PLL */
	ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
	__raw_writel(ctrl, pll->base + PLLCTL);

	if (pll->flags & PLL_HAS_PREDIV)
		__raw_writel(prediv, pll->base + PREDIV);

	__raw_writel(mult, pll->base + PLLM);

	if (pll->flags & PLL_HAS_POSTDIV)
		__raw_writel(postdiv, pll->base + POSTDIV);

	udelay(PLL_RESET_TIME);

	/* Bring PLL out of reset */
	ctrl |= PLLCTL_PLLRST;
	__raw_writel(ctrl, pll->base + PLLCTL);

	udelay(locktime);

	/* Remove PLL from bypass mode */
	ctrl |= PLLCTL_PLLEN;
	__raw_writel(ctrl, pll->base + PLLCTL);

	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(davinci_set_pllrate);

/**
 * davinci_set_refclk_rate() - Set the reference clock rate
 * @rate:	The new rate.
 *
 * Sets the reference clock rate to a given value. This will most likely
 * result in the entire clock tree getting updated.
 *
 * This is used to support boards which use a reference clock different
 * than that used by default in <soc>.c file. The reference clock rate
 * should be updated early in the boot process; ideally soon after the
 * clock tree has been initialized once with the default reference clock
 * rate (davinci_clk_init()).
 *
 * Returns 0 on success, error otherwise.
 */
int davinci_set_refclk_rate(unsigned long rate)
{
	struct clk *refclk;

	refclk = clk_get(NULL, "ref");
	if (IS_ERR(refclk)) {
		pr_err("%s: failed to get reference clock\n", __func__);
		return PTR_ERR(refclk);
	}

	clk_set_rate(refclk, rate);

	clk_put(refclk);

	return 0;
}

int __init davinci_clk_init(struct clk_lookup *clocks)
{
	struct clk_lookup *c;
	struct clk *clk;
	size_t num_clocks = 0;

	for (c = clocks; c->clk; c++) {
		clk = c->clk;

		if (!clk->recalc) {

			/* Check if clock is a PLL */
			if (clk->pll_data)
				clk->recalc = clk_pllclk_recalc;

			/* Else, if it is a PLL-derived clock */
			else if (clk->flags & CLK_PLL)
				clk->recalc = clk_sysclk_recalc;

			/* Otherwise, it is a leaf clock (PSC clock) */
			else if (clk->parent)
				clk->recalc = clk_leafclk_recalc;
		}

		if (clk->pll_data) {
			struct pll_data *pll = clk->pll_data;

			if (!pll->div_ratio_mask)
				pll->div_ratio_mask = PLLDIV_RATIO_MASK;

			if (pll->phys_base && !pll->base) {
				pll->base = ioremap(pll->phys_base, SZ_4K);
				WARN_ON(!pll->base);
			}
		}

		if (clk->recalc)
			clk->rate = clk->recalc(clk);

		if (clk->lpsc)
			clk->flags |= CLK_PSC;

		if (clk->flags & PSC_LRST)
			clk->reset = davinci_clk_reset;

		clk_register(clk);
		num_clocks++;

		/* Turn on clocks that Linux doesn't otherwise manage */
		if (clk->flags & ALWAYS_ENABLED)
			clk_enable(clk);
	}

	clkdev_add_table(clocks, num_clocks);

	return 0;
}

#ifdef CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

#define CLKNAME_MAX	10		/* longest clock name */
#define NEST_DELTA	2
#define NEST_MAX	4

static void
dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
{
	char		*state;
	char		buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
	struct clk	*clk;
	unsigned	i;

	if (parent->flags & CLK_PLL)
		state = "pll";
	else if (parent->flags & CLK_PSC)
		state = "psc";
	else
		state = "";

	/* <nest spaces> name <pad to end> */
	memset(buf, ' ', sizeof(buf) - 1);
	buf[sizeof(buf) - 1] = 0;
	i = strlen(parent->name);
	memcpy(buf + nest, parent->name,
			min(i, (unsigned)(sizeof(buf) - 1 - nest)));

	seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
		   buf, parent->usecount, state, clk_get_rate(parent));
	/* REVISIT show device associations too */

	/* cost is now small, but not linear... */
	list_for_each_entry(clk, &parent->children, childnode) {
		dump_clock(s, nest + NEST_DELTA, clk);
	}
}

static int davinci_ck_show(struct seq_file *m, void *v)
{
	struct clk *clk;

	/*
	 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
	 */
	mutex_lock(&clocks_mutex);
	list_for_each_entry(clk, &clocks, node)
		if (!clk->parent)
			dump_clock(m, 0, clk);
	mutex_unlock(&clocks_mutex);

	return 0;
}

static int davinci_ck_open(struct inode *inode, struct file *file)
{
	return single_open(file, davinci_ck_show, NULL);
}

static const struct file_operations davinci_ck_operations = {
	.open		= davinci_ck_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init davinci_clk_debugfs_init(void)
{
	debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
						&davinci_ck_operations);
	return 0;

}
device_initcall(davinci_clk_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
Commit	Line	Data
3e062b07	1	/*
c5b736d0	2	* Clock and PLL control for DaVinci devices
3e062b07	3	*
c5b736d0 KH	4	* Copyright (C) 2006-2007 Texas Instruments.
c5b736d0 KH	5	* Copyright (C) 2008-2009 Deep Root Systems, LLC
3e062b07 VB	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/errno.h>
c5b736d0	17	#include <linux/clk.h>
3e062b07 VB	18	#include <linux/err.h>
3e062b07 VB	19	#include <linux/mutex.h>
fced80c7	20	#include <linux/io.h>
d6a61563	21	#include <linux/delay.h>
3e062b07	22
a09e64fb	23	#include <mach/hardware.h>
3e062b07	24
28552c2e	25	#include <mach/clock.h>
3acf731c	26	#include "psc.h"
c5b736d0	27	#include <mach/cputype.h>
3e062b07 VB	28	#include "clock.h"
3e062b07 VB	29
3e062b07 VB	30	static LIST_HEAD(clocks);
	31	static DEFINE_MUTEX(clocks_mutex);
	32	static DEFINE_SPINLOCK(clockfw_lock);
	33
48cd30b4	34	void davinci_clk_enable(struct clk *clk)
3e062b07	35	{
c5b736d0	36	if (clk->parent)
48cd30b4	37	davinci_clk_enable(clk->parent);
c6007ffe PA	38	if (clk->usecount++ == 0) {
	39	if (clk->flags & CLK_PSC)
	40	davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
	41	true, clk->flags);
	42	else if (clk->clk_enable)
	43	clk->clk_enable(clk);
	44	}
3e062b07 VB	45	}
3e062b07 VB	46
48cd30b4	47	void davinci_clk_disable(struct clk *clk)
3e062b07	48	{
c5b736d0	49	if (WARN_ON(clk->usecount == 0))
3e062b07	50	return;
c6007ffe PA	51	if (--clk->usecount == 0) {
	52	if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
	53	davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
	54	false, clk->flags);
	55	else if (clk->clk_disable)
	56	clk->clk_disable(clk);
	57	}
c5b736d0	58	if (clk->parent)
48cd30b4	59	davinci_clk_disable(clk->parent);
3e062b07 VB	60	}
3e062b07 VB	61
af47e6bb RT	62	int davinci_clk_reset(struct clk *clk, bool reset)
	63	{
	64	unsigned long flags;
	65
	66	if (clk == NULL \|\| IS_ERR(clk))
	67	return -EINVAL;
	68
	69	spin_lock_irqsave(&clockfw_lock, flags);
	70	if (clk->flags & CLK_PSC)
	71	davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
	72	spin_unlock_irqrestore(&clockfw_lock, flags);
	73
	74	return 0;
	75	}
	76	EXPORT_SYMBOL(davinci_clk_reset);
	77
	78	int davinci_clk_reset_assert(struct clk *clk)
	79	{
	80	if (clk == NULL \|\| IS_ERR(clk) \|\| !clk->reset)
	81	return -EINVAL;
	82
	83	return clk->reset(clk, true);
	84	}
	85	EXPORT_SYMBOL(davinci_clk_reset_assert);
	86
	87	int davinci_clk_reset_deassert(struct clk *clk)
	88	{
	89	if (clk == NULL \|\| IS_ERR(clk) \|\| !clk->reset)
	90	return -EINVAL;
	91
	92	return clk->reset(clk, false);
	93	}
	94	EXPORT_SYMBOL(davinci_clk_reset_deassert);
	95
3e062b07 VB	96	int clk_enable(struct clk *clk)
	97	{
	98	unsigned long flags;
3e062b07	99
f6c1a8a6 PU	100	if (!clk)
	101	return 0;
	102	else if (IS_ERR(clk))
3e062b07 VB	103	return -EINVAL;
3e062b07 VB	104
c5b736d0	105	spin_lock_irqsave(&clockfw_lock, flags);
48cd30b4	106	davinci_clk_enable(clk);
c5b736d0	107	spin_unlock_irqrestore(&clockfw_lock, flags);
3e062b07	108
c5b736d0	109	return 0;
3e062b07 VB	110	}
	111	EXPORT_SYMBOL(clk_enable);
	112
	113	void clk_disable(struct clk *clk)
	114	{
	115	unsigned long flags;
	116
	117	if (clk == NULL \|\| IS_ERR(clk))
	118	return;
	119
c5b736d0	120	spin_lock_irqsave(&clockfw_lock, flags);
48cd30b4	121	davinci_clk_disable(clk);
c5b736d0	122	spin_unlock_irqrestore(&clockfw_lock, flags);
3e062b07 VB	123	}
	124	EXPORT_SYMBOL(clk_disable);
	125
	126	unsigned long clk_get_rate(struct clk *clk)
	127	{
	128	if (clk == NULL \|\| IS_ERR(clk))
f6c1a8a6	129	return 0;
3e062b07	130
c5b736d0	131	return clk->rate;
3e062b07 VB	132	}
	133	EXPORT_SYMBOL(clk_get_rate);
	134
	135	long clk_round_rate(struct clk *clk, unsigned long rate)
	136	{
	137	if (clk == NULL \|\| IS_ERR(clk))
4408c26b	138	return 0;
3e062b07	139
d6a61563 SN	140	if (clk->round_rate)
	141	return clk->round_rate(clk, rate);
	142
c5b736d0	143	return clk->rate;
3e062b07 VB	144	}
	145	EXPORT_SYMBOL(clk_round_rate);
	146
d6a61563 SN	147	/* Propagate rate to children */
	148	static void propagate_rate(struct clk *root)
	149	{
	150	struct clk *clk;
	151
	152	list_for_each_entry(clk, &root->children, childnode) {
	153	if (clk->recalc)
	154	clk->rate = clk->recalc(clk);
	155	propagate_rate(clk);
	156	}
	157	}
	158
3e062b07 VB	159	int clk_set_rate(struct clk *clk, unsigned long rate)
3e062b07 VB	160	{
d6a61563 SN	161	unsigned long flags;
	162	int ret = -EINVAL;
	163
f6c1a8a6 PU	164	if (!clk)
	165	return 0;
	166	else if (IS_ERR(clk))
	167	return -EINVAL;
d6a61563	168
d6a61563 SN	169	if (clk->set_rate)
d6a61563 SN	170	ret = clk->set_rate(clk, rate);
3b43cd6f SN	171
3b43cd6f SN	172	spin_lock_irqsave(&clockfw_lock, flags);
d6a61563 SN	173	if (ret == 0) {
	174	if (clk->recalc)
	175	clk->rate = clk->recalc(clk);
	176	propagate_rate(clk);
	177	}
	178	spin_unlock_irqrestore(&clockfw_lock, flags);
3e062b07	179
d6a61563	180	return ret;
3e062b07 VB	181	}
	182	EXPORT_SYMBOL(clk_set_rate);
	183
b82a51e8 SN	184	int clk_set_parent(struct clk clk, struct clk parent)
	185	{
	186	unsigned long flags;
	187
f6c1a8a6 PU	188	if (!clk)
	189	return 0;
	190	else if (IS_ERR(clk))
b82a51e8 SN	191	return -EINVAL;
	192
	193	/* Cannot change parent on enabled clock */
	194	if (WARN_ON(clk->usecount))
	195	return -EINVAL;
	196
	197	mutex_lock(&clocks_mutex);
8a9d088f DL	198	if (clk->set_parent) {
	199	int ret = clk->set_parent(clk, parent);
	200
	201	if (ret) {
	202	mutex_unlock(&clocks_mutex);
	203	return ret;
	204	}
	205	}
b82a51e8 SN	206	clk->parent = parent;
	207	list_del_init(&clk->childnode);
	208	list_add(&clk->childnode, &clk->parent->children);
	209	mutex_unlock(&clocks_mutex);
	210
	211	spin_lock_irqsave(&clockfw_lock, flags);
	212	if (clk->recalc)
	213	clk->rate = clk->recalc(clk);
	214	propagate_rate(clk);
	215	spin_unlock_irqrestore(&clockfw_lock, flags);
	216
	217	return 0;
	218	}
	219	EXPORT_SYMBOL(clk_set_parent);
	220
3e062b07 VB	221	int clk_register(struct clk *clk)
	222	{
	223	if (clk == NULL \|\| IS_ERR(clk))
	224	return -EINVAL;
	225
c5b736d0 KH	226	if (WARN(clk->parent && !clk->parent->rate,
	227	"CLK: %s parent %s has no rate!\n",
	228	clk->name, clk->parent->name))
	229	return -EINVAL;
	230
f02bf3b3 SN	231	INIT_LIST_HEAD(&clk->children);
f02bf3b3 SN	232
3e062b07	233	mutex_lock(&clocks_mutex);
c5b736d0	234	list_add_tail(&clk->node, &clocks);
8a9d088f DL	235	if (clk->parent) {
	236	if (clk->set_parent) {
	237	int ret = clk->set_parent(clk, clk->parent);
	238
	239	if (ret) {
	240	mutex_unlock(&clocks_mutex);
	241	return ret;
	242	}
	243	}
f02bf3b3	244	list_add_tail(&clk->childnode, &clk->parent->children);
8a9d088f	245	}
3e062b07 VB	246	mutex_unlock(&clocks_mutex);
3e062b07 VB	247
c5b736d0 KH	248	/* If rate is already set, use it */
	249	if (clk->rate)
	250	return 0;
	251
de381a91 SN	252	/* Else, see if there is a way to calculate it */
	253	if (clk->recalc)
	254	clk->rate = clk->recalc(clk);
	255
c5b736d0	256	/* Otherwise, default to parent rate */
de381a91	257	else if (clk->parent)
c5b736d0 KH	258	clk->rate = clk->parent->rate;
c5b736d0 KH	259
3e062b07 VB	260	return 0;
	261	}
	262	EXPORT_SYMBOL(clk_register);
	263
	264	void clk_unregister(struct clk *clk)
	265	{
	266	if (clk == NULL \|\| IS_ERR(clk))
	267	return;
	268
	269	mutex_lock(&clocks_mutex);
	270	list_del(&clk->node);
f02bf3b3	271	list_del(&clk->childnode);
3e062b07 VB	272	mutex_unlock(&clocks_mutex);
	273	}
	274	EXPORT_SYMBOL(clk_unregister);
	275
c5b736d0 KH	276	#ifdef CONFIG_DAVINCI_RESET_CLOCKS
	277	/*
	278	* Disable any unused clocks left on by the bootloader
	279	*/
3aa3e840	280	int __init davinci_clk_disable_unused(void)
c5b736d0 KH	281	{
	282	struct clk *ck;
	283
	284	spin_lock_irq(&clockfw_lock);
	285	list_for_each_entry(ck, &clocks, node) {
	286	if (ck->usecount > 0)
	287	continue;
	288	if (!(ck->flags & CLK_PSC))
	289	continue;
	290
	291	/* ignore if in Disabled or SwRstDisable states */
789a785e	292	if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
c5b736d0 KH	293	continue;
c5b736d0 KH	294
c89f1681	295	pr_debug("Clocks: disable unused %s\n", ck->name);
52958be3	296
12221d43	297	davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
a51ca38b	298	false, ck->flags);
3e062b07	299	}
c5b736d0 KH	300	spin_unlock_irq(&clockfw_lock);
	301
	302	return 0;
	303	}
c5b736d0	304	#endif
3e062b07	305
de381a91	306	static unsigned long clk_sysclk_recalc(struct clk *clk)
3e062b07	307	{
c5b736d0 KH	308	u32 v, plldiv;
c5b736d0 KH	309	struct pll_data *pll;
de381a91	310	unsigned long rate = clk->rate;
c5b736d0 KH	311
	312	/* If this is the PLL base clock, no more calculations needed */
	313	if (clk->pll_data)
de381a91	314	return rate;
c5b736d0 KH	315
c5b736d0 KH	316	if (WARN_ON(!clk->parent))
de381a91	317	return rate;
c5b736d0	318
de381a91	319	rate = clk->parent->rate;
c5b736d0 KH	320
	321	/* Otherwise, the parent must be a PLL */
	322	if (WARN_ON(!clk->parent->pll_data))
de381a91	323	return rate;
c5b736d0 KH	324
	325	pll = clk->parent->pll_data;
	326
	327	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	328	if (clk->flags & PRE_PLL)
de381a91	329	rate = pll->input_rate;
c5b736d0 KH	330
c5b736d0 KH	331	if (!clk->div_reg)
de381a91	332	return rate;
c5b736d0 KH	333
	334	v = __raw_readl(pll->base + clk->div_reg);
	335	if (v & PLLDIV_EN) {
d6961e68	336	plldiv = (v & pll->div_ratio_mask) + 1;
c5b736d0	337	if (plldiv)
de381a91	338	rate /= plldiv;
c5b736d0	339	}
de381a91 SN	340
	341	return rate;
	342	}
	343
b39639b8 SN	344	int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
	345	{
	346	unsigned v;
	347	struct pll_data *pll;
	348	unsigned long input;
	349	unsigned ratio = 0;
	350
	351	/* If this is the PLL base clock, wrong function to call */
	352	if (clk->pll_data)
	353	return -EINVAL;
	354
	355	/* There must be a parent... */
	356	if (WARN_ON(!clk->parent))
	357	return -EINVAL;
	358
	359	/* ... the parent must be a PLL... */
	360	if (WARN_ON(!clk->parent->pll_data))
	361	return -EINVAL;
	362
	363	/* ... and this clock must have a divider. */
	364	if (WARN_ON(!clk->div_reg))
	365	return -EINVAL;
	366
	367	pll = clk->parent->pll_data;
	368
	369	input = clk->parent->rate;
	370
	371	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	372	if (clk->flags & PRE_PLL)
	373	input = pll->input_rate;
	374
	375	if (input > rate) {
	376	/*
	377	* Can afford to provide an output little higher than requested
	378	* only if maximum rate supported by hardware on this sysclk
	379	* is known.
	380	*/
	381	if (clk->maxrate) {
	382	ratio = DIV_ROUND_CLOSEST(input, rate);
	383	if (input / ratio > clk->maxrate)
	384	ratio = 0;
	385	}
	386
	387	if (ratio == 0)
	388	ratio = DIV_ROUND_UP(input, rate);
	389
	390	ratio--;
	391	}
	392
b1d05be6	393	if (ratio > pll->div_ratio_mask)
b39639b8 SN	394	return -EINVAL;
	395
	396	do {
	397	v = __raw_readl(pll->base + PLLSTAT);
	398	} while (v & PLLSTAT_GOSTAT);
	399
	400	v = __raw_readl(pll->base + clk->div_reg);
b1d05be6	401	v &= ~pll->div_ratio_mask;
b39639b8 SN	402	v \|= ratio \| PLLDIV_EN;
	403	__raw_writel(v, pll->base + clk->div_reg);
	404
	405	v = __raw_readl(pll->base + PLLCMD);
	406	v \|= PLLCMD_GOSET;
	407	__raw_writel(v, pll->base + PLLCMD);
	408
	409	do {
	410	v = __raw_readl(pll->base + PLLSTAT);
	411	} while (v & PLLSTAT_GOSTAT);
	412
	413	return 0;
	414	}
	415	EXPORT_SYMBOL(davinci_set_sysclk_rate);
	416
de381a91 SN	417	static unsigned long clk_leafclk_recalc(struct clk *clk)
	418	{
	419	if (WARN_ON(!clk->parent))
	420	return clk->rate;
	421
	422	return clk->parent->rate;
c5b736d0 KH	423	}
c5b736d0 KH	424
56e580d7 SN	425	int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
	426	{
	427	clk->rate = rate;
	428	return 0;
	429	}
	430
de381a91	431	static unsigned long clk_pllclk_recalc(struct clk *clk)
c5b736d0 KH	432	{
	433	u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
	434	u8 bypass;
	435	struct pll_data *pll = clk->pll_data;
de381a91	436	unsigned long rate = clk->rate;
c5b736d0	437
c5b736d0	438	ctrl = __raw_readl(pll->base + PLLCTL);
de381a91	439	rate = pll->input_rate = clk->parent->rate;
c5b736d0 KH	440
	441	if (ctrl & PLLCTL_PLLEN) {
	442	bypass = 0;
	443	mult = __raw_readl(pll->base + PLLM);
fb8fcb89 SP	444	if (cpu_is_davinci_dm365())
	445	mult = 2 * (mult & PLLM_PLLM_MASK);
	446	else
	447	mult = (mult & PLLM_PLLM_MASK) + 1;
c5b736d0 KH	448	} else
	449	bypass = 1;
	450
	451	if (pll->flags & PLL_HAS_PREDIV) {
	452	prediv = __raw_readl(pll->base + PREDIV);
	453	if (prediv & PLLDIV_EN)
d6961e68	454	prediv = (prediv & pll->div_ratio_mask) + 1;
c5b736d0 KH	455	else
	456	prediv = 1;
	457	}
	458
	459	/* pre-divider is fixed, but (some?) chips won't report that */
	460	if (cpu_is_davinci_dm355() && pll->num == 1)
	461	prediv = 8;
	462
	463	if (pll->flags & PLL_HAS_POSTDIV) {
	464	postdiv = __raw_readl(pll->base + POSTDIV);
	465	if (postdiv & PLLDIV_EN)
d6961e68	466	postdiv = (postdiv & pll->div_ratio_mask) + 1;
c5b736d0 KH	467	else
	468	postdiv = 1;
	469	}
	470
	471	if (!bypass) {
de381a91 SN	472	rate /= prediv;
	473	rate *= mult;
	474	rate /= postdiv;
c5b736d0 KH	475	}
	476
	477	pr_debug("PLL%d: input = %lu MHz [ ",
	478	pll->num, clk->parent->rate / 1000000);
	479	if (bypass)
	480	pr_debug("bypass ");
	481	if (prediv > 1)
	482	pr_debug("/ %d ", prediv);
	483	if (mult > 1)
	484	pr_debug("* %d ", mult);
	485	if (postdiv > 1)
	486	pr_debug("/ %d ", postdiv);
de381a91 SN	487	pr_debug("] --> %lu MHz output.\n", rate / 1000000);
	488
	489	return rate;
c5b736d0 KH	490	}
c5b736d0 KH	491
d6a61563 SN	492	/**
	493	* davinci_set_pllrate - set the output rate of a given PLL.
	494	*
	495	* Note: Currently tested to work with OMAP-L138 only.
	496	*
	497	* @pll: pll whose rate needs to be changed.
	498	* @prediv: The pre divider value. Passing 0 disables the pre-divider.
	499	* @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
	500	* @postdiv: The post divider value. Passing 0 disables the post-divider.
	501	*/
	502	int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
	503	unsigned int mult, unsigned int postdiv)
	504	{
	505	u32 ctrl;
	506	unsigned int locktime;
3b43cd6f	507	unsigned long flags;
d6a61563 SN	508
	509	if (pll->base == NULL)
	510	return -EINVAL;
	511
	512	/*
	513	* PLL lock time required per OMAP-L138 datasheet is
	514	* (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
	515	* as 4 and OSCIN cycle as 25 MHz.
	516	*/
	517	if (prediv) {
	518	locktime = ((2000 * prediv) / 100);
	519	prediv = (prediv - 1) \| PLLDIV_EN;
	520	} else {
9a219a9e	521	locktime = PLL_LOCK_TIME;
d6a61563 SN	522	}
	523	if (postdiv)
	524	postdiv = (postdiv - 1) \| PLLDIV_EN;
	525	if (mult)
	526	mult = mult - 1;
	527
3b43cd6f SN	528	/* Protect against simultaneous calls to PLL setting seqeunce */
	529	spin_lock_irqsave(&clockfw_lock, flags);
	530
d6a61563 SN	531	ctrl = __raw_readl(pll->base + PLLCTL);
	532
	533	/* Switch the PLL to bypass mode */
	534	ctrl &= ~(PLLCTL_PLLENSRC \| PLLCTL_PLLEN);
	535	__raw_writel(ctrl, pll->base + PLLCTL);
	536
9a219a9e	537	udelay(PLL_BYPASS_TIME);
d6a61563 SN	538
	539	/* Reset and enable PLL */
	540	ctrl &= ~(PLLCTL_PLLRST \| PLLCTL_PLLDIS);
	541	__raw_writel(ctrl, pll->base + PLLCTL);
	542
	543	if (pll->flags & PLL_HAS_PREDIV)
	544	__raw_writel(prediv, pll->base + PREDIV);
	545
	546	__raw_writel(mult, pll->base + PLLM);
	547
	548	if (pll->flags & PLL_HAS_POSTDIV)
	549	__raw_writel(postdiv, pll->base + POSTDIV);
	550
9a219a9e	551	udelay(PLL_RESET_TIME);
d6a61563 SN	552
	553	/* Bring PLL out of reset */
	554	ctrl \|= PLLCTL_PLLRST;
	555	__raw_writel(ctrl, pll->base + PLLCTL);
	556
	557	udelay(locktime);
	558
	559	/* Remove PLL from bypass mode */
	560	ctrl \|= PLLCTL_PLLEN;
	561	__raw_writel(ctrl, pll->base + PLLCTL);
	562
3b43cd6f SN	563	spin_unlock_irqrestore(&clockfw_lock, flags);
3b43cd6f SN	564
d6a61563 SN	565	return 0;
	566	}
	567	EXPORT_SYMBOL(davinci_set_pllrate);
	568
56e580d7 SN	569	/**
	570	* davinci_set_refclk_rate() - Set the reference clock rate
	571	* @rate: The new rate.
	572	*
	573	* Sets the reference clock rate to a given value. This will most likely
	574	* result in the entire clock tree getting updated.
	575	*
	576	* This is used to support boards which use a reference clock different
	577	* than that used by default in <soc>.c file. The reference clock rate
	578	* should be updated early in the boot process; ideally soon after the
	579	* clock tree has been initialized once with the default reference clock
6fc9ebbd	580	* rate (davinci_clk_init()).
56e580d7 SN	581	*
	582	* Returns 0 on success, error otherwise.
	583	*/
	584	int davinci_set_refclk_rate(unsigned long rate)
	585	{
	586	struct clk *refclk;
	587
	588	refclk = clk_get(NULL, "ref");
	589	if (IS_ERR(refclk)) {
a7ca2bcf	590	pr_err("%s: failed to get reference clock\n", __func__);
56e580d7 SN	591	return PTR_ERR(refclk);
	592	}
	593
	594	clk_set_rate(refclk, rate);
	595
	596	clk_put(refclk);
	597
	598	return 0;
	599	}
	600
08aca087	601	int __init davinci_clk_init(struct clk_lookup *clocks)
af47e6bb	602	{
08aca087	603	struct clk_lookup *c;
c5b736d0	604	struct clk *clk;
08aca087	605	size_t num_clocks = 0;
c5b736d0	606
08aca087 KH	607	for (c = clocks; c->clk; c++) {
08aca087 KH	608	clk = c->clk;
c5b736d0	609
de381a91 SN	610	if (!clk->recalc) {
	611
	612	/* Check if clock is a PLL */
	613	if (clk->pll_data)
	614	clk->recalc = clk_pllclk_recalc;
	615
	616	/* Else, if it is a PLL-derived clock */
	617	else if (clk->flags & CLK_PLL)
	618	clk->recalc = clk_sysclk_recalc;
	619
	620	/* Otherwise, it is a leaf clock (PSC clock) */
	621	else if (clk->parent)
	622	clk->recalc = clk_leafclk_recalc;
	623	}
c5b736d0	624
e4c822c7 CC	625	if (clk->pll_data) {
	626	struct pll_data *pll = clk->pll_data;
	627
	628	if (!pll->div_ratio_mask)
	629	pll->div_ratio_mask = PLLDIV_RATIO_MASK;
	630
	631	if (pll->phys_base && !pll->base) {
	632	pll->base = ioremap(pll->phys_base, SZ_4K);
	633	WARN_ON(!pll->base);
	634	}
	635	}
d6961e68	636
de381a91 SN	637	if (clk->recalc)
de381a91 SN	638	clk->rate = clk->recalc(clk);
c5b736d0 KH	639
	640	if (clk->lpsc)
	641	clk->flags \|= CLK_PSC;
	642
af47e6bb RT	643	if (clk->flags & PSC_LRST)
	644	clk->reset = davinci_clk_reset;
	645
c5b736d0	646	clk_register(clk);
08aca087	647	num_clocks++;
c5b736d0 KH	648
	649	/* Turn on clocks that Linux doesn't otherwise manage */
	650	if (clk->flags & ALWAYS_ENABLED)
	651	clk_enable(clk);
3e062b07 VB	652	}
3e062b07 VB	653
08aca087 KH	654	clkdev_add_table(clocks, num_clocks);
08aca087 KH	655
3e062b07 VB	656	return 0;
	657	}
	658
2f72e8dc	659	#ifdef CONFIG_DEBUG_FS
3e062b07	660
2f72e8dc SN	661	#include <linux/debugfs.h>
2f72e8dc SN	662	#include <linux/seq_file.h>
3e062b07	663
c5b736d0 KH	664	#define CLKNAME_MAX 10 /* longest clock name */
	665	#define NEST_DELTA 2
	666	#define NEST_MAX 4
	667
	668	static void
	669	dump_clock(struct seq_file s, unsigned nest, struct clk parent)
3e062b07	670	{
c5b736d0 KH	671	char *state;
	672	char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
	673	struct clk *clk;
	674	unsigned i;
	675
	676	if (parent->flags & CLK_PLL)
	677	state = "pll";
	678	else if (parent->flags & CLK_PSC)
	679	state = "psc";
	680	else
	681	state = "";
	682
	683	/* <nest spaces> name <pad to end> */
	684	memset(buf, ' ', sizeof(buf) - 1);
	685	buf[sizeof(buf) - 1] = 0;
	686	i = strlen(parent->name);
	687	memcpy(buf + nest, parent->name,
	688	min(i, (unsigned)(sizeof(buf) - 1 - nest)));
	689
	690	seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
	691	buf, parent->usecount, state, clk_get_rate(parent));
	692	/* REVISIT show device associations too */
	693
	694	/* cost is now small, but not linear... */
f02bf3b3 SN	695	list_for_each_entry(clk, &parent->children, childnode) {
f02bf3b3 SN	696	dump_clock(s, nest + NEST_DELTA, clk);
c5b736d0 KH	697	}
c5b736d0 KH	698	}
3e062b07	699
c5b736d0 KH	700	static int davinci_ck_show(struct seq_file m, void v)
c5b736d0 KH	701	{
f979aa6e SN	702	struct clk *clk;
	703
	704	/*
	705	* Show clock tree; We trust nonzero usecounts equate to PSC enables...
c5b736d0 KH	706	*/
c5b736d0 KH	707	mutex_lock(&clocks_mutex);
f979aa6e SN	708	list_for_each_entry(clk, &clocks, node)
	709	if (!clk->parent)
	710	dump_clock(m, 0, clk);
c5b736d0	711	mutex_unlock(&clocks_mutex);
3e062b07 VB	712
	713	return 0;
	714	}
	715
3e062b07 VB	716	static int davinci_ck_open(struct inode inode, struct file file)
3e062b07 VB	717	{
2f72e8dc	718	return single_open(file, davinci_ck_show, NULL);
3e062b07 VB	719	}
3e062b07 VB	720
2f72e8dc	721	static const struct file_operations davinci_ck_operations = {
3e062b07 VB	722	.open = davinci_ck_open,
	723	.read = seq_read,
	724	.llseek = seq_lseek,
2f72e8dc	725	.release = single_release,
3e062b07 VB	726	};
3e062b07 VB	727
2f72e8dc	728	static int __init davinci_clk_debugfs_init(void)
3e062b07	729	{
2f72e8dc SN	730	debugfs_create_file("davinci_clocks", S_IFREG \| S_IRUGO, NULL, NULL,
2f72e8dc SN	731	&davinci_ck_operations);
3e062b07 VB	732	return 0;
	733
	734	}
2f72e8dc SN	735	device_initcall(davinci_clk_debugfs_init);
2f72e8dc SN	736	#endif /* CONFIG_DEBUG_FS */