[linux-2.6-block.git] / arch / arm / mach-davinci / board-mityomapl138.c

/*
 * Critical Link MityOMAP-L138 SoM
 *
 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of
 * any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/platform_data/at24.h>
#include <linux/etherdevice.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>

#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/cp_intc.h>
#include <mach/da8xx.h>
#include <linux/platform_data/mtd-davinci.h>
#include <mach/mux.h>
#include <linux/platform_data/spi-davinci.h>

#define MITYOMAPL138_PHY_ID		""

#define FACTORY_CONFIG_MAGIC	0x012C0138
#define FACTORY_CONFIG_VERSION	0x00010001

/* Data Held in On-Board I2C device */
struct factory_config {
	u32	magic;
	u32	version;
	u8	mac[6];
	u32	fpga_type;
	u32	spare;
	u32	serialnumber;
	char	partnum[32];
};

static struct factory_config factory_config;

struct part_no_info {
	const char	*part_no;	/* part number string of interest */
	int		max_freq;	/* khz */
};

static struct part_no_info mityomapl138_pn_info[] = {
	{
		.part_no	= "L138-C",
		.max_freq	= 300000,
	},
	{
		.part_no	= "L138-D",
		.max_freq	= 375000,
	},
	{
		.part_no	= "L138-F",
		.max_freq	= 456000,
	},
	{
		.part_no	= "1808-C",
		.max_freq	= 300000,
	},
	{
		.part_no	= "1808-D",
		.max_freq	= 375000,
	},
	{
		.part_no	= "1808-F",
		.max_freq	= 456000,
	},
	{
		.part_no	= "1810-D",
		.max_freq	= 375000,
	},
};

#ifdef CONFIG_CPU_FREQ
static void mityomapl138_cpufreq_init(const char *partnum)
{
	int i, ret;

	for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
		/*
		 * the part number has additional characters beyond what is
		 * stored in the table.  This information is not needed for
		 * determining the speed grade, and would require several
		 * more table entries.  Only check the first N characters
		 * for a match.
		 */
		if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
			     strlen(mityomapl138_pn_info[i].part_no))) {
			da850_max_speed = mityomapl138_pn_info[i].max_freq;
			break;
		}
	}

	ret = da850_register_cpufreq("pll0_sysclk3");
	if (ret)
		pr_warning("cpufreq registration failed: %d\n", ret);
}
#else
static void mityomapl138_cpufreq_init(const char *partnum) { }
#endif

static void read_factory_config(struct memory_accessor *a, void *context)
{
	int ret;
	const char *partnum = NULL;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	if (ret != sizeof(struct factory_config)) {
		pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
				ret);
		goto bad_config;
	}

	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
		pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
				factory_config.magic);
		goto bad_config;
	}

	if (factory_config.version != FACTORY_CONFIG_VERSION) {
		pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
				factory_config.version);
		goto bad_config;
	}

	pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
	if (is_valid_ether_addr(factory_config.mac))
		memcpy(soc_info->emac_pdata->mac_addr,
			factory_config.mac, ETH_ALEN);
	else
		pr_warning("MityOMAPL138: Invalid MAC found "
				"in factory config block\n");

	partnum = factory_config.partnum;
	pr_info("MityOMAPL138: Part Number = %s\n", partnum);

bad_config:
	/* default maximum speed is valid for all platforms */
	mityomapl138_cpufreq_init(partnum);
}

static struct at24_platform_data mityomapl138_fd_chip = {
	.byte_len	= 256,
	.page_size	= 8,
	.flags		= AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
	.setup		= read_factory_config,
	.context	= NULL,
};

static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	.bus_freq	= 100,	/* kHz */
	.bus_delay	= 0,	/* usec */
};

/* TPS65023 voltage regulator support */
/* 1.2V Core */
static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
	{
		.supply = "cvdd",
	},
};

/* 1.8V */
static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
	{
		.supply = "usb0_vdda18",
	},
	{
		.supply = "usb1_vdda18",
	},
	{
		.supply = "ddr_dvdd18",
	},
	{
		.supply = "sata_vddr",
	},
};

/* 1.2V */
static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
	{
		.supply = "sata_vdd",
	},
	{
		.supply = "usb_cvdd",
	},
	{
		.supply = "pll0_vdda",
	},
	{
		.supply = "pll1_vdda",
	},
};

/* 1.8V Aux LDO, not used */
static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
	{
		.supply = "1.8v_aux",
	},
};

/* FPGA VCC Aux (2.5 or 3.3) LDO */
static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
	{
		.supply = "vccaux",
	},
};

static struct regulator_init_data tps65023_regulator_data[] = {
	/* dcdc1 */
	{
		.constraints = {
			.min_uV = 1150000,
			.max_uV = 1350000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
		.consumer_supplies = tps65023_dcdc1_consumers,
	},
	/* dcdc2 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
		.consumer_supplies = tps65023_dcdc2_consumers,
	},
	/* dcdc3 */
	{
		.constraints = {
			.min_uV = 1200000,
			.max_uV = 1200000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
		.consumer_supplies = tps65023_dcdc3_consumers,
	},
	/* ldo1 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
		.consumer_supplies = tps65023_ldo1_consumers,
	},
	/* ldo2 */
	{
		.constraints = {
			.min_uV = 2500000,
			.max_uV = 3300000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
		.consumer_supplies = tps65023_ldo2_consumers,
	},
};

static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	{
		I2C_BOARD_INFO("tps65023", 0x48),
		.platform_data = &tps65023_regulator_data[0],
	},
	{
		I2C_BOARD_INFO("24c02", 0x50),
		.platform_data = &mityomapl138_fd_chip,
	},
};

static int __init pmic_tps65023_init(void)
{
	return i2c_register_board_info(1, mityomap_tps65023_info,
					ARRAY_SIZE(mityomap_tps65023_info));
}

/*
 * SPI Devices:
 *	SPI1_CS0: 8M Flash ST-M25P64-VME6G
 */
static struct mtd_partition spi_flash_partitions[] = {
	[0] = {
		.name		= "ubl",
		.offset		= 0,
		.size		= SZ_64K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[1] = {
		.name		= "u-boot",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_512K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[2] = {
		.name		= "u-boot-env",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_64K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[3] = {
		.name		= "periph-config",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_64K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[4] = {
		.name		= "reserved",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_256K + SZ_64K,
	},
	[5] = {
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_2M + SZ_1M,
	},
	[6] = {
		.name		= "fpga",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_2M,
	},
	[7] = {
		.name		= "spare",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
	},
};

static struct flash_platform_data mityomapl138_spi_flash_data = {
	.name		= "m25p80",
	.parts		= spi_flash_partitions,
	.nr_parts	= ARRAY_SIZE(spi_flash_partitions),
	.type		= "m24p64",
};

static struct davinci_spi_config spi_eprom_config = {
	.io_type	= SPI_IO_TYPE_DMA,
	.c2tdelay	= 8,
	.t2cdelay	= 8,
};

static struct spi_board_info mityomapl138_spi_flash_info[] = {
	{
		.modalias		= "m25p80",
		.platform_data		= &mityomapl138_spi_flash_data,
		.controller_data	= &spi_eprom_config,
		.mode			= SPI_MODE_0,
		.max_speed_hz		= 30000000,
		.bus_num		= 1,
		.chip_select		= 0,
	},
};

/*
 * MityDSP-L138 includes a 256 MByte large-page NAND flash
 * (128K blocks).
 */
static struct mtd_partition mityomapl138_nandflash_partition[] = {
	{
		.name		= "rootfs",
		.offset		= 0,
		.size		= SZ_128M,
		.mask_flags	= 0, /* MTD_WRITEABLE, */
	},
	{
		.name		= "homefs",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	},
};

static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	.parts		= mityomapl138_nandflash_partition,
	.nr_parts	= ARRAY_SIZE(mityomapl138_nandflash_partition),
	.ecc_mode	= NAND_ECC_HW,
	.bbt_options	= NAND_BBT_USE_FLASH,
	.options	= NAND_BUSWIDTH_16,
	.ecc_bits	= 1, /* 4 bit mode is not supported with 16 bit NAND */
};

static struct resource mityomapl138_nandflash_resource[] = {
	{
		.start	= DA8XX_AEMIF_CS3_BASE,
		.end	= DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= DA8XX_AEMIF_CTL_BASE,
		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mityomapl138_nandflash_device = {
	.name		= "davinci_nand",
	.id		= 1,
	.dev		= {
		.platform_data	= &mityomapl138_nandflash_data,
	},
	.num_resources	= ARRAY_SIZE(mityomapl138_nandflash_resource),
	.resource	= mityomapl138_nandflash_resource,
};

static struct platform_device *mityomapl138_devices[] __initdata = {
	&mityomapl138_nandflash_device,
};

static void __init mityomapl138_setup_nand(void)
{
	platform_add_devices(mityomapl138_devices,
				 ARRAY_SIZE(mityomapl138_devices));
}

static const short mityomap_mii_pins[] = {
	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static const short mityomap_rmii_pins[] = {
	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static void __init mityomapl138_config_emac(void)
{
	void __iomem *cfg_chip3_base;
	int ret;
	u32 val;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */

	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
	val = __raw_readl(cfg_chip3_base);

	if (soc_info->emac_pdata->rmii_en) {
		val |= BIT(8);
		ret = davinci_cfg_reg_list(mityomap_rmii_pins);
		pr_info("RMII PHY configured\n");
	} else {
		val &= ~BIT(8);
		ret = davinci_cfg_reg_list(mityomap_mii_pins);
		pr_info("MII PHY configured\n");
	}

	if (ret) {
		pr_warning("mii/rmii mux setup failed: %d\n", ret);
		return;
	}

	/* configure the CFGCHIP3 register for RMII or MII */
	__raw_writel(val, cfg_chip3_base);

	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;

	ret = da8xx_register_emac();
	if (ret)
		pr_warning("emac registration failed: %d\n", ret);
}

static struct davinci_pm_config da850_pm_pdata = {
	.sleepcount = 128,
};

static struct platform_device da850_pm_device = {
	.name	= "pm-davinci",
	.dev = {
		.platform_data  = &da850_pm_pdata,
	},
	.id	= -1,
};

static void __init mityomapl138_init(void)
{
	int ret;

	/* for now, no special EDMA channels are reserved */
	ret = da850_register_edma(NULL);
	if (ret)
		pr_warning("edma registration failed: %d\n", ret);

	ret = da8xx_register_watchdog();
	if (ret)
		pr_warning("watchdog registration failed: %d\n", ret);

	davinci_serial_init(da8xx_serial_device);

	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	if (ret)
		pr_warning("i2c0 registration failed: %d\n", ret);

	ret = pmic_tps65023_init();
	if (ret)
		pr_warning("TPS65023 PMIC init failed: %d\n", ret);

	mityomapl138_setup_nand();

	ret = spi_register_board_info(mityomapl138_spi_flash_info,
				      ARRAY_SIZE(mityomapl138_spi_flash_info));
	if (ret)
		pr_warn("spi info registration failed: %d\n", ret);

	ret = da8xx_register_spi_bus(1,
				     ARRAY_SIZE(mityomapl138_spi_flash_info));
	if (ret)
		pr_warning("spi 1 registration failed: %d\n", ret);

	mityomapl138_config_emac();

	ret = da8xx_register_rtc();
	if (ret)
		pr_warning("rtc setup failed: %d\n", ret);

	ret = da8xx_register_cpuidle();
	if (ret)
		pr_warning("cpuidle registration failed: %d\n", ret);

	ret = da850_register_pm(&da850_pm_device);
	if (ret)
		pr_warning("da850_evm_init: suspend registration failed: %d\n",
				ret);
}

#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init mityomapl138_console_init(void)
{
	if (!machine_is_mityomapl138())
		return 0;

	return add_preferred_console("ttyS", 1, "115200");
}
console_initcall(mityomapl138_console_init);
#endif

static void __init mityomapl138_map_io(void)
{
	da850_init();
}

MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
	.atag_offset	= 0x100,
	.map_io		= mityomapl138_map_io,
	.init_irq	= cp_intc_init,
	.init_time	= davinci_timer_init,
	.init_machine	= mityomapl138_init,
	.init_late	= davinci_init_late,
	.dma_zone_size	= SZ_128M,
	.restart	= da8xx_restart,
MACHINE_END
Commit	Line	Data
f2dbb6d9 MW	1	/*
	2	* Critical Link MityOMAP-L138 SoM
	3	*
	4	* Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of
	8	* any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/console.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/mtd/partitions.h>
87748823 MW	16	#include <linux/regulator/machine.h>
87748823 MW	17	#include <linux/i2c.h>
25f73ed5	18	#include <linux/platform_data/at24.h>
2a7dae04	19	#include <linux/etherdevice.h>
dd561c6a MW	20	#include <linux/spi/spi.h>
dd561c6a MW	21	#include <linux/spi/flash.h>
f2dbb6d9	22
b7f080cf	23	#include <asm/io.h>
f2dbb6d9 MW	24	#include <asm/mach-types.h>
	25	#include <asm/mach/arch.h>
	26	#include <mach/common.h>
	27	#include <mach/cp_intc.h>
	28	#include <mach/da8xx.h>
ec2a0833	29	#include <linux/platform_data/mtd-davinci.h>
f2dbb6d9	30	#include <mach/mux.h>
ec2a0833	31	#include <linux/platform_data/spi-davinci.h>
f2dbb6d9	32
336f4027	33	#define MITYOMAPL138_PHY_ID ""
2a7dae04 MW	34
	35	#define FACTORY_CONFIG_MAGIC 0x012C0138
	36	#define FACTORY_CONFIG_VERSION 0x00010001
	37
	38	/* Data Held in On-Board I2C device */
	39	struct factory_config {
	40	u32 magic;
	41	u32 version;
	42	u8 mac[6];
	43	u32 fpga_type;
	44	u32 spare;
	45	u32 serialnumber;
	46	char partnum[32];
	47	};
	48
	49	static struct factory_config factory_config;
	50
6619490a MW	51	struct part_no_info {
	52	const char part_no; / part number string of interest */
	53	int max_freq; /* khz */
	54	};
	55
	56	static struct part_no_info mityomapl138_pn_info[] = {
	57	{
	58	.part_no = "L138-C",
	59	.max_freq = 300000,
	60	},
	61	{
	62	.part_no = "L138-D",
	63	.max_freq = 375000,
	64	},
	65	{
	66	.part_no = "L138-F",
	67	.max_freq = 456000,
	68	},
	69	{
	70	.part_no = "1808-C",
	71	.max_freq = 300000,
	72	},
	73	{
	74	.part_no = "1808-D",
	75	.max_freq = 375000,
	76	},
	77	{
	78	.part_no = "1808-F",
	79	.max_freq = 456000,
	80	},
	81	{
	82	.part_no = "1810-D",
	83	.max_freq = 375000,
	84	},
	85	};
	86
	87	#ifdef CONFIG_CPU_FREQ
	88	static void mityomapl138_cpufreq_init(const char *partnum)
	89	{
	90	int i, ret;
	91
	92	for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
	93	/*
	94	* the part number has additional characters beyond what is
	95	* stored in the table. This information is not needed for
	96	* determining the speed grade, and would require several
	97	* more table entries. Only check the first N characters
	98	* for a match.
	99	*/
	100	if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
	101	strlen(mityomapl138_pn_info[i].part_no))) {
	102	da850_max_speed = mityomapl138_pn_info[i].max_freq;
	103	break;
	104	}
	105	}
	106
	107	ret = da850_register_cpufreq("pll0_sysclk3");
	108	if (ret)
	109	pr_warning("cpufreq registration failed: %d\n", ret);
	110	}
	111	#else
	112	static void mityomapl138_cpufreq_init(const char *partnum) { }
	113	#endif
	114
2a7dae04 MW	115	static void read_factory_config(struct memory_accessor a, void context)
	116	{
	117	int ret;
6619490a	118	const char *partnum = NULL;
2a7dae04 MW	119	struct davinci_soc_info *soc_info = &davinci_soc_info;
	120
	121	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	122	if (ret != sizeof(struct factory_config)) {
	123	pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
	124	ret);
6619490a	125	goto bad_config;
2a7dae04 MW	126	}
	127
	128	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
	129	pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
	130	factory_config.magic);
6619490a	131	goto bad_config;
2a7dae04 MW	132	}
	133
	134	if (factory_config.version != FACTORY_CONFIG_VERSION) {
	135	pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
	136	factory_config.version);
6619490a	137	goto bad_config;
2a7dae04 MW	138	}
	139
	140	pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
2a7dae04 MW	141	if (is_valid_ether_addr(factory_config.mac))
	142	memcpy(soc_info->emac_pdata->mac_addr,
	143	factory_config.mac, ETH_ALEN);
	144	else
	145	pr_warning("MityOMAPL138: Invalid MAC found "
	146	"in factory config block\n");
6619490a MW	147
	148	partnum = factory_config.partnum;
	149	pr_info("MityOMAPL138: Part Number = %s\n", partnum);
	150
	151	bad_config:
	152	/* default maximum speed is valid for all platforms */
	153	mityomapl138_cpufreq_init(partnum);
2a7dae04 MW	154	}
	155
	156	static struct at24_platform_data mityomapl138_fd_chip = {
	157	.byte_len = 256,
	158	.page_size = 8,
	159	.flags = AT24_FLAG_READONLY \| AT24_FLAG_IRUGO,
	160	.setup = read_factory_config,
	161	.context = NULL,
	162	};
	163
87748823 MW	164	static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	165	.bus_freq = 100, /* kHz */
	166	.bus_delay = 0, /* usec */
	167	};
	168
	169	/* TPS65023 voltage regulator support */
	170	/* 1.2V Core */
8939b350	171	static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
87748823 MW	172	{
	173	.supply = "cvdd",
	174	},
	175	};
	176
	177	/* 1.8V */
8939b350	178	static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
87748823 MW	179	{
	180	.supply = "usb0_vdda18",
	181	},
	182	{
	183	.supply = "usb1_vdda18",
	184	},
	185	{
	186	.supply = "ddr_dvdd18",
	187	},
	188	{
	189	.supply = "sata_vddr",
	190	},
	191	};
	192
	193	/* 1.2V */
8939b350	194	static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
87748823 MW	195	{
	196	.supply = "sata_vdd",
	197	},
	198	{
	199	.supply = "usb_cvdd",
	200	},
	201	{
	202	.supply = "pll0_vdda",
	203	},
	204	{
	205	.supply = "pll1_vdda",
	206	},
	207	};
	208
	209	/* 1.8V Aux LDO, not used */
8939b350	210	static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
87748823 MW	211	{
	212	.supply = "1.8v_aux",
	213	},
	214	};
	215
	216	/* FPGA VCC Aux (2.5 or 3.3) LDO */
8939b350	217	static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
87748823 MW	218	{
	219	.supply = "vccaux",
	220	},
	221	};
	222
8939b350	223	static struct regulator_init_data tps65023_regulator_data[] = {
87748823 MW	224	/* dcdc1 */
	225	{
	226	.constraints = {
	227	.min_uV = 1150000,
	228	.max_uV = 1350000,
	229	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	230	REGULATOR_CHANGE_STATUS,
	231	.boot_on = 1,
	232	},
	233	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
	234	.consumer_supplies = tps65023_dcdc1_consumers,
	235	},
	236	/* dcdc2 */
	237	{
	238	.constraints = {
	239	.min_uV = 1800000,
	240	.max_uV = 1800000,
	241	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	242	.boot_on = 1,
	243	},
	244	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
	245	.consumer_supplies = tps65023_dcdc2_consumers,
	246	},
	247	/* dcdc3 */
	248	{
	249	.constraints = {
	250	.min_uV = 1200000,
	251	.max_uV = 1200000,
	252	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	253	.boot_on = 1,
	254	},
	255	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
	256	.consumer_supplies = tps65023_dcdc3_consumers,
	257	},
	258	/* ldo1 */
	259	{
	260	.constraints = {
	261	.min_uV = 1800000,
	262	.max_uV = 1800000,
	263	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	264	.boot_on = 1,
	265	},
	266	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
	267	.consumer_supplies = tps65023_ldo1_consumers,
	268	},
	269	/* ldo2 */
	270	{
	271	.constraints = {
	272	.min_uV = 2500000,
	273	.max_uV = 3300000,
	274	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	275	REGULATOR_CHANGE_STATUS,
	276	.boot_on = 1,
	277	},
	278	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
	279	.consumer_supplies = tps65023_ldo2_consumers,
	280	},
	281	};
	282
	283	static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	284	{
	285	I2C_BOARD_INFO("tps65023", 0x48),
	286	.platform_data = &tps65023_regulator_data[0],
	287	},
288	{
289	I2C_BOARD_INFO("24c02", 0x50),
2a7dae04	290	.platform_data = &mityomapl138_fd_chip,
87748823 MW	291	},
	292	};
	293
	294	static int __init pmic_tps65023_init(void)
	295	{
	296	return i2c_register_board_info(1, mityomap_tps65023_info,
	297	ARRAY_SIZE(mityomap_tps65023_info));
	298	}
	299
dd561c6a MW	300	/*
	301	* SPI Devices:
	302	* SPI1_CS0: 8M Flash ST-M25P64-VME6G
	303	*/
	304	static struct mtd_partition spi_flash_partitions[] = {
	305	[0] = {
	306	.name = "ubl",
	307	.offset = 0,
	308	.size = SZ_64K,
	309	.mask_flags = MTD_WRITEABLE,
	310	},
	311	[1] = {
	312	.name = "u-boot",
	313	.offset = MTDPART_OFS_APPEND,
	314	.size = SZ_512K,
	315	.mask_flags = MTD_WRITEABLE,
	316	},
	317	[2] = {
	318	.name = "u-boot-env",
	319	.offset = MTDPART_OFS_APPEND,
	320	.size = SZ_64K,
	321	.mask_flags = MTD_WRITEABLE,
	322	},
	323	[3] = {
	324	.name = "periph-config",
	325	.offset = MTDPART_OFS_APPEND,
	326	.size = SZ_64K,
	327	.mask_flags = MTD_WRITEABLE,
	328	},
	329	[4] = {
	330	.name = "reserved",
	331	.offset = MTDPART_OFS_APPEND,
	332	.size = SZ_256K + SZ_64K,
	333	},
	334	[5] = {
	335	.name = "kernel",
	336	.offset = MTDPART_OFS_APPEND,
	337	.size = SZ_2M + SZ_1M,
	338	},
	339	[6] = {
	340	.name = "fpga",
	341	.offset = MTDPART_OFS_APPEND,
	342	.size = SZ_2M,
	343	},
	344	[7] = {
	345	.name = "spare",
	346	.offset = MTDPART_OFS_APPEND,
	347	.size = MTDPART_SIZ_FULL,
	348	},
	349	};
	350
	351	static struct flash_platform_data mityomapl138_spi_flash_data = {
	352	.name = "m25p80",
	353	.parts = spi_flash_partitions,
	354	.nr_parts = ARRAY_SIZE(spi_flash_partitions),
	355	.type = "m24p64",
	356	};
	357
	358	static struct davinci_spi_config spi_eprom_config = {
	359	.io_type = SPI_IO_TYPE_DMA,
	360	.c2tdelay = 8,
	361	.t2cdelay = 8,
	362	};
	363
364	static struct spi_board_info mityomapl138_spi_flash_info[] = {
365	{
366	.modalias = "m25p80",
367	.platform_data = &mityomapl138_spi_flash_data,
368	.controller_data = &spi_eprom_config,
369	.mode = SPI_MODE_0,
370	.max_speed_hz = 30000000,
371	.bus_num = 1,
372	.chip_select = 0,
373	},
374	};
375
f2dbb6d9 MW	376	/*
	377	* MityDSP-L138 includes a 256 MByte large-page NAND flash
	378	* (128K blocks).
	379	*/
8939b350	380	static struct mtd_partition mityomapl138_nandflash_partition[] = {
f2dbb6d9 MW	381	{
	382	.name = "rootfs",
	383	.offset = 0,
	384	.size = SZ_128M,
	385	.mask_flags = 0, /* MTD_WRITEABLE, */
	386	},
	387	{
	388	.name = "homefs",
	389	.offset = MTDPART_OFS_APPEND,
	390	.size = MTDPART_SIZ_FULL,
	391	.mask_flags = 0,
	392	},
	393	};
	394
	395	static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	396	.parts = mityomapl138_nandflash_partition,
	397	.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
	398	.ecc_mode = NAND_ECC_HW,
bb9ebd4e	399	.bbt_options = NAND_BBT_USE_FLASH,
a40f7341	400	.options = NAND_BUSWIDTH_16,
f2dbb6d9 MW	401	.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
	402	};
	403
	404	static struct resource mityomapl138_nandflash_resource[] = {
	405	{
	406	.start = DA8XX_AEMIF_CS3_BASE,
	407	.end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
	408	.flags = IORESOURCE_MEM,
	409	},
	410	{
	411	.start = DA8XX_AEMIF_CTL_BASE,
	412	.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
	413	.flags = IORESOURCE_MEM,
	414	},
	415	};
	416
	417	static struct platform_device mityomapl138_nandflash_device = {
	418	.name = "davinci_nand",
ad10e105	419	.id = 1,
f2dbb6d9 MW	420	.dev = {
	421	.platform_data = &mityomapl138_nandflash_data,
	422	},
	423	.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
	424	.resource = mityomapl138_nandflash_resource,
	425	};
	426
	427	static struct platform_device *mityomapl138_devices[] __initdata = {
	428	&mityomapl138_nandflash_device,
	429	};
	430
	431	static void __init mityomapl138_setup_nand(void)
	432	{
	433	platform_add_devices(mityomapl138_devices,
	434	ARRAY_SIZE(mityomapl138_devices));
	435	}
	436
f2dbb6d9 MW	437	static const short mityomap_mii_pins[] = {
	438	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	439	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	440	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	441	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
	442	DA850_MDIO_D,
	443	-1
	444	};
	445
	446	static const short mityomap_rmii_pins[] = {
	447	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
	448	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
	449	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
	450	DA850_MDIO_D,
	451	-1
	452	};
	453
	454	static void __init mityomapl138_config_emac(void)
	455	{
	456	void __iomem *cfg_chip3_base;
	457	int ret;
	458	u32 val;
	459	struct davinci_soc_info *soc_info = &davinci_soc_info;
	460
	461	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
	462
	463	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
	464	val = __raw_readl(cfg_chip3_base);
	465
	466	if (soc_info->emac_pdata->rmii_en) {
	467	val \|= BIT(8);
	468	ret = davinci_cfg_reg_list(mityomap_rmii_pins);
	469	pr_info("RMII PHY configured\n");
	470	} else {
	471	val &= ~BIT(8);
	472	ret = davinci_cfg_reg_list(mityomap_mii_pins);
	473	pr_info("MII PHY configured\n");
	474	}
	475
	476	if (ret) {
	477	pr_warning("mii/rmii mux setup failed: %d\n", ret);
	478	return;
	479	}
	480
	481	/* configure the CFGCHIP3 register for RMII or MII */
	482	__raw_writel(val, cfg_chip3_base);
	483
782f2d78	484	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
f2dbb6d9 MW	485
	486	ret = da8xx_register_emac();
	487	if (ret)
	488	pr_warning("emac registration failed: %d\n", ret);
	489	}
	490
	491	static struct davinci_pm_config da850_pm_pdata = {
	492	.sleepcount = 128,
	493	};
	494
	495	static struct platform_device da850_pm_device = {
	496	.name = "pm-davinci",
	497	.dev = {
	498	.platform_data = &da850_pm_pdata,
	499	},
	500	.id = -1,
	501	};
	502
	503	static void __init mityomapl138_init(void)
	504	{
	505	int ret;
	506
	507	/* for now, no special EDMA channels are reserved */
	508	ret = da850_register_edma(NULL);
	509	if (ret)
	510	pr_warning("edma registration failed: %d\n", ret);
	511
	512	ret = da8xx_register_watchdog();
	513	if (ret)
	514	pr_warning("watchdog registration failed: %d\n", ret);
	515
fcf7157b	516	davinci_serial_init(da8xx_serial_device);
f2dbb6d9	517
87748823 MW	518	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	519	if (ret)
	520	pr_warning("i2c0 registration failed: %d\n", ret);
	521
	522	ret = pmic_tps65023_init();
	523	if (ret)
	524	pr_warning("TPS65023 PMIC init failed: %d\n", ret);
	525
f2dbb6d9 MW	526	mityomapl138_setup_nand();
f2dbb6d9 MW	527
0273612c VD	528	ret = spi_register_board_info(mityomapl138_spi_flash_info,
	529	ARRAY_SIZE(mityomapl138_spi_flash_info));
	530	if (ret)
	531	pr_warn("spi info registration failed: %d\n", ret);
	532
	533	ret = da8xx_register_spi_bus(1,
	534	ARRAY_SIZE(mityomapl138_spi_flash_info));
dd561c6a MW	535	if (ret)
	536	pr_warning("spi 1 registration failed: %d\n", ret);
	537
f2dbb6d9 MW	538	mityomapl138_config_emac();
	539
	540	ret = da8xx_register_rtc();
	541	if (ret)
	542	pr_warning("rtc setup failed: %d\n", ret);
	543
f2dbb6d9 MW	544	ret = da8xx_register_cpuidle();
	545	if (ret)
	546	pr_warning("cpuidle registration failed: %d\n", ret);
	547
	548	ret = da850_register_pm(&da850_pm_device);
	549	if (ret)
	550	pr_warning("da850_evm_init: suspend registration failed: %d\n",
	551	ret);
	552	}
	553
	554	#ifdef CONFIG_SERIAL_8250_CONSOLE
	555	static int __init mityomapl138_console_init(void)
	556	{
	557	if (!machine_is_mityomapl138())
	558	return 0;
	559
	560	return add_preferred_console("ttyS", 1, "115200");
	561	}
	562	console_initcall(mityomapl138_console_init);
	563	#endif
	564
	565	static void __init mityomapl138_map_io(void)
	566	{
	567	da850_init();
	568	}
	569
	570	MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
e7e56014	571	.atag_offset = 0x100,
f2dbb6d9 MW	572	.map_io = mityomapl138_map_io,
f2dbb6d9 MW	573	.init_irq = cp_intc_init,
6bb27d73	574	.init_time = davinci_timer_init,
f2dbb6d9	575	.init_machine = mityomapl138_init,
3aa3e840	576	.init_late = davinci_init_late,
f68deabf	577	.dma_zone_size = SZ_128M,
c6121ddd	578	.restart = da8xx_restart,
f2dbb6d9	579	MACHINE_END