[linux-2.6-block.git] / arch / arm / mach-davinci / board-mityomapl138.c

/*
 * Critical Link MityOMAP-L138 SoM
 *
 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of
 * any kind, whether express or implied.
 */

#define pr_fmt(fmt) "MityOMAPL138: " fmt

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/platform_data/at24.h>
#include <linux/etherdevice.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>

#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/cp_intc.h>
#include <mach/da8xx.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <mach/mux.h>
#include <linux/platform_data/spi-davinci.h>

#define MITYOMAPL138_PHY_ID		""

#define FACTORY_CONFIG_MAGIC	0x012C0138
#define FACTORY_CONFIG_VERSION	0x00010001

/* Data Held in On-Board I2C device */
struct factory_config {
	u32	magic;
	u32	version;
	u8	mac[6];
	u32	fpga_type;
	u32	spare;
	u32	serialnumber;
	char	partnum[32];
};

static struct factory_config factory_config;

struct part_no_info {
	const char	*part_no;	/* part number string of interest */
	int		max_freq;	/* khz */
};

static struct part_no_info mityomapl138_pn_info[] = {
	{
		.part_no	= "L138-C",
		.max_freq	= 300000,
	},
	{
		.part_no	= "L138-D",
		.max_freq	= 375000,
	},
	{
		.part_no	= "L138-F",
		.max_freq	= 456000,
	},
	{
		.part_no	= "1808-C",
		.max_freq	= 300000,
	},
	{
		.part_no	= "1808-D",
		.max_freq	= 375000,
	},
	{
		.part_no	= "1808-F",
		.max_freq	= 456000,
	},
	{
		.part_no	= "1810-D",
		.max_freq	= 375000,
	},
};

#ifdef CONFIG_CPU_FREQ
static void mityomapl138_cpufreq_init(const char *partnum)
{
	int i, ret;

	for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
		/*
		 * the part number has additional characters beyond what is
		 * stored in the table.  This information is not needed for
		 * determining the speed grade, and would require several
		 * more table entries.  Only check the first N characters
		 * for a match.
		 */
		if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
			     strlen(mityomapl138_pn_info[i].part_no))) {
			da850_max_speed = mityomapl138_pn_info[i].max_freq;
			break;
		}
	}

	ret = da850_register_cpufreq("pll0_sysclk3");
	if (ret)
		pr_warn("cpufreq registration failed: %d\n", ret);
}
#else
static void mityomapl138_cpufreq_init(const char *partnum) { }
#endif

static void read_factory_config(struct memory_accessor *a, void *context)
{
	int ret;
	const char *partnum = NULL;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	if (ret != sizeof(struct factory_config)) {
		pr_warn("Read Factory Config Failed: %d\n", ret);
		goto bad_config;
	}

	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
		pr_warn("Factory Config Magic Wrong (%X)\n",
			factory_config.magic);
		goto bad_config;
	}

	if (factory_config.version != FACTORY_CONFIG_VERSION) {
		pr_warn("Factory Config Version Wrong (%X)\n",
			factory_config.version);
		goto bad_config;
	}

	pr_info("Found MAC = %pM\n", factory_config.mac);
	if (is_valid_ether_addr(factory_config.mac))
		memcpy(soc_info->emac_pdata->mac_addr,
			factory_config.mac, ETH_ALEN);
	else
		pr_warn("Invalid MAC found in factory config block\n");

	partnum = factory_config.partnum;
	pr_info("Part Number = %s\n", partnum);

bad_config:
	/* default maximum speed is valid for all platforms */
	mityomapl138_cpufreq_init(partnum);
}

static struct at24_platform_data mityomapl138_fd_chip = {
	.byte_len	= 256,
	.page_size	= 8,
	.flags		= AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
	.setup		= read_factory_config,
	.context	= NULL,
};

static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	.bus_freq	= 100,	/* kHz */
	.bus_delay	= 0,	/* usec */
};

/* TPS65023 voltage regulator support */
/* 1.2V Core */
static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
	{
		.supply = "cvdd",
	},
};

/* 1.8V */
static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
	{
		.supply = "usb0_vdda18",
	},
	{
		.supply = "usb1_vdda18",
	},
	{
		.supply = "ddr_dvdd18",
	},
	{
		.supply = "sata_vddr",
	},
};

/* 1.2V */
static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
	{
		.supply = "sata_vdd",
	},
	{
		.supply = "usb_cvdd",
	},
	{
		.supply = "pll0_vdda",
	},
	{
		.supply = "pll1_vdda",
	},
};

/* 1.8V Aux LDO, not used */
static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
	{
		.supply = "1.8v_aux",
	},
};

/* FPGA VCC Aux (2.5 or 3.3) LDO */
static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
	{
		.supply = "vccaux",
	},
};

static struct regulator_init_data tps65023_regulator_data[] = {
	/* dcdc1 */
	{
		.constraints = {
			.min_uV = 1150000,
			.max_uV = 1350000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
		.consumer_supplies = tps65023_dcdc1_consumers,
	},
	/* dcdc2 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
		.consumer_supplies = tps65023_dcdc2_consumers,
	},
	/* dcdc3 */
	{
		.constraints = {
			.min_uV = 1200000,
			.max_uV = 1200000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
		.consumer_supplies = tps65023_dcdc3_consumers,
	},
	/* ldo1 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
		.consumer_supplies = tps65023_ldo1_consumers,
	},
	/* ldo2 */
	{
		.constraints = {
			.min_uV = 2500000,
			.max_uV = 3300000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
		.consumer_supplies = tps65023_ldo2_consumers,
	},
};

static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	{
		I2C_BOARD_INFO("tps65023", 0x48),
		.platform_data = &tps65023_regulator_data[0],
	},
	{
		I2C_BOARD_INFO("24c02", 0x50),
		.platform_data = &mityomapl138_fd_chip,
	},
};

static int __init pmic_tps65023_init(void)
{
	return i2c_register_board_info(1, mityomap_tps65023_info,
					ARRAY_SIZE(mityomap_tps65023_info));
}

/*
 * SPI Devices:
 *	SPI1_CS0: 8M Flash ST-M25P64-VME6G
 */
static struct mtd_partition spi_flash_partitions[] = {
	[0] = {
		.name		= "ubl",
		.offset		= 0,
		.size		= SZ_64K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[1] = {
		.name		= "u-boot",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_512K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[2] = {
		.name		= "u-boot-env",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_64K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[3] = {
		.name		= "periph-config",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_64K,
		.mask_flags	= MTD_WRITEABLE,
	},
	[4] = {
		.name		= "reserved",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_256K + SZ_64K,
	},
	[5] = {
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_2M + SZ_1M,
	},
	[6] = {
		.name		= "fpga",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_2M,
	},
	[7] = {
		.name		= "spare",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
	},
};

static struct flash_platform_data mityomapl138_spi_flash_data = {
	.name		= "m25p80",
	.parts		= spi_flash_partitions,
	.nr_parts	= ARRAY_SIZE(spi_flash_partitions),
	.type		= "m24p64",
};

static struct davinci_spi_config spi_eprom_config = {
	.io_type	= SPI_IO_TYPE_DMA,
	.c2tdelay	= 8,
	.t2cdelay	= 8,
};

static struct spi_board_info mityomapl138_spi_flash_info[] = {
	{
		.modalias		= "m25p80",
		.platform_data		= &mityomapl138_spi_flash_data,
		.controller_data	= &spi_eprom_config,
		.mode			= SPI_MODE_0,
		.max_speed_hz		= 30000000,
		.bus_num		= 1,
		.chip_select		= 0,
	},
};

/*
 * MityDSP-L138 includes a 256 MByte large-page NAND flash
 * (128K blocks).
 */
static struct mtd_partition mityomapl138_nandflash_partition[] = {
	{
		.name		= "rootfs",
		.offset		= 0,
		.size		= SZ_128M,
		.mask_flags	= 0, /* MTD_WRITEABLE, */
	},
	{
		.name		= "homefs",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	},
};

static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	.parts		= mityomapl138_nandflash_partition,
	.nr_parts	= ARRAY_SIZE(mityomapl138_nandflash_partition),
	.ecc_mode	= NAND_ECC_HW,
	.bbt_options	= NAND_BBT_USE_FLASH,
	.options	= NAND_BUSWIDTH_16,
	.ecc_bits	= 1, /* 4 bit mode is not supported with 16 bit NAND */
};

static struct resource mityomapl138_nandflash_resource[] = {
	{
		.start	= DA8XX_AEMIF_CS3_BASE,
		.end	= DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= DA8XX_AEMIF_CTL_BASE,
		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mityomapl138_nandflash_device = {
	.name		= "davinci_nand",
	.id		= 1,
	.dev		= {
		.platform_data	= &mityomapl138_nandflash_data,
	},
	.num_resources	= ARRAY_SIZE(mityomapl138_nandflash_resource),
	.resource	= mityomapl138_nandflash_resource,
};

static struct platform_device *mityomapl138_devices[] __initdata = {
	&mityomapl138_nandflash_device,
};

static void __init mityomapl138_setup_nand(void)
{
	platform_add_devices(mityomapl138_devices,
				 ARRAY_SIZE(mityomapl138_devices));

	if (davinci_aemif_setup(&mityomapl138_nandflash_device))
		pr_warn("%s: Cannot configure AEMIF\n", __func__);
}

static const short mityomap_mii_pins[] = {
	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static const short mityomap_rmii_pins[] = {
	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static void __init mityomapl138_config_emac(void)
{
	void __iomem *cfg_chip3_base;
	int ret;
	u32 val;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */

	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
	val = __raw_readl(cfg_chip3_base);

	if (soc_info->emac_pdata->rmii_en) {
		val |= BIT(8);
		ret = davinci_cfg_reg_list(mityomap_rmii_pins);
		pr_info("RMII PHY configured\n");
	} else {
		val &= ~BIT(8);
		ret = davinci_cfg_reg_list(mityomap_mii_pins);
		pr_info("MII PHY configured\n");
	}

	if (ret) {
		pr_warn("mii/rmii mux setup failed: %d\n", ret);
		return;
	}

	/* configure the CFGCHIP3 register for RMII or MII */
	__raw_writel(val, cfg_chip3_base);

	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;

	ret = da8xx_register_emac();
	if (ret)
		pr_warn("emac registration failed: %d\n", ret);
}

static struct davinci_pm_config da850_pm_pdata = {
	.sleepcount = 128,
};

static struct platform_device da850_pm_device = {
	.name	= "pm-davinci",
	.dev = {
		.platform_data  = &da850_pm_pdata,
	},
	.id	= -1,
};

static void __init mityomapl138_init(void)
{
	int ret;

	/* for now, no special EDMA channels are reserved */
	ret = da850_register_edma(NULL);
	if (ret)
		pr_warn("edma registration failed: %d\n", ret);

	ret = da8xx_register_watchdog();
	if (ret)
		pr_warn("watchdog registration failed: %d\n", ret);

	davinci_serial_init(da8xx_serial_device);

	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	if (ret)
		pr_warn("i2c0 registration failed: %d\n", ret);

	ret = pmic_tps65023_init();
	if (ret)
		pr_warn("TPS65023 PMIC init failed: %d\n", ret);

	mityomapl138_setup_nand();

	ret = spi_register_board_info(mityomapl138_spi_flash_info,
				      ARRAY_SIZE(mityomapl138_spi_flash_info));
	if (ret)
		pr_warn("spi info registration failed: %d\n", ret);

	ret = da8xx_register_spi_bus(1,
				     ARRAY_SIZE(mityomapl138_spi_flash_info));
	if (ret)
		pr_warn("spi 1 registration failed: %d\n", ret);

	mityomapl138_config_emac();

	ret = da8xx_register_rtc();
	if (ret)
		pr_warn("rtc setup failed: %d\n", ret);

	ret = da8xx_register_cpuidle();
	if (ret)
		pr_warn("cpuidle registration failed: %d\n", ret);

	ret = da850_register_pm(&da850_pm_device);
	if (ret)
		pr_warn("suspend registration failed: %d\n", ret);
}

#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init mityomapl138_console_init(void)
{
	if (!machine_is_mityomapl138())
		return 0;

	return add_preferred_console("ttyS", 1, "115200");
}
console_initcall(mityomapl138_console_init);
#endif

static void __init mityomapl138_map_io(void)
{
	da850_init();
}

MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
	.atag_offset	= 0x100,
	.map_io		= mityomapl138_map_io,
	.init_irq	= cp_intc_init,
	.init_time	= davinci_timer_init,
	.init_machine	= mityomapl138_init,
	.init_late	= davinci_init_late,
	.dma_zone_size	= SZ_128M,
	.restart	= da8xx_restart,
MACHINE_END
Commit	Line	Data
f2dbb6d9 MW	1	/*
	2	* Critical Link MityOMAP-L138 SoM
	3	*
	4	* Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of
	8	* any kind, whether express or implied.
	9	*/
	10
a7ca2bcf JP	11	#define pr_fmt(fmt) "MityOMAPL138: " fmt
a7ca2bcf JP	12
f2dbb6d9 MW	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/console.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/mtd/partitions.h>
87748823 MW	18	#include <linux/regulator/machine.h>
87748823 MW	19	#include <linux/i2c.h>
25f73ed5	20	#include <linux/platform_data/at24.h>
2a7dae04	21	#include <linux/etherdevice.h>
dd561c6a MW	22	#include <linux/spi/spi.h>
dd561c6a MW	23	#include <linux/spi/flash.h>
f2dbb6d9	24
b7f080cf	25	#include <asm/io.h>
f2dbb6d9 MW	26	#include <asm/mach-types.h>
	27	#include <asm/mach/arch.h>
	28	#include <mach/common.h>
	29	#include <mach/cp_intc.h>
	30	#include <mach/da8xx.h>
ec2a0833	31	#include <linux/platform_data/mtd-davinci.h>
67f5185c	32	#include <linux/platform_data/mtd-davinci-aemif.h>
f2dbb6d9	33	#include <mach/mux.h>
ec2a0833	34	#include <linux/platform_data/spi-davinci.h>
f2dbb6d9	35
336f4027	36	#define MITYOMAPL138_PHY_ID ""
2a7dae04 MW	37
	38	#define FACTORY_CONFIG_MAGIC 0x012C0138
	39	#define FACTORY_CONFIG_VERSION 0x00010001
	40
	41	/* Data Held in On-Board I2C device */
	42	struct factory_config {
	43	u32 magic;
	44	u32 version;
	45	u8 mac[6];
	46	u32 fpga_type;
	47	u32 spare;
	48	u32 serialnumber;
	49	char partnum[32];
	50	};
	51
	52	static struct factory_config factory_config;
	53
6619490a MW	54	struct part_no_info {
	55	const char part_no; / part number string of interest */
	56	int max_freq; /* khz */
	57	};
	58
	59	static struct part_no_info mityomapl138_pn_info[] = {
	60	{
	61	.part_no = "L138-C",
	62	.max_freq = 300000,
	63	},
	64	{
	65	.part_no = "L138-D",
	66	.max_freq = 375000,
	67	},
	68	{
	69	.part_no = "L138-F",
	70	.max_freq = 456000,
	71	},
	72	{
	73	.part_no = "1808-C",
	74	.max_freq = 300000,
	75	},
	76	{
	77	.part_no = "1808-D",
	78	.max_freq = 375000,
	79	},
	80	{
	81	.part_no = "1808-F",
	82	.max_freq = 456000,
	83	},
	84	{
	85	.part_no = "1810-D",
	86	.max_freq = 375000,
	87	},
	88	};
	89
	90	#ifdef CONFIG_CPU_FREQ
	91	static void mityomapl138_cpufreq_init(const char *partnum)
	92	{
	93	int i, ret;
	94
	95	for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
	96	/*
	97	* the part number has additional characters beyond what is
	98	* stored in the table. This information is not needed for
	99	* determining the speed grade, and would require several
	100	* more table entries. Only check the first N characters
	101	* for a match.
	102	*/
	103	if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
	104	strlen(mityomapl138_pn_info[i].part_no))) {
	105	da850_max_speed = mityomapl138_pn_info[i].max_freq;
	106	break;
	107	}
	108	}
	109
	110	ret = da850_register_cpufreq("pll0_sysclk3");
	111	if (ret)
a7ca2bcf	112	pr_warn("cpufreq registration failed: %d\n", ret);
6619490a MW	113	}
	114	#else
	115	static void mityomapl138_cpufreq_init(const char *partnum) { }
	116	#endif
	117
2a7dae04 MW	118	static void read_factory_config(struct memory_accessor a, void context)
	119	{
	120	int ret;
6619490a	121	const char *partnum = NULL;
2a7dae04 MW	122	struct davinci_soc_info *soc_info = &davinci_soc_info;
	123
	124	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	125	if (ret != sizeof(struct factory_config)) {
a7ca2bcf	126	pr_warn("Read Factory Config Failed: %d\n", ret);
6619490a	127	goto bad_config;
2a7dae04 MW	128	}
	129
	130	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
a7ca2bcf JP	131	pr_warn("Factory Config Magic Wrong (%X)\n",
a7ca2bcf JP	132	factory_config.magic);
6619490a	133	goto bad_config;
2a7dae04 MW	134	}
	135
	136	if (factory_config.version != FACTORY_CONFIG_VERSION) {
a7ca2bcf JP	137	pr_warn("Factory Config Version Wrong (%X)\n",
a7ca2bcf JP	138	factory_config.version);
6619490a	139	goto bad_config;
2a7dae04 MW	140	}
2a7dae04 MW	141
a7ca2bcf	142	pr_info("Found MAC = %pM\n", factory_config.mac);
2a7dae04 MW	143	if (is_valid_ether_addr(factory_config.mac))
	144	memcpy(soc_info->emac_pdata->mac_addr,
	145	factory_config.mac, ETH_ALEN);
	146	else
a7ca2bcf	147	pr_warn("Invalid MAC found in factory config block\n");
6619490a MW	148
6619490a MW	149	partnum = factory_config.partnum;
a7ca2bcf	150	pr_info("Part Number = %s\n", partnum);
6619490a MW	151
	152	bad_config:
	153	/* default maximum speed is valid for all platforms */
	154	mityomapl138_cpufreq_init(partnum);
2a7dae04 MW	155	}
	156
	157	static struct at24_platform_data mityomapl138_fd_chip = {
	158	.byte_len = 256,
	159	.page_size = 8,
	160	.flags = AT24_FLAG_READONLY \| AT24_FLAG_IRUGO,
	161	.setup = read_factory_config,
	162	.context = NULL,
	163	};
	164
87748823 MW	165	static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	166	.bus_freq = 100, /* kHz */
	167	.bus_delay = 0, /* usec */
	168	};
	169
	170	/* TPS65023 voltage regulator support */
	171	/* 1.2V Core */
8939b350	172	static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
87748823 MW	173	{
	174	.supply = "cvdd",
	175	},
	176	};
	177
	178	/* 1.8V */
8939b350	179	static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
87748823 MW	180	{
	181	.supply = "usb0_vdda18",
	182	},
	183	{
	184	.supply = "usb1_vdda18",
	185	},
	186	{
	187	.supply = "ddr_dvdd18",
	188	},
	189	{
	190	.supply = "sata_vddr",
	191	},
	192	};
	193
	194	/* 1.2V */
8939b350	195	static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
87748823 MW	196	{
	197	.supply = "sata_vdd",
	198	},
	199	{
	200	.supply = "usb_cvdd",
	201	},
	202	{
	203	.supply = "pll0_vdda",
	204	},
	205	{
	206	.supply = "pll1_vdda",
	207	},
	208	};
	209
	210	/* 1.8V Aux LDO, not used */
8939b350	211	static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
87748823 MW	212	{
	213	.supply = "1.8v_aux",
	214	},
	215	};
	216
	217	/* FPGA VCC Aux (2.5 or 3.3) LDO */
8939b350	218	static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
87748823 MW	219	{
	220	.supply = "vccaux",
	221	},
	222	};
	223
8939b350	224	static struct regulator_init_data tps65023_regulator_data[] = {
87748823 MW	225	/* dcdc1 */
	226	{
	227	.constraints = {
	228	.min_uV = 1150000,
	229	.max_uV = 1350000,
	230	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	231	REGULATOR_CHANGE_STATUS,
	232	.boot_on = 1,
	233	},
	234	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
	235	.consumer_supplies = tps65023_dcdc1_consumers,
	236	},
	237	/* dcdc2 */
	238	{
	239	.constraints = {
	240	.min_uV = 1800000,
	241	.max_uV = 1800000,
	242	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	243	.boot_on = 1,
	244	},
	245	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
	246	.consumer_supplies = tps65023_dcdc2_consumers,
	247	},
	248	/* dcdc3 */
	249	{
	250	.constraints = {
	251	.min_uV = 1200000,
	252	.max_uV = 1200000,
	253	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	254	.boot_on = 1,
	255	},
	256	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
	257	.consumer_supplies = tps65023_dcdc3_consumers,
	258	},
	259	/* ldo1 */
	260	{
	261	.constraints = {
	262	.min_uV = 1800000,
	263	.max_uV = 1800000,
	264	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	265	.boot_on = 1,
	266	},
	267	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
	268	.consumer_supplies = tps65023_ldo1_consumers,
	269	},
	270	/* ldo2 */
	271	{
	272	.constraints = {
	273	.min_uV = 2500000,
	274	.max_uV = 3300000,
	275	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	276	REGULATOR_CHANGE_STATUS,
	277	.boot_on = 1,
	278	},
	279	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
	280	.consumer_supplies = tps65023_ldo2_consumers,
	281	},
	282	};
	283
	284	static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	285	{
	286	I2C_BOARD_INFO("tps65023", 0x48),
	287	.platform_data = &tps65023_regulator_data[0],
	288	},
289	{
290	I2C_BOARD_INFO("24c02", 0x50),
2a7dae04	291	.platform_data = &mityomapl138_fd_chip,
87748823 MW	292	},
	293	};
	294
	295	static int __init pmic_tps65023_init(void)
	296	{
	297	return i2c_register_board_info(1, mityomap_tps65023_info,
	298	ARRAY_SIZE(mityomap_tps65023_info));
	299	}
	300
dd561c6a MW	301	/*
	302	* SPI Devices:
	303	* SPI1_CS0: 8M Flash ST-M25P64-VME6G
	304	*/
	305	static struct mtd_partition spi_flash_partitions[] = {
	306	[0] = {
	307	.name = "ubl",
	308	.offset = 0,
	309	.size = SZ_64K,
	310	.mask_flags = MTD_WRITEABLE,
	311	},
	312	[1] = {
	313	.name = "u-boot",
	314	.offset = MTDPART_OFS_APPEND,
	315	.size = SZ_512K,
	316	.mask_flags = MTD_WRITEABLE,
	317	},
	318	[2] = {
	319	.name = "u-boot-env",
	320	.offset = MTDPART_OFS_APPEND,
	321	.size = SZ_64K,
	322	.mask_flags = MTD_WRITEABLE,
	323	},
	324	[3] = {
	325	.name = "periph-config",
	326	.offset = MTDPART_OFS_APPEND,
	327	.size = SZ_64K,
	328	.mask_flags = MTD_WRITEABLE,
	329	},
	330	[4] = {
	331	.name = "reserved",
	332	.offset = MTDPART_OFS_APPEND,
	333	.size = SZ_256K + SZ_64K,
	334	},
	335	[5] = {
	336	.name = "kernel",
	337	.offset = MTDPART_OFS_APPEND,
	338	.size = SZ_2M + SZ_1M,
	339	},
	340	[6] = {
	341	.name = "fpga",
	342	.offset = MTDPART_OFS_APPEND,
	343	.size = SZ_2M,
	344	},
	345	[7] = {
	346	.name = "spare",
	347	.offset = MTDPART_OFS_APPEND,
	348	.size = MTDPART_SIZ_FULL,
	349	},
	350	};
	351
	352	static struct flash_platform_data mityomapl138_spi_flash_data = {
	353	.name = "m25p80",
	354	.parts = spi_flash_partitions,
	355	.nr_parts = ARRAY_SIZE(spi_flash_partitions),
	356	.type = "m24p64",
	357	};
	358
	359	static struct davinci_spi_config spi_eprom_config = {
	360	.io_type = SPI_IO_TYPE_DMA,
	361	.c2tdelay = 8,
	362	.t2cdelay = 8,
	363	};
	364
365	static struct spi_board_info mityomapl138_spi_flash_info[] = {
366	{
367	.modalias = "m25p80",
368	.platform_data = &mityomapl138_spi_flash_data,
369	.controller_data = &spi_eprom_config,
370	.mode = SPI_MODE_0,
371	.max_speed_hz = 30000000,
372	.bus_num = 1,
373	.chip_select = 0,
374	},
375	};
376
f2dbb6d9 MW	377	/*
	378	* MityDSP-L138 includes a 256 MByte large-page NAND flash
	379	* (128K blocks).
	380	*/
8939b350	381	static struct mtd_partition mityomapl138_nandflash_partition[] = {
f2dbb6d9 MW	382	{
	383	.name = "rootfs",
	384	.offset = 0,
	385	.size = SZ_128M,
	386	.mask_flags = 0, /* MTD_WRITEABLE, */
	387	},
	388	{
	389	.name = "homefs",
	390	.offset = MTDPART_OFS_APPEND,
	391	.size = MTDPART_SIZ_FULL,
	392	.mask_flags = 0,
	393	},
	394	};
	395
	396	static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	397	.parts = mityomapl138_nandflash_partition,
	398	.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
	399	.ecc_mode = NAND_ECC_HW,
bb9ebd4e	400	.bbt_options = NAND_BBT_USE_FLASH,
a40f7341	401	.options = NAND_BUSWIDTH_16,
f2dbb6d9 MW	402	.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
	403	};
	404
	405	static struct resource mityomapl138_nandflash_resource[] = {
	406	{
	407	.start = DA8XX_AEMIF_CS3_BASE,
	408	.end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
	409	.flags = IORESOURCE_MEM,
	410	},
	411	{
	412	.start = DA8XX_AEMIF_CTL_BASE,
	413	.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
	414	.flags = IORESOURCE_MEM,
	415	},
	416	};
	417
	418	static struct platform_device mityomapl138_nandflash_device = {
	419	.name = "davinci_nand",
ad10e105	420	.id = 1,
f2dbb6d9 MW	421	.dev = {
	422	.platform_data = &mityomapl138_nandflash_data,
	423	},
	424	.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
	425	.resource = mityomapl138_nandflash_resource,
	426	};
	427
	428	static struct platform_device *mityomapl138_devices[] __initdata = {
	429	&mityomapl138_nandflash_device,
	430	};
	431
	432	static void __init mityomapl138_setup_nand(void)
	433	{
	434	platform_add_devices(mityomapl138_devices,
	435	ARRAY_SIZE(mityomapl138_devices));
67f5185c IK	436
67f5185c IK	437	if (davinci_aemif_setup(&mityomapl138_nandflash_device))
a7ca2bcf	438	pr_warn("%s: Cannot configure AEMIF\n", __func__);
f2dbb6d9 MW	439	}
f2dbb6d9 MW	440
f2dbb6d9 MW	441	static const short mityomap_mii_pins[] = {
	442	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	443	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	444	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	445	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
	446	DA850_MDIO_D,
	447	-1
	448	};
	449
	450	static const short mityomap_rmii_pins[] = {
	451	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
	452	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
	453	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
	454	DA850_MDIO_D,
	455	-1
	456	};
	457
	458	static void __init mityomapl138_config_emac(void)
	459	{
	460	void __iomem *cfg_chip3_base;
	461	int ret;
	462	u32 val;
	463	struct davinci_soc_info *soc_info = &davinci_soc_info;
	464
	465	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
	466
	467	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
	468	val = __raw_readl(cfg_chip3_base);
	469
	470	if (soc_info->emac_pdata->rmii_en) {
	471	val \|= BIT(8);
	472	ret = davinci_cfg_reg_list(mityomap_rmii_pins);
	473	pr_info("RMII PHY configured\n");
	474	} else {
	475	val &= ~BIT(8);
	476	ret = davinci_cfg_reg_list(mityomap_mii_pins);
	477	pr_info("MII PHY configured\n");
	478	}
	479
	480	if (ret) {
a7ca2bcf	481	pr_warn("mii/rmii mux setup failed: %d\n", ret);
f2dbb6d9 MW	482	return;
	483	}
	484
	485	/* configure the CFGCHIP3 register for RMII or MII */
	486	__raw_writel(val, cfg_chip3_base);
	487
782f2d78	488	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
f2dbb6d9 MW	489
	490	ret = da8xx_register_emac();
	491	if (ret)
a7ca2bcf	492	pr_warn("emac registration failed: %d\n", ret);
f2dbb6d9 MW	493	}
	494
	495	static struct davinci_pm_config da850_pm_pdata = {
	496	.sleepcount = 128,
	497	};
	498
	499	static struct platform_device da850_pm_device = {
	500	.name = "pm-davinci",
	501	.dev = {
	502	.platform_data = &da850_pm_pdata,
	503	},
	504	.id = -1,
	505	};
	506
	507	static void __init mityomapl138_init(void)
	508	{
	509	int ret;
	510
	511	/* for now, no special EDMA channels are reserved */
	512	ret = da850_register_edma(NULL);
	513	if (ret)
a7ca2bcf	514	pr_warn("edma registration failed: %d\n", ret);
f2dbb6d9 MW	515
	516	ret = da8xx_register_watchdog();
	517	if (ret)
a7ca2bcf	518	pr_warn("watchdog registration failed: %d\n", ret);
f2dbb6d9	519
fcf7157b	520	davinci_serial_init(da8xx_serial_device);
f2dbb6d9	521
87748823 MW	522	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
87748823 MW	523	if (ret)
a7ca2bcf	524	pr_warn("i2c0 registration failed: %d\n", ret);
87748823 MW	525
	526	ret = pmic_tps65023_init();
	527	if (ret)
a7ca2bcf	528	pr_warn("TPS65023 PMIC init failed: %d\n", ret);
87748823	529
f2dbb6d9 MW	530	mityomapl138_setup_nand();
f2dbb6d9 MW	531
0273612c VD	532	ret = spi_register_board_info(mityomapl138_spi_flash_info,
	533	ARRAY_SIZE(mityomapl138_spi_flash_info));
	534	if (ret)
	535	pr_warn("spi info registration failed: %d\n", ret);
	536
	537	ret = da8xx_register_spi_bus(1,
	538	ARRAY_SIZE(mityomapl138_spi_flash_info));
dd561c6a	539	if (ret)
a7ca2bcf	540	pr_warn("spi 1 registration failed: %d\n", ret);
dd561c6a	541
f2dbb6d9 MW	542	mityomapl138_config_emac();
	543
	544	ret = da8xx_register_rtc();
	545	if (ret)
a7ca2bcf	546	pr_warn("rtc setup failed: %d\n", ret);
f2dbb6d9	547
f2dbb6d9 MW	548	ret = da8xx_register_cpuidle();
f2dbb6d9 MW	549	if (ret)
a7ca2bcf	550	pr_warn("cpuidle registration failed: %d\n", ret);
f2dbb6d9 MW	551
	552	ret = da850_register_pm(&da850_pm_device);
	553	if (ret)
a7ca2bcf	554	pr_warn("suspend registration failed: %d\n", ret);
f2dbb6d9 MW	555	}
	556
	557	#ifdef CONFIG_SERIAL_8250_CONSOLE
	558	static int __init mityomapl138_console_init(void)
	559	{
	560	if (!machine_is_mityomapl138())
	561	return 0;
	562
	563	return add_preferred_console("ttyS", 1, "115200");
	564	}
	565	console_initcall(mityomapl138_console_init);
	566	#endif
	567
	568	static void __init mityomapl138_map_io(void)
	569	{
	570	da850_init();
	571	}
	572
	573	MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
e7e56014	574	.atag_offset = 0x100,
f2dbb6d9 MW	575	.map_io = mityomapl138_map_io,
f2dbb6d9 MW	576	.init_irq = cp_intc_init,
6bb27d73	577	.init_time = davinci_timer_init,
f2dbb6d9	578	.init_machine = mityomapl138_init,
3aa3e840	579	.init_late = davinci_init_late,
f68deabf	580	.dma_zone_size = SZ_128M,
c6121ddd	581	.restart = da8xx_restart,
f2dbb6d9	582	MACHINE_END