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e38d92fd KH |
1 | /* |
2 | * TI DaVinci DM646X EVM board | |
3 | * | |
4 | * Derived from: arch/arm/mach-davinci/board-evm.c | |
5 | * Copyright (C) 2006 Texas Instruments. | |
6 | * | |
7 | * (C) 2007-2008, MontaVista Software, Inc. | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public License | |
10 | * version 2. This program is licensed "as is" without any warranty of any | |
11 | * kind, whether express or implied. | |
12 | * | |
13 | */ | |
14 | ||
15 | /************************************************************************** | |
16 | * Included Files | |
17 | **************************************************************************/ | |
18 | ||
19 | #include <linux/kernel.h> | |
e38d92fd | 20 | #include <linux/init.h> |
e38d92fd KH |
21 | #include <linux/leds.h> |
22 | #include <linux/gpio.h> | |
e38d92fd KH |
23 | #include <linux/platform_device.h> |
24 | #include <linux/i2c.h> | |
25 | #include <linux/i2c/at24.h> | |
26 | #include <linux/i2c/pcf857x.h> | |
e38d92fd | 27 | |
85609c1c MK |
28 | #include <media/tvp514x.h> |
29 | ||
50fbabfe HP |
30 | #include <linux/mtd/mtd.h> |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/partitions.h> | |
c1978e1d | 33 | #include <linux/clk.h> |
50fbabfe | 34 | |
e38d92fd KH |
35 | #include <asm/mach-types.h> |
36 | #include <asm/mach/arch.h> | |
e38d92fd KH |
37 | |
38 | #include <mach/dm646x.h> | |
39 | #include <mach/common.h> | |
e38d92fd KH |
40 | #include <mach/serial.h> |
41 | #include <mach/i2c.h> | |
50fbabfe | 42 | #include <mach/nand.h> |
77a92c71 NS |
43 | #include <mach/clock.h> |
44 | #include <mach/cdce949.h> | |
ac7b75b5 | 45 | |
c1978e1d SN |
46 | #include "clock.h" |
47 | ||
50fbabfe HP |
48 | #define NAND_BLOCK_SIZE SZ_128K |
49 | ||
50fbabfe HP |
50 | /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot |
51 | * and U-Boot environment this avoids dependency on any particular combination | |
52 | * of UBL, U-Boot or flashing tools etc. | |
53 | */ | |
54 | static struct mtd_partition davinci_nand_partitions[] = { | |
55 | { | |
56 | /* UBL, U-Boot with environment */ | |
57 | .name = "bootloader", | |
58 | .offset = MTDPART_OFS_APPEND, | |
59 | .size = 16 * NAND_BLOCK_SIZE, | |
60 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
61 | }, { | |
62 | .name = "kernel", | |
63 | .offset = MTDPART_OFS_APPEND, | |
64 | .size = SZ_4M, | |
65 | .mask_flags = 0, | |
66 | }, { | |
67 | .name = "filesystem", | |
68 | .offset = MTDPART_OFS_APPEND, | |
69 | .size = MTDPART_SIZ_FULL, | |
70 | .mask_flags = 0, | |
71 | } | |
72 | }; | |
73 | ||
74 | static struct davinci_nand_pdata davinci_nand_data = { | |
75 | .mask_cle = 0x80000, | |
76 | .mask_ale = 0x40000, | |
77 | .parts = davinci_nand_partitions, | |
78 | .nr_parts = ARRAY_SIZE(davinci_nand_partitions), | |
79 | .ecc_mode = NAND_ECC_HW, | |
80 | .options = 0, | |
81 | }; | |
82 | ||
83 | static struct resource davinci_nand_resources[] = { | |
84 | { | |
70342174 SS |
85 | .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE, |
86 | .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1, | |
50fbabfe HP |
87 | .flags = IORESOURCE_MEM, |
88 | }, { | |
70342174 SS |
89 | .start = DM646X_ASYNC_EMIF_CONTROL_BASE, |
90 | .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, | |
50fbabfe HP |
91 | .flags = IORESOURCE_MEM, |
92 | }, | |
93 | }; | |
94 | ||
95 | static struct platform_device davinci_nand_device = { | |
96 | .name = "davinci_nand", | |
97 | .id = 0, | |
98 | ||
99 | .num_resources = ARRAY_SIZE(davinci_nand_resources), | |
100 | .resource = davinci_nand_resources, | |
101 | ||
102 | .dev = { | |
103 | .platform_data = &davinci_nand_data, | |
104 | }, | |
105 | }; | |
106 | ||
b73b526e SN |
107 | #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ |
108 | defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) | |
109 | #define HAS_ATA 1 | |
110 | #else | |
111 | #define HAS_ATA 0 | |
112 | #endif | |
113 | ||
114 | /* CPLD Register 0 bits to control ATA */ | |
115 | #define DM646X_EVM_ATA_RST BIT(0) | |
116 | #define DM646X_EVM_ATA_PWD BIT(1) | |
117 | ||
548197bd HP |
118 | /* CPLD Register 0 Client: used for I/O Control */ |
119 | static int cpld_reg0_probe(struct i2c_client *client, | |
120 | const struct i2c_device_id *id) | |
121 | { | |
122 | if (HAS_ATA) { | |
123 | u8 data; | |
124 | struct i2c_msg msg[2] = { | |
125 | { | |
126 | .addr = client->addr, | |
127 | .flags = I2C_M_RD, | |
128 | .len = 1, | |
129 | .buf = &data, | |
130 | }, | |
131 | { | |
132 | .addr = client->addr, | |
133 | .flags = 0, | |
134 | .len = 1, | |
135 | .buf = &data, | |
136 | }, | |
137 | }; | |
138 | ||
139 | /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */ | |
140 | i2c_transfer(client->adapter, msg, 1); | |
141 | data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD); | |
142 | i2c_transfer(client->adapter, msg + 1, 1); | |
143 | } | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | static const struct i2c_device_id cpld_reg_ids[] = { | |
149 | { "cpld_reg0", 0, }, | |
150 | { }, | |
151 | }; | |
152 | ||
153 | static struct i2c_driver dm6467evm_cpld_driver = { | |
154 | .driver.name = "cpld_reg0", | |
155 | .id_table = cpld_reg_ids, | |
156 | .probe = cpld_reg0_probe, | |
157 | }; | |
158 | ||
e38d92fd KH |
159 | /* LEDS */ |
160 | ||
161 | static struct gpio_led evm_leds[] = { | |
162 | { .name = "DS1", .active_low = 1, }, | |
163 | { .name = "DS2", .active_low = 1, }, | |
164 | { .name = "DS3", .active_low = 1, }, | |
165 | { .name = "DS4", .active_low = 1, }, | |
166 | }; | |
167 | ||
445094f9 | 168 | static const struct gpio_led_platform_data evm_led_data = { |
e38d92fd KH |
169 | .num_leds = ARRAY_SIZE(evm_leds), |
170 | .leds = evm_leds, | |
171 | }; | |
172 | ||
173 | static struct platform_device *evm_led_dev; | |
174 | ||
175 | static int evm_led_setup(struct i2c_client *client, int gpio, | |
176 | unsigned int ngpio, void *c) | |
177 | { | |
178 | struct gpio_led *leds = evm_leds; | |
179 | int status; | |
180 | ||
181 | while (ngpio--) { | |
182 | leds->gpio = gpio++; | |
183 | leds++; | |
184 | }; | |
185 | ||
186 | evm_led_dev = platform_device_alloc("leds-gpio", 0); | |
187 | platform_device_add_data(evm_led_dev, &evm_led_data, | |
188 | sizeof(evm_led_data)); | |
189 | ||
190 | evm_led_dev->dev.parent = &client->dev; | |
191 | status = platform_device_add(evm_led_dev); | |
192 | if (status < 0) { | |
193 | platform_device_put(evm_led_dev); | |
194 | evm_led_dev = NULL; | |
195 | } | |
196 | return status; | |
197 | } | |
198 | ||
199 | static int evm_led_teardown(struct i2c_client *client, int gpio, | |
200 | unsigned ngpio, void *c) | |
201 | { | |
202 | if (evm_led_dev) { | |
203 | platform_device_unregister(evm_led_dev); | |
204 | evm_led_dev = NULL; | |
205 | } | |
206 | return 0; | |
207 | } | |
208 | ||
209 | static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL }; | |
210 | ||
211 | static int evm_sw_setup(struct i2c_client *client, int gpio, | |
212 | unsigned ngpio, void *c) | |
213 | { | |
214 | int status; | |
215 | int i; | |
216 | char label[10]; | |
217 | ||
218 | for (i = 0; i < 4; ++i) { | |
219 | snprintf(label, 10, "user_sw%d", i); | |
220 | status = gpio_request(gpio, label); | |
221 | if (status) | |
222 | goto out_free; | |
223 | evm_sw_gpio[i] = gpio++; | |
224 | ||
225 | status = gpio_direction_input(evm_sw_gpio[i]); | |
226 | if (status) { | |
227 | gpio_free(evm_sw_gpio[i]); | |
228 | evm_sw_gpio[i] = -EINVAL; | |
229 | goto out_free; | |
230 | } | |
231 | ||
232 | status = gpio_export(evm_sw_gpio[i], 0); | |
233 | if (status) { | |
234 | gpio_free(evm_sw_gpio[i]); | |
235 | evm_sw_gpio[i] = -EINVAL; | |
236 | goto out_free; | |
237 | } | |
238 | } | |
239 | return status; | |
240 | out_free: | |
241 | for (i = 0; i < 4; ++i) { | |
242 | if (evm_sw_gpio[i] != -EINVAL) { | |
243 | gpio_free(evm_sw_gpio[i]); | |
244 | evm_sw_gpio[i] = -EINVAL; | |
245 | } | |
246 | } | |
247 | return status; | |
248 | } | |
249 | ||
250 | static int evm_sw_teardown(struct i2c_client *client, int gpio, | |
251 | unsigned ngpio, void *c) | |
252 | { | |
253 | int i; | |
254 | ||
255 | for (i = 0; i < 4; ++i) { | |
256 | if (evm_sw_gpio[i] != -EINVAL) { | |
257 | gpio_unexport(evm_sw_gpio[i]); | |
258 | gpio_free(evm_sw_gpio[i]); | |
259 | evm_sw_gpio[i] = -EINVAL; | |
260 | } | |
261 | } | |
262 | return 0; | |
263 | } | |
264 | ||
265 | static int evm_pcf_setup(struct i2c_client *client, int gpio, | |
266 | unsigned int ngpio, void *c) | |
267 | { | |
268 | int status; | |
269 | ||
270 | if (ngpio < 8) | |
271 | return -EINVAL; | |
272 | ||
273 | status = evm_sw_setup(client, gpio, 4, c); | |
274 | if (status) | |
275 | return status; | |
276 | ||
277 | return evm_led_setup(client, gpio+4, 4, c); | |
278 | } | |
279 | ||
280 | static int evm_pcf_teardown(struct i2c_client *client, int gpio, | |
281 | unsigned int ngpio, void *c) | |
282 | { | |
283 | BUG_ON(ngpio < 8); | |
284 | ||
285 | evm_sw_teardown(client, gpio, 4, c); | |
286 | evm_led_teardown(client, gpio+4, 4, c); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static struct pcf857x_platform_data pcf_data = { | |
292 | .gpio_base = DAVINCI_N_GPIO+1, | |
293 | .setup = evm_pcf_setup, | |
294 | .teardown = evm_pcf_teardown, | |
295 | }; | |
296 | ||
297 | /* Most of this EEPROM is unused, but U-Boot uses some data: | |
298 | * - 0x7f00, 6 bytes Ethernet Address | |
299 | * - ... newer boards may have more | |
300 | */ | |
e38d92fd KH |
301 | |
302 | static struct at24_platform_data eeprom_info = { | |
303 | .byte_len = (256*1024) / 8, | |
304 | .page_size = 64, | |
305 | .flags = AT24_FLAG_ADDR16, | |
b14dc0f9 MG |
306 | .setup = davinci_get_mac_addr, |
307 | .context = (void *)0x7f00, | |
e38d92fd KH |
308 | }; |
309 | ||
25acf553 C |
310 | static u8 dm646x_iis_serializer_direction[] = { |
311 | TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, | |
312 | }; | |
313 | ||
314 | static u8 dm646x_dit_serializer_direction[] = { | |
315 | TX_MODE, | |
316 | }; | |
317 | ||
318 | static struct snd_platform_data dm646x_evm_snd_data[] = { | |
319 | { | |
25acf553 C |
320 | .tx_dma_offset = 0x400, |
321 | .rx_dma_offset = 0x400, | |
322 | .op_mode = DAVINCI_MCASP_IIS_MODE, | |
323 | .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), | |
324 | .tdm_slots = 2, | |
325 | .serial_dir = dm646x_iis_serializer_direction, | |
326 | .eventq_no = EVENTQ_0, | |
327 | }, | |
328 | { | |
25acf553 C |
329 | .tx_dma_offset = 0x400, |
330 | .rx_dma_offset = 0, | |
331 | .op_mode = DAVINCI_MCASP_DIT_MODE, | |
332 | .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), | |
333 | .tdm_slots = 32, | |
334 | .serial_dir = dm646x_dit_serializer_direction, | |
335 | .eventq_no = EVENTQ_0, | |
336 | }, | |
337 | }; | |
338 | ||
85609c1c MK |
339 | static struct i2c_client *cpld_client; |
340 | ||
341 | static int cpld_video_probe(struct i2c_client *client, | |
342 | const struct i2c_device_id *id) | |
343 | { | |
344 | cpld_client = client; | |
345 | return 0; | |
346 | } | |
347 | ||
348 | static int __devexit cpld_video_remove(struct i2c_client *client) | |
349 | { | |
350 | cpld_client = NULL; | |
351 | return 0; | |
352 | } | |
353 | ||
354 | static const struct i2c_device_id cpld_video_id[] = { | |
355 | { "cpld_video", 0 }, | |
356 | { } | |
357 | }; | |
358 | ||
359 | static struct i2c_driver cpld_video_driver = { | |
360 | .driver = { | |
361 | .name = "cpld_video", | |
362 | }, | |
363 | .probe = cpld_video_probe, | |
364 | .remove = cpld_video_remove, | |
365 | .id_table = cpld_video_id, | |
366 | }; | |
367 | ||
368 | static void evm_init_cpld(void) | |
369 | { | |
370 | i2c_add_driver(&cpld_video_driver); | |
371 | } | |
372 | ||
e38d92fd KH |
373 | static struct i2c_board_info __initdata i2c_info[] = { |
374 | { | |
375 | I2C_BOARD_INFO("24c256", 0x50), | |
376 | .platform_data = &eeprom_info, | |
377 | }, | |
378 | { | |
379 | I2C_BOARD_INFO("pcf8574a", 0x38), | |
380 | .platform_data = &pcf_data, | |
381 | }, | |
548197bd HP |
382 | { |
383 | I2C_BOARD_INFO("cpld_reg0", 0x3a), | |
384 | }, | |
1a7ff8ff C |
385 | { |
386 | I2C_BOARD_INFO("tlv320aic33", 0x18), | |
85609c1c MK |
387 | }, |
388 | { | |
389 | I2C_BOARD_INFO("cpld_video", 0x3b), | |
390 | }, | |
77a92c71 NS |
391 | { |
392 | I2C_BOARD_INFO("cdce949", 0x6c), | |
393 | }, | |
e38d92fd KH |
394 | }; |
395 | ||
396 | static struct davinci_i2c_platform_data i2c_pdata = { | |
397 | .bus_freq = 100 /* kHz */, | |
398 | .bus_delay = 0 /* usec */, | |
399 | }; | |
400 | ||
b73b526e SN |
401 | #define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38) |
402 | #define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c) | |
403 | #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8)) | |
404 | #define VCH2CLK_SYSCLK8 (BIT(9)) | |
405 | #define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) | |
406 | #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12)) | |
407 | #define VCH3CLK_SYSCLK8 (BIT(13)) | |
408 | #define VCH3CLK_AUXCLK (BIT(14) | BIT(13)) | |
409 | ||
410 | #define VIDCH2CLK (BIT(10)) | |
411 | #define VIDCH3CLK (BIT(11)) | |
412 | #define VIDCH1CLK (BIT(4)) | |
413 | #define TVP7002_INPUT (BIT(4)) | |
414 | #define TVP5147_INPUT (~BIT(4)) | |
415 | #define VPIF_INPUT_ONE_CHANNEL (BIT(5)) | |
416 | #define VPIF_INPUT_TWO_CHANNEL (~BIT(5)) | |
417 | #define TVP5147_CH0 "tvp514x-0" | |
418 | #define TVP5147_CH1 "tvp514x-1" | |
419 | ||
420 | static void __iomem *vpif_vidclkctl_reg; | |
421 | static void __iomem *vpif_vsclkdis_reg; | |
422 | /* spin lock for updating above registers */ | |
423 | static spinlock_t vpif_reg_lock; | |
424 | ||
85609c1c MK |
425 | static int set_vpif_clock(int mux_mode, int hd) |
426 | { | |
427 | unsigned long flags; | |
428 | unsigned int value; | |
429 | int val = 0; | |
430 | int err = 0; | |
431 | ||
432 | if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client) | |
433 | return -ENXIO; | |
434 | ||
435 | /* disable the clock */ | |
436 | spin_lock_irqsave(&vpif_reg_lock, flags); | |
437 | value = __raw_readl(vpif_vsclkdis_reg); | |
438 | value |= (VIDCH3CLK | VIDCH2CLK); | |
439 | __raw_writel(value, vpif_vsclkdis_reg); | |
440 | spin_unlock_irqrestore(&vpif_reg_lock, flags); | |
441 | ||
442 | val = i2c_smbus_read_byte(cpld_client); | |
443 | if (val < 0) | |
444 | return val; | |
445 | ||
446 | if (mux_mode == 1) | |
447 | val &= ~0x40; | |
448 | else | |
449 | val |= 0x40; | |
450 | ||
451 | err = i2c_smbus_write_byte(cpld_client, val); | |
452 | if (err) | |
453 | return err; | |
454 | ||
455 | value = __raw_readl(vpif_vidclkctl_reg); | |
456 | value &= ~(VCH2CLK_MASK); | |
457 | value &= ~(VCH3CLK_MASK); | |
458 | ||
459 | if (hd >= 1) | |
460 | value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8); | |
461 | else | |
462 | value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK); | |
463 | ||
464 | __raw_writel(value, vpif_vidclkctl_reg); | |
465 | ||
466 | spin_lock_irqsave(&vpif_reg_lock, flags); | |
467 | value = __raw_readl(vpif_vsclkdis_reg); | |
468 | /* enable the clock */ | |
469 | value &= ~(VIDCH3CLK | VIDCH2CLK); | |
470 | __raw_writel(value, vpif_vsclkdis_reg); | |
471 | spin_unlock_irqrestore(&vpif_reg_lock, flags); | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static struct vpif_subdev_info dm646x_vpif_subdev[] = { | |
477 | { | |
478 | .name = "adv7343", | |
479 | .board_info = { | |
480 | I2C_BOARD_INFO("adv7343", 0x2a), | |
481 | }, | |
482 | }, | |
483 | { | |
484 | .name = "ths7303", | |
485 | .board_info = { | |
486 | I2C_BOARD_INFO("ths7303", 0x2c), | |
487 | }, | |
488 | }, | |
489 | }; | |
490 | ||
491 | static const char *output[] = { | |
492 | "Composite", | |
493 | "Component", | |
494 | "S-Video", | |
495 | }; | |
496 | ||
497 | static struct vpif_display_config dm646x_vpif_display_config = { | |
498 | .set_clock = set_vpif_clock, | |
499 | .subdevinfo = dm646x_vpif_subdev, | |
500 | .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), | |
501 | .output = output, | |
502 | .output_count = ARRAY_SIZE(output), | |
503 | .card_name = "DM646x EVM", | |
504 | }; | |
505 | ||
506 | /** | |
507 | * setup_vpif_input_path() | |
508 | * @channel: channel id (0 - CH0, 1 - CH1) | |
509 | * @sub_dev_name: ptr sub device name | |
510 | * | |
511 | * This will set vpif input to capture data from tvp514x or | |
512 | * tvp7002. | |
513 | */ | |
514 | static int setup_vpif_input_path(int channel, const char *sub_dev_name) | |
515 | { | |
516 | int err = 0; | |
517 | int val; | |
518 | ||
519 | /* for channel 1, we don't do anything */ | |
520 | if (channel != 0) | |
521 | return 0; | |
522 | ||
523 | if (!cpld_client) | |
524 | return -ENXIO; | |
525 | ||
526 | val = i2c_smbus_read_byte(cpld_client); | |
527 | if (val < 0) | |
528 | return val; | |
529 | ||
530 | if (!strcmp(sub_dev_name, TVP5147_CH0) || | |
531 | !strcmp(sub_dev_name, TVP5147_CH1)) | |
532 | val &= TVP5147_INPUT; | |
533 | else | |
534 | val |= TVP7002_INPUT; | |
535 | ||
536 | err = i2c_smbus_write_byte(cpld_client, val); | |
537 | if (err) | |
538 | return err; | |
539 | return 0; | |
540 | } | |
541 | ||
542 | /** | |
543 | * setup_vpif_input_channel_mode() | |
544 | * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel | |
545 | * | |
546 | * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147) | |
547 | */ | |
548 | static int setup_vpif_input_channel_mode(int mux_mode) | |
549 | { | |
550 | unsigned long flags; | |
551 | int err = 0; | |
552 | int val; | |
553 | u32 value; | |
554 | ||
555 | if (!vpif_vsclkdis_reg || !cpld_client) | |
556 | return -ENXIO; | |
557 | ||
558 | val = i2c_smbus_read_byte(cpld_client); | |
559 | if (val < 0) | |
560 | return val; | |
561 | ||
562 | spin_lock_irqsave(&vpif_reg_lock, flags); | |
563 | value = __raw_readl(vpif_vsclkdis_reg); | |
564 | if (mux_mode) { | |
565 | val &= VPIF_INPUT_TWO_CHANNEL; | |
566 | value |= VIDCH1CLK; | |
567 | } else { | |
568 | val |= VPIF_INPUT_ONE_CHANNEL; | |
569 | value &= ~VIDCH1CLK; | |
570 | } | |
571 | __raw_writel(value, vpif_vsclkdis_reg); | |
572 | spin_unlock_irqrestore(&vpif_reg_lock, flags); | |
573 | ||
574 | err = i2c_smbus_write_byte(cpld_client, val); | |
575 | if (err) | |
576 | return err; | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | static struct tvp514x_platform_data tvp5146_pdata = { | |
582 | .clk_polarity = 0, | |
583 | .hs_polarity = 1, | |
584 | .vs_polarity = 1 | |
585 | }; | |
586 | ||
587 | #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) | |
588 | ||
589 | static struct vpif_subdev_info vpif_capture_sdev_info[] = { | |
590 | { | |
591 | .name = TVP5147_CH0, | |
592 | .board_info = { | |
593 | I2C_BOARD_INFO("tvp5146", 0x5d), | |
594 | .platform_data = &tvp5146_pdata, | |
595 | }, | |
596 | .input = INPUT_CVBS_VI2B, | |
597 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | |
598 | .can_route = 1, | |
599 | .vpif_if = { | |
600 | .if_type = VPIF_IF_BT656, | |
601 | .hd_pol = 1, | |
602 | .vd_pol = 1, | |
603 | .fid_pol = 0, | |
604 | }, | |
605 | }, | |
606 | { | |
607 | .name = TVP5147_CH1, | |
608 | .board_info = { | |
609 | I2C_BOARD_INFO("tvp5146", 0x5c), | |
610 | .platform_data = &tvp5146_pdata, | |
611 | }, | |
612 | .input = INPUT_SVIDEO_VI2C_VI1C, | |
613 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | |
614 | .can_route = 1, | |
615 | .vpif_if = { | |
616 | .if_type = VPIF_IF_BT656, | |
617 | .hd_pol = 1, | |
618 | .vd_pol = 1, | |
619 | .fid_pol = 0, | |
620 | }, | |
621 | }, | |
622 | }; | |
623 | ||
624 | static const struct vpif_input dm6467_ch0_inputs[] = { | |
625 | { | |
626 | .input = { | |
627 | .index = 0, | |
628 | .name = "Composite", | |
629 | .type = V4L2_INPUT_TYPE_CAMERA, | |
630 | .std = TVP514X_STD_ALL, | |
631 | }, | |
632 | .subdev_name = TVP5147_CH0, | |
633 | }, | |
634 | }; | |
635 | ||
636 | static const struct vpif_input dm6467_ch1_inputs[] = { | |
637 | { | |
638 | .input = { | |
639 | .index = 0, | |
640 | .name = "S-Video", | |
641 | .type = V4L2_INPUT_TYPE_CAMERA, | |
642 | .std = TVP514X_STD_ALL, | |
643 | }, | |
644 | .subdev_name = TVP5147_CH1, | |
645 | }, | |
646 | }; | |
647 | ||
648 | static struct vpif_capture_config dm646x_vpif_capture_cfg = { | |
649 | .setup_input_path = setup_vpif_input_path, | |
650 | .setup_input_channel_mode = setup_vpif_input_channel_mode, | |
651 | .subdev_info = vpif_capture_sdev_info, | |
652 | .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info), | |
653 | .chan_config[0] = { | |
654 | .inputs = dm6467_ch0_inputs, | |
655 | .input_count = ARRAY_SIZE(dm6467_ch0_inputs), | |
656 | }, | |
657 | .chan_config[1] = { | |
658 | .inputs = dm6467_ch1_inputs, | |
659 | .input_count = ARRAY_SIZE(dm6467_ch1_inputs), | |
660 | }, | |
661 | }; | |
662 | ||
663 | static void __init evm_init_video(void) | |
664 | { | |
665 | vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4); | |
666 | vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4); | |
667 | if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) { | |
668 | pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n"); | |
669 | return; | |
670 | } | |
671 | spin_lock_init(&vpif_reg_lock); | |
672 | ||
673 | dm646x_setup_vpif(&dm646x_vpif_display_config, | |
674 | &dm646x_vpif_capture_cfg); | |
675 | } | |
676 | ||
e38d92fd KH |
677 | static void __init evm_init_i2c(void) |
678 | { | |
679 | davinci_init_i2c(&i2c_pdata); | |
548197bd | 680 | i2c_add_driver(&dm6467evm_cpld_driver); |
e38d92fd | 681 | i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); |
85609c1c MK |
682 | evm_init_cpld(); |
683 | evm_init_video(); | |
e38d92fd KH |
684 | } |
685 | ||
77a92c71 NS |
686 | #define CDCE949_XIN_RATE 27000000 |
687 | ||
688 | /* CDCE949 support - "lpsc" field is overridden to work as clock number */ | |
689 | static struct clk cdce_clk_in = { | |
690 | .name = "cdce_xin", | |
691 | .rate = CDCE949_XIN_RATE, | |
692 | }; | |
693 | ||
c564191b | 694 | static struct clk_lookup cdce_clks[] = { |
77a92c71 NS |
695 | CLK(NULL, "xin", &cdce_clk_in), |
696 | CLK(NULL, NULL, NULL), | |
697 | }; | |
698 | ||
699 | static void __init cdce_clk_init(void) | |
700 | { | |
c564191b | 701 | struct clk_lookup *c; |
77a92c71 NS |
702 | struct clk *clk; |
703 | ||
c564191b KH |
704 | for (c = cdce_clks; c->clk; c++) { |
705 | clk = c->clk; | |
706 | clkdev_add(c); | |
77a92c71 NS |
707 | clk_register(clk); |
708 | } | |
709 | } | |
710 | ||
e38d92fd KH |
711 | static void __init davinci_map_io(void) |
712 | { | |
e38d92fd | 713 | dm646x_init(); |
77a92c71 | 714 | cdce_clk_init(); |
e38d92fd KH |
715 | } |
716 | ||
b73b526e SN |
717 | static struct davinci_uart_config uart_config __initdata = { |
718 | .enabled_uarts = (1 << 0), | |
719 | }; | |
720 | ||
721 | #define DM646X_EVM_PHY_MASK (0x2) | |
722 | #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ | |
723 | ||
e38d92fd KH |
724 | static __init void evm_init(void) |
725 | { | |
972412b6 MG |
726 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
727 | ||
e38d92fd KH |
728 | evm_init_i2c(); |
729 | davinci_serial_init(&uart_config); | |
25acf553 C |
730 | dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); |
731 | dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); | |
972412b6 | 732 | |
50fbabfe HP |
733 | platform_device_register(&davinci_nand_device); |
734 | ||
548197bd | 735 | if (HAS_ATA) |
7a9978a1 | 736 | davinci_init_ide(); |
548197bd | 737 | |
972412b6 MG |
738 | soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; |
739 | soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; | |
e38d92fd KH |
740 | } |
741 | ||
c1978e1d SN |
742 | #define DM646X_EVM_REF_FREQ 27000000 |
743 | #define DM6467T_EVM_REF_FREQ 33000000 | |
744 | ||
745 | void __init dm646x_board_setup_refclk(struct clk *clk) | |
746 | { | |
747 | if (machine_is_davinci_dm6467tevm()) | |
748 | clk->rate = DM6467T_EVM_REF_FREQ; | |
749 | else | |
750 | clk->rate = DM646X_EVM_REF_FREQ; | |
751 | } | |
752 | ||
e38d92fd KH |
753 | MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") |
754 | .phys_io = IO_PHYS, | |
755 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, | |
756 | .boot_params = (0x80000100), | |
757 | .map_io = davinci_map_io, | |
bd808947 | 758 | .init_irq = davinci_irq_init, |
e38d92fd KH |
759 | .timer = &davinci_timer, |
760 | .init_machine = evm_init, | |
761 | MACHINE_END | |
762 | ||
c1978e1d SN |
763 | MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") |
764 | .phys_io = IO_PHYS, | |
765 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, | |
766 | .boot_params = (0x80000100), | |
767 | .map_io = davinci_map_io, | |
bd808947 | 768 | .init_irq = davinci_irq_init, |
c1978e1d SN |
769 | .timer = &davinci_timer, |
770 | .init_machine = evm_init, | |
771 | MACHINE_END | |
772 |