Merge branch 'work.mount' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux-2.6-block.git] / arch / arm / mach-davinci / board-dm644x-evm.c
CommitLineData
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1/*
2 * TI DaVinci EVM board support
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
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12#include <linux/init.h>
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
7bff3c4c 15#include <linux/gpio.h>
e5353765 16#include <linux/gpio/machine.h>
7bff3c4c 17#include <linux/i2c.h>
b6480fae 18#include <linux/platform_data/pcf857x.h>
9411ac07 19#include <linux/platform_data/gpio-davinci.h>
4b683bbb 20#include <linux/property.h>
7c6337e2 21#include <linux/mtd/mtd.h>
d4092d76 22#include <linux/mtd/rawnand.h>
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23#include <linux/mtd/partitions.h>
24#include <linux/mtd/physmap.h>
89c817c4 25#include <linux/nvmem-provider.h>
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26#include <linux/phy.h>
27#include <linux/clk.h>
ab8e8df8 28#include <linux/videodev2.h>
36864082 29#include <linux/v4l2-dv-timings.h>
dc28094b 30#include <linux/export.h>
f46f335c 31#include <linux/leds.h>
ab8e8df8 32
b5dcee22 33#include <media/i2c/tvp514x.h>
7c6337e2 34
7c6337e2 35#include <asm/mach-types.h>
7c6337e2 36#include <asm/mach/arch.h>
7c6337e2 37
a09e64fb 38#include <mach/common.h>
d0e47fba 39#include <mach/mux.h>
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40#include <mach/serial.h>
41
42#include <linux/platform_data/i2c-davinci.h>
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43#include <linux/platform_data/mtd-davinci.h>
44#include <linux/platform_data/mmc-davinci.h>
45#include <linux/platform_data/usb-davinci.h>
46#include <linux/platform_data/mtd-davinci-aemif.h>
2ee2948e 47#include <linux/platform_data/ti-aemif.h>
d0e47fba 48
39c6d2d1 49#include "davinci.h"
544ca0b0 50#include "irqs.h"
39c6d2d1 51
f6f97588 52#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
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53#define LXT971_PHY_ID (0x001378e2)
54#define LXT971_PHY_MASK (0xfffffff0)
7c6337e2 55
7bff3c4c 56static struct mtd_partition davinci_evm_norflash_partitions[] = {
d0e47fba 57 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
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58 {
59 .name = "bootloader",
60 .offset = 0,
d0e47fba 61 .size = 5 * SZ_64K,
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62 .mask_flags = MTD_WRITEABLE, /* force read-only */
63 },
64 /* bootloader params in the next 1 sectors */
65 {
66 .name = "params",
67 .offset = MTDPART_OFS_APPEND,
68 .size = SZ_64K,
69 .mask_flags = 0,
70 },
71 /* kernel */
72 {
73 .name = "kernel",
74 .offset = MTDPART_OFS_APPEND,
75 .size = SZ_2M,
76 .mask_flags = 0
77 },
78 /* file system */
79 {
80 .name = "filesystem",
81 .offset = MTDPART_OFS_APPEND,
82 .size = MTDPART_SIZ_FULL,
83 .mask_flags = 0
84 }
85};
86
7bff3c4c 87static struct physmap_flash_data davinci_evm_norflash_data = {
7c6337e2 88 .width = 2,
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89 .parts = davinci_evm_norflash_partitions,
90 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
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91};
92
93/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
94 * limits addresses to 16M, so using addresses past 16M will wrap */
7bff3c4c 95static struct resource davinci_evm_norflash_resource = {
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96 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
97 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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98 .flags = IORESOURCE_MEM,
99};
100
7bff3c4c 101static struct platform_device davinci_evm_norflash_device = {
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102 .name = "physmap-flash",
103 .id = 0,
104 .dev = {
7bff3c4c 105 .platform_data = &davinci_evm_norflash_data,
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106 },
107 .num_resources = 1,
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108 .resource = &davinci_evm_norflash_resource,
109};
110
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111/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
112 * It may used instead of the (default) NOR chip to boot, using TI's
113 * tools to install the secondary boot loader (UBL) and U-Boot.
114 */
28552c2e 115static struct mtd_partition davinci_evm_nandflash_partition[] = {
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116 /* Bootloader layout depends on whose u-boot is installed, but we
117 * can hide all the details.
118 * - block 0 for u-boot environment ... in mainline u-boot
119 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
120 * - blocks 6...? for u-boot
121 * - blocks 16..23 for u-boot environment ... in TI's u-boot
122 */
123 {
124 .name = "bootloader",
125 .offset = 0,
126 .size = SZ_256K + SZ_128K,
127 .mask_flags = MTD_WRITEABLE, /* force read-only */
128 },
129 /* Kernel */
d0e47fba 130 {
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131 .name = "kernel",
132 .offset = MTDPART_OFS_APPEND,
133 .size = SZ_4M,
134 .mask_flags = 0,
135 },
136 /* File system (older GIT kernels started this on the 5MB mark) */
137 {
138 .name = "filesystem",
139 .offset = MTDPART_OFS_APPEND,
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140 .size = MTDPART_SIZ_FULL,
141 .mask_flags = 0,
142 }
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143 /* A few blocks at end hold a flash BBT ... created by TI's CCS
144 * using flashwriter_nand.out, but ignored by TI's versions of
145 * Linux and u-boot. We boot faster by using them.
146 */
d0e47fba 147};
7bff3c4c 148
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149static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
150 .wsetup = 20,
151 .wstrobe = 40,
152 .whold = 20,
153 .rsetup = 10,
154 .rstrobe = 40,
155 .rhold = 10,
156 .ta = 40,
157};
158
d0e47fba 159static struct davinci_nand_pdata davinci_evm_nandflash_data = {
040c6a04 160 .core_chipsel = 0,
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161 .parts = davinci_evm_nandflash_partition,
162 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
163 .ecc_mode = NAND_ECC_HW,
acd36357 164 .ecc_bits = 1,
bb9ebd4e 165 .bbt_options = NAND_BBT_USE_FLASH,
fe69c82d 166 .timing = &davinci_evm_nandflash_timing,
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167};
168
169static struct resource davinci_evm_nandflash_resource[] = {
170 {
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171 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
172 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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173 .flags = IORESOURCE_MEM,
174 }, {
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175 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
176 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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177 .flags = IORESOURCE_MEM,
178 },
179};
180
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181static struct resource davinci_evm_aemif_resource[] = {
182 {
183 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
184 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
185 .flags = IORESOURCE_MEM,
d0e47fba 186 },
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187};
188
189static struct aemif_abus_data davinci_evm_aemif_abus_data[] = {
190 {
191 .cs = 1,
192 },
193};
194
195static struct platform_device davinci_evm_nandflash_devices[] = {
196 {
197 .name = "davinci_nand",
198 .id = 0,
199 .dev = {
200 .platform_data = &davinci_evm_nandflash_data,
201 },
202 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
203 .resource = davinci_evm_nandflash_resource,
204 },
205};
206
207static struct aemif_platform_data davinci_evm_aemif_pdata = {
208 .abus_data = davinci_evm_aemif_abus_data,
209 .num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data),
210 .sub_devices = davinci_evm_nandflash_devices,
211 .num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices),
212};
213
214static struct platform_device davinci_evm_aemif_device = {
215 .name = "ti-aemif",
216 .id = -1,
217 .dev = {
218 .platform_data = &davinci_evm_aemif_pdata,
219 },
220 .resource = davinci_evm_aemif_resource,
221 .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource),
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222};
223
3e9c18e1 224static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
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225
226static struct platform_device davinci_fb_device = {
227 .name = "davincifb",
228 .id = -1,
229 .dev = {
230 .dma_mask = &davinci_fb_dma_mask,
3e9c18e1 231 .coherent_dma_mask = DMA_BIT_MASK(32),
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232 },
233 .num_resources = 0,
234};
235
314d7389 236static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
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237 .clk_polarity = 0,
238 .hs_polarity = 1,
239 .vs_polarity = 1
240};
241
242#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
243/* Inputs available at the TVP5146 */
314d7389 244static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
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245 {
246 .index = 0,
247 .name = "Composite",
248 .type = V4L2_INPUT_TYPE_CAMERA,
249 .std = TVP514X_STD_ALL,
250 },
251 {
252 .index = 1,
253 .name = "S-Video",
254 .type = V4L2_INPUT_TYPE_CAMERA,
255 .std = TVP514X_STD_ALL,
256 },
257};
258
259/*
260 * this is the route info for connecting each input to decoder
261 * ouput that goes to vpfe. There is a one to one correspondence
262 * with tvp5146_inputs
263 */
314d7389 264static struct vpfe_route dm644xevm_tvp5146_routes[] = {
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265 {
266 .input = INPUT_CVBS_VI2B,
267 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
268 },
269 {
270 .input = INPUT_SVIDEO_VI2C_VI1C,
271 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
272 },
273};
274
314d7389 275static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
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276 {
277 .name = "tvp5146",
278 .grp_id = 0,
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279 .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
280 .inputs = dm644xevm_tvp5146_inputs,
281 .routes = dm644xevm_tvp5146_routes,
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282 .can_route = 1,
283 .ccdc_if_params = {
284 .if_type = VPFE_BT656,
285 .hdpol = VPFE_PINPOL_POSITIVE,
286 .vdpol = VPFE_PINPOL_POSITIVE,
287 },
288 .board_info = {
289 I2C_BOARD_INFO("tvp5146", 0x5d),
314d7389 290 .platform_data = &dm644xevm_tvp5146_pdata,
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291 },
292 },
293};
294
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295static struct vpfe_config dm644xevm_capture_cfg = {
296 .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
077639f4 297 .i2c_adapter_id = 1,
314d7389 298 .sub_devs = dm644xevm_vpfe_sub_devs,
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299 .card_name = "DM6446 EVM",
300 .ccdc = "DM6446 CCDC",
301};
302
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303static struct platform_device rtc_dev = {
304 .name = "rtc_davinci_evm",
305 .id = -1,
306};
7bff3c4c 307
7bff3c4c 308/*----------------------------------------------------------------------*/
8e580411 309#ifdef CONFIG_I2C
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310/*
311 * I2C GPIO expanders
312 */
313
314#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
315
316
317/* U2 -- LEDs */
318
319static struct gpio_led evm_leds[] = {
320 { .name = "DS8", .active_low = 1,
321 .default_trigger = "heartbeat", },
322 { .name = "DS7", .active_low = 1, },
323 { .name = "DS6", .active_low = 1, },
324 { .name = "DS5", .active_low = 1, },
325 { .name = "DS4", .active_low = 1, },
326 { .name = "DS3", .active_low = 1, },
327 { .name = "DS2", .active_low = 1,
328 .default_trigger = "mmc0", },
329 { .name = "DS1", .active_low = 1,
e5808227 330 .default_trigger = "disk-activity", },
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331};
332
333static const struct gpio_led_platform_data evm_led_data = {
334 .num_leds = ARRAY_SIZE(evm_leds),
335 .leds = evm_leds,
336};
337
338static struct platform_device *evm_led_dev;
339
340static int
341evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
342{
343 struct gpio_led *leds = evm_leds;
344 int status;
345
346 while (ngpio--) {
347 leds->gpio = gpio++;
348 leds++;
349 }
350
351 /* what an extremely annoying way to be forced to handle
352 * device unregistration ...
353 */
354 evm_led_dev = platform_device_alloc("leds-gpio", 0);
355 platform_device_add_data(evm_led_dev,
356 &evm_led_data, sizeof evm_led_data);
357
358 evm_led_dev->dev.parent = &client->dev;
359 status = platform_device_add(evm_led_dev);
360 if (status < 0) {
361 platform_device_put(evm_led_dev);
362 evm_led_dev = NULL;
363 }
364 return status;
365}
366
367static int
368evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
369{
370 if (evm_led_dev) {
371 platform_device_unregister(evm_led_dev);
372 evm_led_dev = NULL;
373 }
374 return 0;
375}
376
377static struct pcf857x_platform_data pcf_data_u2 = {
378 .gpio_base = PCF_Uxx_BASE(0),
379 .setup = evm_led_setup,
380 .teardown = evm_led_teardown,
381};
382
383
384/* U18 - A/V clock generator and user switch */
385
386static int sw_gpio;
387
388static ssize_t
389sw_show(struct device *d, struct device_attribute *a, char *buf)
390{
391 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
392
393 strcpy(buf, s);
394 return strlen(s);
395}
396
397static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
398
399static int
400evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
401{
402 int status;
403
404 /* export dip switch option */
405 sw_gpio = gpio + 7;
406 status = gpio_request(sw_gpio, "user_sw");
407 if (status == 0)
408 status = gpio_direction_input(sw_gpio);
409 if (status == 0)
410 status = device_create_file(&client->dev, &dev_attr_user_sw);
411 else
412 gpio_free(sw_gpio);
413 if (status != 0)
414 sw_gpio = -EINVAL;
415
416 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
417 gpio_request(gpio + 3, "pll_fs2");
418 gpio_direction_output(gpio + 3, 0);
419
420 gpio_request(gpio + 2, "pll_fs1");
421 gpio_direction_output(gpio + 2, 0);
422
423 gpio_request(gpio + 1, "pll_sr");
424 gpio_direction_output(gpio + 1, 0);
425
426 return 0;
427}
428
429static int
430evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
431{
432 gpio_free(gpio + 1);
433 gpio_free(gpio + 2);
434 gpio_free(gpio + 3);
435
436 if (sw_gpio > 0) {
437 device_remove_file(&client->dev, &dev_attr_user_sw);
438 gpio_free(sw_gpio);
439 }
440 return 0;
441}
442
443static struct pcf857x_platform_data pcf_data_u18 = {
444 .gpio_base = PCF_Uxx_BASE(1),
445 .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
446 .setup = evm_u18_setup,
447 .teardown = evm_u18_teardown,
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448};
449
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450
451/* U35 - various I/O signals used to manage USB, CF, ATA, etc */
452
453static int
454evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
455{
456 /* p0 = nDRV_VBUS (initial: don't supply it) */
457 gpio_request(gpio + 0, "nDRV_VBUS");
458 gpio_direction_output(gpio + 0, 1);
459
460 /* p1 = VDDIMX_EN */
461 gpio_request(gpio + 1, "VDDIMX_EN");
462 gpio_direction_output(gpio + 1, 1);
463
464 /* p2 = VLYNQ_EN */
465 gpio_request(gpio + 2, "VLYNQ_EN");
466 gpio_direction_output(gpio + 2, 1);
467
468 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
469 gpio_request(gpio + 3, "nCF_RESET");
470 gpio_direction_output(gpio + 3, 0);
471
472 /* (p4 unused) */
473
474 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
475 gpio_request(gpio + 5, "WLAN_RESET");
476 gpio_direction_output(gpio + 5, 1);
477
478 /* p6 = nATA_SEL (initial: select) */
479 gpio_request(gpio + 6, "nATA_SEL");
480 gpio_direction_output(gpio + 6, 0);
481
482 /* p7 = nCF_SEL (initial: deselect) */
483 gpio_request(gpio + 7, "nCF_SEL");
484 gpio_direction_output(gpio + 7, 1);
485
486 return 0;
487}
488
489static int
490evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
491{
492 gpio_free(gpio + 7);
493 gpio_free(gpio + 6);
494 gpio_free(gpio + 5);
495 gpio_free(gpio + 3);
496 gpio_free(gpio + 2);
497 gpio_free(gpio + 1);
498 gpio_free(gpio + 0);
499 return 0;
500}
501
502static struct pcf857x_platform_data pcf_data_u35 = {
503 .gpio_base = PCF_Uxx_BASE(2),
504 .setup = evm_u35_setup,
505 .teardown = evm_u35_teardown,
506};
507
508/*----------------------------------------------------------------------*/
509
510/* Most of this EEPROM is unused, but U-Boot uses some data:
511 * - 0x7f00, 6 bytes Ethernet Address
512 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
513 * - ... newer boards may have more
514 */
d0e47fba 515
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516static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
517 {
518 .name = "macaddr",
519 .offset = 0x7f00,
520 .bytes = ETH_ALEN,
521 }
522};
523
524static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
525 .nvmem_name = "1-00500",
526 .cells = dm644evm_nvmem_cells,
527 .ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
528};
529
530static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
531 .nvmem_name = "1-00500",
532 .cell_name = "macaddr",
533 .dev_id = "davinci_emac.1",
534 .con_id = "mac-address",
535};
536
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537static const struct property_entry eeprom_properties[] = {
538 PROPERTY_ENTRY_U32("pagesize", 64),
539 { }
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540};
541
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542/*
543 * MSP430 supports RTC, card detection, input from IR remote, and
544 * a bit more. It triggers interrupts on GPIO(7) from pressing
545 * buttons on the IR remote, and for card detect switches.
546 */
547static struct i2c_client *dm6446evm_msp;
548
549static int dm6446evm_msp_probe(struct i2c_client *client,
550 const struct i2c_device_id *id)
551{
552 dm6446evm_msp = client;
553 return 0;
554}
555
556static int dm6446evm_msp_remove(struct i2c_client *client)
557{
558 dm6446evm_msp = NULL;
559 return 0;
560}
561
562static const struct i2c_device_id dm6446evm_msp_ids[] = {
563 { "dm6446evm_msp", 0, },
564 { /* end of list */ },
565};
566
567static struct i2c_driver dm6446evm_msp_driver = {
568 .driver.name = "dm6446evm_msp",
569 .id_table = dm6446evm_msp_ids,
570 .probe = dm6446evm_msp_probe,
571 .remove = dm6446evm_msp_remove,
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572};
573
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574static int dm6444evm_msp430_get_pins(void)
575{
576 static const char txbuf[2] = { 2, 4, };
577 char buf[4];
578 struct i2c_msg msg[2] = {
579 {
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580 .flags = 0,
581 .len = 2,
582 .buf = (void __force *)txbuf,
583 },
584 {
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585 .flags = I2C_M_RD,
586 .len = 4,
587 .buf = buf,
588 },
589 };
590 int status;
591
592 if (!dm6446evm_msp)
593 return -ENXIO;
594
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595 msg[0].addr = dm6446evm_msp->addr;
596 msg[1].addr = dm6446evm_msp->addr;
597
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598 /* Command 4 == get input state, returns port 2 and port3 data
599 * S Addr W [A] len=2 [A] cmd=4 [A]
600 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
601 */
602 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
603 if (status < 0)
604 return status;
605
d1a31e97 606 dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
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KH
607
608 return (buf[3] << 8) | buf[2];
609}
610
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KH
611static int dm6444evm_mmc_get_cd(int module)
612{
613 int status = dm6444evm_msp430_get_pins();
614
615 return (status < 0) ? status : !(status & BIT(1));
616}
617
618static int dm6444evm_mmc_get_ro(int module)
619{
620 int status = dm6444evm_msp430_get_pins();
621
622 return (status < 0) ? status : status & BIT(6 + 8);
623}
624
625static struct davinci_mmc_config dm6446evm_mmc_config = {
626 .get_cd = dm6444evm_mmc_get_cd,
627 .get_ro = dm6444evm_mmc_get_ro,
628 .wires = 4,
2dbf56ae
KH
629};
630
7bff3c4c 631static struct i2c_board_info __initdata i2c_info[] = {
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KH
632 {
633 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
634 },
7bff3c4c
DB
635 {
636 I2C_BOARD_INFO("pcf8574", 0x38),
637 .platform_data = &pcf_data_u2,
638 },
639 {
640 I2C_BOARD_INFO("pcf8574", 0x39),
641 .platform_data = &pcf_data_u18,
642 },
643 {
644 I2C_BOARD_INFO("pcf8574", 0x3a),
645 .platform_data = &pcf_data_u35,
646 },
647 {
648 I2C_BOARD_INFO("24c256", 0x50),
4b683bbb 649 .properties = eeprom_properties,
7bff3c4c 650 },
1a7ff8ff
C
651 {
652 I2C_BOARD_INFO("tlv320aic33", 0x1b),
653 },
7bff3c4c
DB
654};
655
9411ac07
SN
656#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
657#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
658
e5353765 659static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
9411ac07 660 .dev_id = "i2c_davinci.1",
e5353765 661 .table = {
7f1015b2 662 GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
e5353765 663 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
7f1015b2 664 GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
e5353765
LW
665 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
666 },
667};
668
7bff3c4c
DB
669/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
670 * which requires 100 usec of idle bus after i2c writes sent to it.
671 */
672static struct davinci_i2c_platform_data i2c_pdata = {
673 .bus_freq = 20 /* kHz */,
674 .bus_delay = 100 /* usec */,
e5353765 675 .gpio_recovery = true,
7bff3c4c
DB
676};
677
678static void __init evm_init_i2c(void)
679{
e5353765 680 gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
7bff3c4c 681 davinci_init_i2c(&i2c_pdata);
d0e47fba 682 i2c_add_driver(&dm6446evm_msp_driver);
7bff3c4c
DB
683 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
684}
8e580411 685#endif
7bff3c4c 686
d5be5f54
MH
687#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
688
689/* venc standard timings */
690static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
691 {
692 .name = "ntsc",
693 .timings_type = VPBE_ENC_STD,
89cdbba8 694 .std_id = V4L2_STD_NTSC,
d5be5f54
MH
695 .interlaced = 1,
696 .xres = 720,
697 .yres = 480,
698 .aspect = {11, 10},
699 .fps = {30000, 1001},
700 .left_margin = 0x79,
701 .upper_margin = 0x10,
702 },
703 {
704 .name = "pal",
705 .timings_type = VPBE_ENC_STD,
89cdbba8 706 .std_id = V4L2_STD_PAL,
d5be5f54
MH
707 .interlaced = 1,
708 .xres = 720,
709 .yres = 576,
710 .aspect = {54, 59},
711 .fps = {25, 1},
712 .left_margin = 0x7e,
713 .upper_margin = 0x16,
714 },
715};
716
717/* venc dv preset timings */
718static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
719 {
720 .name = "480p59_94",
ef2d41b1 721 .timings_type = VPBE_ENC_DV_TIMINGS,
36864082 722 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
d5be5f54
MH
723 .interlaced = 0,
724 .xres = 720,
725 .yres = 480,
726 .aspect = {1, 1},
727 .fps = {5994, 100},
728 .left_margin = 0x80,
729 .upper_margin = 0x20,
730 },
731 {
732 .name = "576p50",
ef2d41b1 733 .timings_type = VPBE_ENC_DV_TIMINGS,
36864082 734 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
d5be5f54
MH
735 .interlaced = 0,
736 .xres = 720,
737 .yres = 576,
738 .aspect = {1, 1},
739 .fps = {50, 1},
740 .left_margin = 0x7e,
741 .upper_margin = 0x30,
742 },
743};
744
745/*
746 * The outputs available from VPBE + encoders. Keep the order same
747 * as that of encoders. First those from venc followed by that from
748 * encoders. Index in the output refers to index on a particular encoder.
749 * Driver uses this index to pass it to encoder when it supports more
750 * than one output. Userspace applications use index of the array to
751 * set an output.
752 */
753static struct vpbe_output dm644xevm_vpbe_outputs[] = {
754 {
755 .output = {
756 .index = 0,
757 .name = "Composite",
758 .type = V4L2_OUTPUT_TYPE_ANALOG,
759 .std = VENC_STD_ALL,
760 .capabilities = V4L2_OUT_CAP_STD,
761 },
caff80c3 762 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
d5be5f54
MH
763 .default_mode = "ntsc",
764 .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
765 .modes = dm644xevm_enc_std_timing,
766 },
767 {
768 .output = {
769 .index = 1,
770 .name = "Component",
771 .type = V4L2_OUTPUT_TYPE_ANALOG,
e32087bc 772 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
d5be5f54 773 },
caff80c3 774 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
d5be5f54
MH
775 .default_mode = "480p59_94",
776 .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
777 .modes = dm644xevm_enc_preset_timing,
778 },
779};
780
781static struct vpbe_config dm644xevm_display_cfg = {
782 .module_name = "dm644x-vpbe-display",
783 .i2c_adapter_id = 1,
784 .osd = {
caff80c3 785 .module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
d5be5f54
MH
786 },
787 .venc = {
caff80c3 788 .module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
d5be5f54
MH
789 },
790 .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
791 .outputs = dm644xevm_vpbe_outputs,
792};
793
7c6337e2 794static struct platform_device *davinci_evm_devices[] __initdata = {
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KH
795 &davinci_fb_device,
796 &rtc_dev,
797};
798
7c6337e2
KH
799static void __init
800davinci_evm_map_io(void)
801{
d0e47fba 802 dm644x_init();
7c6337e2
KH
803}
804
d0e47fba 805static int davinci_phy_fixup(struct phy_device *phydev)
7c6337e2 806{
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KH
807 unsigned int control;
808 /* CRITICAL: Fix for increasing PHY signal drive strength for
809 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
810 * signal strength was low causing TX to fail randomly. The
811 * fix is to Set bit 11 (Increased MII drive strength) of PHY
812 * register 26 (Digital Config register) on this phy. */
813 control = phy_read(phydev, 26);
814 phy_write(phydev, 26, (control | 0x800));
815 return 0;
816}
817
28d4d1d0
SN
818#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
819 IS_ENABLED(CONFIG_PATA_BK3710))
a0a56db9
LP
820
821#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
822
823#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
7c6337e2 824
d0e47fba
KH
825static __init void davinci_evm_init(void)
826{
834acb2a 827 int ret;
d0e47fba 828 struct clk *aemif_clk;
972412b6 829 struct davinci_soc_info *soc_info = &davinci_soc_info;
d0e47fba 830
a5b1a871
DL
831 dm644x_register_clocks();
832
8e730c7f
SN
833 dm644x_init_devices();
834
834acb2a
PA
835 ret = dm644x_gpio_register();
836 if (ret)
837 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
838
d0e47fba 839 aemif_clk = clk_get(NULL, "aemif");
b6f1ffed 840 clk_prepare_enable(aemif_clk);
d0e47fba
KH
841
842 if (HAS_ATA) {
843 if (HAS_NAND || HAS_NOR)
a7ca2bcf
JP
844 pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
845 "\tDisable IDE for NAND/NOR support\n");
7a9978a1 846 davinci_init_ide();
d0e47fba
KH
847 } else if (HAS_NAND || HAS_NOR) {
848 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
849 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
850
851 /* only one device will be jumpered and detected */
852 if (HAS_NAND) {
2ee2948e 853 platform_device_register(&davinci_evm_aemif_device);
8e580411 854#ifdef CONFIG_I2C
d0e47fba 855 evm_leds[7].default_trigger = "nand-disk";
8e580411 856#endif
d0e47fba 857 if (HAS_NOR)
a7ca2bcf 858 pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
d0e47fba
KH
859 } else if (HAS_NOR)
860 platform_device_register(&davinci_evm_norflash_device);
861 }
862
7c6337e2
KH
863 platform_add_devices(davinci_evm_devices,
864 ARRAY_SIZE(davinci_evm_devices));
8e580411 865#ifdef CONFIG_I2C
89c817c4
BG
866 nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
867 nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
7bff3c4c 868 evm_init_i2c();
2dbf56ae 869 davinci_setup_mmc(0, &dm6446evm_mmc_config);
8e580411 870#endif
d5be5f54 871 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
2dbf56ae 872
fcf7157b 873 davinci_serial_init(dm644x_serial_device);
6bce5efd 874 dm644x_init_asp();
d0e47fba 875
60d97a84
SS
876 /* irlml6401 switches over 1A, in under 8 msec */
877 davinci_setup_usb(1000, 8);
878
4bbef1da
AB
879 if (IS_BUILTIN(CONFIG_PHYLIB)) {
880 soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
881 /* Register the fixup for PHY on DaVinci */
882 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
883 davinci_phy_fixup);
884 }
7c6337e2
KH
885}
886
d0e47fba 887MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
7c6337e2 888 /* Maintainer: MontaVista Software <source@mvista.com> */
e7e56014 889 .atag_offset = 0x100,
7c6337e2 890 .map_io = davinci_evm_map_io,
de4f82a2 891 .init_irq = dm644x_init_irq,
96c08173 892 .init_time = dm644x_init_time,
7c6337e2 893 .init_machine = davinci_evm_init,
3aa3e840 894 .init_late = davinci_init_late,
f68deabf 895 .dma_zone_size = SZ_128M,
7c6337e2 896MACHINE_END