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Merge branch 'tracing/core' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / arch / arm / mach-davinci / board-dm644x-evm.c
CommitLineData
7c6337e2
KH		 1/*
2 * TI DaVinci EVM board support
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
7c6337e2
KH		 12#include <linux/init.h>
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
7bff3c4c 15#include <linux/gpio.h>
7bff3c4c
DB		 16#include <linux/i2c.h>
17#include <linux/i2c/pcf857x.h>
18#include <linux/i2c/at24.h>
7c6337e2 19#include <linux/mtd/mtd.h>
d0e47fba 20#include <linux/mtd/nand.h>
7c6337e2
KH		 21#include <linux/mtd/partitions.h>
22#include <linux/mtd/physmap.h>
d0e47fba
KH		 23#include <linux/phy.h>
24#include <linux/clk.h>
ab8e8df8
MK		 25#include <linux/videodev2.h>
26
27#include <media/tvp514x.h>
7c6337e2 28
7c6337e2 29#include <asm/mach-types.h>
7c6337e2 30#include <asm/mach/arch.h>
7c6337e2 31
d0e47fba 32#include <mach/dm644x.h>
a09e64fb 33#include <mach/common.h>
7bff3c4c 34#include <mach/i2c.h>
d0e47fba
KH		 35#include <mach/serial.h>
36#include <mach/mux.h>
d0e47fba 37#include <mach/nand.h>
2dbf56ae 38#include <mach/mmc.h>
355fb4e3 39#include <mach/usb.h>
d0e47fba
KH		 40
41#define DM644X_EVM_PHY_MASK (0x2)
42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
7c6337e2 43
f5c122da 44#define DAVINCI_CFC_ATA_BASE 0x01C66000
f5c122da 45
d0e47fba
KH		 46#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
47#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
48#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
49#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
50#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
7c6337e2 51
d0e47fba
KH		 52#define LXT971_PHY_ID (0x001378e2)
53#define LXT971_PHY_MASK (0xfffffff0)
7c6337e2 54
7bff3c4c 55static struct mtd_partition davinci_evm_norflash_partitions[] = {
d0e47fba 56 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
7c6337e2
KH		 57 {
58 .name = "bootloader",
59 .offset = 0,
d0e47fba 60 .size = 5 * SZ_64K,
7c6337e2
KH		 61 .mask_flags = MTD_WRITEABLE, /* force read-only */
62 },
63 /* bootloader params in the next 1 sectors */
64 {
65 .name = "params",
66 .offset = MTDPART_OFS_APPEND,
67 .size = SZ_64K,
68 .mask_flags = 0,
69 },
70 /* kernel */
71 {
72 .name = "kernel",
73 .offset = MTDPART_OFS_APPEND,
74 .size = SZ_2M,
75 .mask_flags = 0
76 },
77 /* file system */
78 {
79 .name = "filesystem",
80 .offset = MTDPART_OFS_APPEND,
81 .size = MTDPART_SIZ_FULL,
82 .mask_flags = 0
83 }
84};
85
7bff3c4c 86static struct physmap_flash_data davinci_evm_norflash_data = {
7c6337e2 87 .width = 2,
7bff3c4c
DB		 88 .parts = davinci_evm_norflash_partitions,
89 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
7c6337e2
KH		 90};
91
92/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
93 * limits addresses to 16M, so using addresses past 16M will wrap */
7bff3c4c
DB		 94static struct resource davinci_evm_norflash_resource = {
95 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
96 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
7c6337e2
KH		 97 .flags = IORESOURCE_MEM,
98};
99
7bff3c4c 100static struct platform_device davinci_evm_norflash_device = {
7c6337e2
KH		 101 .name = "physmap-flash",
102 .id = 0,
103 .dev = {
7bff3c4c 104 .platform_data = &davinci_evm_norflash_data,
7c6337e2
KH		 105 },
106 .num_resources = 1,
7bff3c4c
DB		 107 .resource = &davinci_evm_norflash_resource,
108};
109
3e9c18e1
DB		 110/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
111 * It may used instead of the (default) NOR chip to boot, using TI's
112 * tools to install the secondary boot loader (UBL) and U-Boot.
113 */
d0e47fba 114struct mtd_partition davinci_evm_nandflash_partition[] = {
3e9c18e1
DB		 115 /* Bootloader layout depends on whose u-boot is installed, but we
116 * can hide all the details.
117 * - block 0 for u-boot environment ... in mainline u-boot
118 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
119 * - blocks 6...? for u-boot
120 * - blocks 16..23 for u-boot environment ... in TI's u-boot
121 */
122 {
123 .name = "bootloader",
124 .offset = 0,
125 .size = SZ_256K + SZ_128K,
126 .mask_flags = MTD_WRITEABLE, /* force read-only */
127 },
128 /* Kernel */
d0e47fba 129 {
3e9c18e1
DB		 130 .name = "kernel",
131 .offset = MTDPART_OFS_APPEND,
132 .size = SZ_4M,
133 .mask_flags = 0,
134 },
135 /* File system (older GIT kernels started this on the 5MB mark) */
136 {
137 .name = "filesystem",
138 .offset = MTDPART_OFS_APPEND,
d0e47fba
KH		 139 .size = MTDPART_SIZ_FULL,
140 .mask_flags = 0,
141 }
3e9c18e1
DB		 142 /* A few blocks at end hold a flash BBT ... created by TI's CCS
143 * using flashwriter_nand.out, but ignored by TI's versions of
144 * Linux and u-boot. We boot faster by using them.
145 */
d0e47fba 146};
7bff3c4c 147
d0e47fba
KH		 148static struct davinci_nand_pdata davinci_evm_nandflash_data = {
149 .parts = davinci_evm_nandflash_partition,
150 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
151 .ecc_mode = NAND_ECC_HW,
3e9c18e1 152 .options = NAND_USE_FLASH_BBT,
d0e47fba
KH		 153};
154
155static struct resource davinci_evm_nandflash_resource[] = {
156 {
157 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
158 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
159 .flags = IORESOURCE_MEM,
160 }, {
161 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
162 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
163 .flags = IORESOURCE_MEM,
164 },
165};
166
167static struct platform_device davinci_evm_nandflash_device = {
168 .name = "davinci_nand",
169 .id = 0,
170 .dev = {
171 .platform_data = &davinci_evm_nandflash_data,
172 },
173 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
174 .resource = davinci_evm_nandflash_resource,
175};
176
3e9c18e1 177static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
d0e47fba
KH		 178
179static struct platform_device davinci_fb_device = {
180 .name = "davincifb",
181 .id = -1,
182 .dev = {
183 .dma_mask = &davinci_fb_dma_mask,
3e9c18e1 184 .coherent_dma_mask = DMA_BIT_MASK(32),
d0e47fba
KH		 185 },
186 .num_resources = 0,
187};
188
ab8e8df8
MK		 189static struct tvp514x_platform_data tvp5146_pdata = {
190 .clk_polarity = 0,
191 .hs_polarity = 1,
192 .vs_polarity = 1
193};
194
195#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
196/* Inputs available at the TVP5146 */
197static struct v4l2_input tvp5146_inputs[] = {
198 {
199 .index = 0,
200 .name = "Composite",
201 .type = V4L2_INPUT_TYPE_CAMERA,
202 .std = TVP514X_STD_ALL,
203 },
204 {
205 .index = 1,
206 .name = "S-Video",
207 .type = V4L2_INPUT_TYPE_CAMERA,
208 .std = TVP514X_STD_ALL,
209 },
210};
211
212/*
213 * this is the route info for connecting each input to decoder
214 * ouput that goes to vpfe. There is a one to one correspondence
215 * with tvp5146_inputs
216 */
217static struct vpfe_route tvp5146_routes[] = {
218 {
219 .input = INPUT_CVBS_VI2B,
220 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
221 },
222 {
223 .input = INPUT_SVIDEO_VI2C_VI1C,
224 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
225 },
226};
227
228static struct vpfe_subdev_info vpfe_sub_devs[] = {
229 {
230 .name = "tvp5146",
231 .grp_id = 0,
232 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
233 .inputs = tvp5146_inputs,
234 .routes = tvp5146_routes,
235 .can_route = 1,
236 .ccdc_if_params = {
237 .if_type = VPFE_BT656,
238 .hdpol = VPFE_PINPOL_POSITIVE,
239 .vdpol = VPFE_PINPOL_POSITIVE,
240 },
241 .board_info = {
242 I2C_BOARD_INFO("tvp5146", 0x5d),
243 .platform_data = &tvp5146_pdata,
244 },
245 },
246};
247
248static struct vpfe_config vpfe_cfg = {
249 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
077639f4 250 .i2c_adapter_id = 1,
ab8e8df8
MK		 251 .sub_devs = vpfe_sub_devs,
252 .card_name = "DM6446 EVM",
253 .ccdc = "DM6446 CCDC",
254};
255
d0e47fba
KH		 256static struct platform_device rtc_dev = {
257 .name = "rtc_davinci_evm",
258 .id = -1,
259};
7bff3c4c
DB		 260
261static struct resource ide_resources[] = {
262 {
263 .start = DAVINCI_CFC_ATA_BASE,
264 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
265 .flags = IORESOURCE_MEM,
266 },
267 {
268 .start = IRQ_IDE,
269 .end = IRQ_IDE,
270 .flags = IORESOURCE_IRQ,
271 },
272};
273
a029b706 274static u64 ide_dma_mask = DMA_BIT_MASK(32);
7bff3c4c
DB		 275
276static struct platform_device ide_dev = {
277 .name = "palm_bk3710",
278 .id = -1,
279 .resource = ide_resources,
280 .num_resources = ARRAY_SIZE(ide_resources),
281 .dev = {
282 .dma_mask = &ide_dma_mask,
a029b706 283 .coherent_dma_mask = DMA_BIT_MASK(32),
7bff3c4c
DB		 284 },
285};
286
61aa0732 287static struct snd_platform_data dm644x_evm_snd_data;
25acf553 288
7bff3c4c
DB		 289/*----------------------------------------------------------------------*/
290
291/*
292 * I2C GPIO expanders
293 */
294
295#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
296
297
298/* U2 -- LEDs */
299
300static struct gpio_led evm_leds[] = {
301 { .name = "DS8", .active_low = 1,
302 .default_trigger = "heartbeat", },
303 { .name = "DS7", .active_low = 1, },
304 { .name = "DS6", .active_low = 1, },
305 { .name = "DS5", .active_low = 1, },
306 { .name = "DS4", .active_low = 1, },
307 { .name = "DS3", .active_low = 1, },
308 { .name = "DS2", .active_low = 1,
309 .default_trigger = "mmc0", },
310 { .name = "DS1", .active_low = 1,
311 .default_trigger = "ide-disk", },
312};
313
314static const struct gpio_led_platform_data evm_led_data = {
315 .num_leds = ARRAY_SIZE(evm_leds),
316 .leds = evm_leds,
317};
318
319static struct platform_device *evm_led_dev;
320
321static int
322evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
323{
324 struct gpio_led *leds = evm_leds;
325 int status;
326
327 while (ngpio--) {
328 leds->gpio = gpio++;
329 leds++;
330 }
331
332 /* what an extremely annoying way to be forced to handle
333 * device unregistration ...
334 */
335 evm_led_dev = platform_device_alloc("leds-gpio", 0);
336 platform_device_add_data(evm_led_dev,
337 &evm_led_data, sizeof evm_led_data);
338
339 evm_led_dev->dev.parent = &client->dev;
340 status = platform_device_add(evm_led_dev);
341 if (status < 0) {
342 platform_device_put(evm_led_dev);
343 evm_led_dev = NULL;
344 }
345 return status;
346}
347
348static int
349evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
350{
351 if (evm_led_dev) {
352 platform_device_unregister(evm_led_dev);
353 evm_led_dev = NULL;
354 }
355 return 0;
356}
357
358static struct pcf857x_platform_data pcf_data_u2 = {
359 .gpio_base = PCF_Uxx_BASE(0),
360 .setup = evm_led_setup,
361 .teardown = evm_led_teardown,
362};
363
364
365/* U18 - A/V clock generator and user switch */
366
367static int sw_gpio;
368
369static ssize_t
370sw_show(struct device *d, struct device_attribute *a, char *buf)
371{
372 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
373
374 strcpy(buf, s);
375 return strlen(s);
376}
377
378static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
379
380static int
381evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
382{
383 int status;
384
385 /* export dip switch option */
386 sw_gpio = gpio + 7;
387 status = gpio_request(sw_gpio, "user_sw");
388 if (status == 0)
389 status = gpio_direction_input(sw_gpio);
390 if (status == 0)
391 status = device_create_file(&client->dev, &dev_attr_user_sw);
392 else
393 gpio_free(sw_gpio);
394 if (status != 0)
395 sw_gpio = -EINVAL;
396
397 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
398 gpio_request(gpio + 3, "pll_fs2");
399 gpio_direction_output(gpio + 3, 0);
400
401 gpio_request(gpio + 2, "pll_fs1");
402 gpio_direction_output(gpio + 2, 0);
403
404 gpio_request(gpio + 1, "pll_sr");
405 gpio_direction_output(gpio + 1, 0);
406
407 return 0;
408}
409
410static int
411evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
412{
413 gpio_free(gpio + 1);
414 gpio_free(gpio + 2);
415 gpio_free(gpio + 3);
416
417 if (sw_gpio > 0) {
418 device_remove_file(&client->dev, &dev_attr_user_sw);
419 gpio_free(sw_gpio);
420 }
421 return 0;
422}
423
424static struct pcf857x_platform_data pcf_data_u18 = {
425 .gpio_base = PCF_Uxx_BASE(1),
426 .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
427 .setup = evm_u18_setup,
428 .teardown = evm_u18_teardown,
7c6337e2
KH		 429};
430
7bff3c4c
DB		 431
432/* U35 - various I/O signals used to manage USB, CF, ATA, etc */
433
434static int
435evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
436{
437 /* p0 = nDRV_VBUS (initial: don't supply it) */
438 gpio_request(gpio + 0, "nDRV_VBUS");
439 gpio_direction_output(gpio + 0, 1);
440
441 /* p1 = VDDIMX_EN */
442 gpio_request(gpio + 1, "VDDIMX_EN");
443 gpio_direction_output(gpio + 1, 1);
444
445 /* p2 = VLYNQ_EN */
446 gpio_request(gpio + 2, "VLYNQ_EN");
447 gpio_direction_output(gpio + 2, 1);
448
449 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
450 gpio_request(gpio + 3, "nCF_RESET");
451 gpio_direction_output(gpio + 3, 0);
452
453 /* (p4 unused) */
454
455 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
456 gpio_request(gpio + 5, "WLAN_RESET");
457 gpio_direction_output(gpio + 5, 1);
458
459 /* p6 = nATA_SEL (initial: select) */
460 gpio_request(gpio + 6, "nATA_SEL");
461 gpio_direction_output(gpio + 6, 0);
462
463 /* p7 = nCF_SEL (initial: deselect) */
464 gpio_request(gpio + 7, "nCF_SEL");
465 gpio_direction_output(gpio + 7, 1);
466
d0e47fba
KH		 467 /* irlml6401 switches over 1A, in under 8 msec;
468 * now it can be managed by nDRV_VBUS ...
469 */
355fb4e3 470 davinci_setup_usb(1000, 8);
34f32c97 471
7bff3c4c
DB		 472 return 0;
473}
474
475static int
476evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
477{
478 gpio_free(gpio + 7);
479 gpio_free(gpio + 6);
480 gpio_free(gpio + 5);
481 gpio_free(gpio + 3);
482 gpio_free(gpio + 2);
483 gpio_free(gpio + 1);
484 gpio_free(gpio + 0);
485 return 0;
486}
487
488static struct pcf857x_platform_data pcf_data_u35 = {
489 .gpio_base = PCF_Uxx_BASE(2),
490 .setup = evm_u35_setup,
491 .teardown = evm_u35_teardown,
492};
493
494/*----------------------------------------------------------------------*/
495
496/* Most of this EEPROM is unused, but U-Boot uses some data:
497 * - 0x7f00, 6 bytes Ethernet Address
498 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
499 * - ... newer boards may have more
500 */
d0e47fba 501
7bff3c4c
DB		 502static struct at24_platform_data eeprom_info = {
503 .byte_len = (256*1024) / 8,
504 .page_size = 64,
505 .flags = AT24_FLAG_ADDR16,
b14dc0f9
MG		 506 .setup = davinci_get_mac_addr,
507 .context = (void *)0x7f00,
d0e47fba
KH		 508};
509
d0e47fba
KH		 510/*
511 * MSP430 supports RTC, card detection, input from IR remote, and
512 * a bit more. It triggers interrupts on GPIO(7) from pressing
513 * buttons on the IR remote, and for card detect switches.
514 */
515static struct i2c_client *dm6446evm_msp;
516
517static int dm6446evm_msp_probe(struct i2c_client *client,
518 const struct i2c_device_id *id)
519{
520 dm6446evm_msp = client;
521 return 0;
522}
523
524static int dm6446evm_msp_remove(struct i2c_client *client)
525{
526 dm6446evm_msp = NULL;
527 return 0;
528}
529
530static const struct i2c_device_id dm6446evm_msp_ids[] = {
531 { "dm6446evm_msp", 0, },
532 { /* end of list */ },
533};
534
535static struct i2c_driver dm6446evm_msp_driver = {
536 .driver.name = "dm6446evm_msp",
537 .id_table = dm6446evm_msp_ids,
538 .probe = dm6446evm_msp_probe,
539 .remove = dm6446evm_msp_remove,
7bff3c4c
DB		 540};
541
d0e47fba
KH		 542static int dm6444evm_msp430_get_pins(void)
543{
544 static const char txbuf[2] = { 2, 4, };
545 char buf[4];
546 struct i2c_msg msg[2] = {
547 {
548 .addr = dm6446evm_msp->addr,
549 .flags = 0,
550 .len = 2,
551 .buf = (void __force *)txbuf,
552 },
553 {
554 .addr = dm6446evm_msp->addr,
555 .flags = I2C_M_RD,
556 .len = 4,
557 .buf = buf,
558 },
559 };
560 int status;
561
562 if (!dm6446evm_msp)
563 return -ENXIO;
564
565 /* Command 4 == get input state, returns port 2 and port3 data
566 * S Addr W [A] len=2 [A] cmd=4 [A]
567 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
568 */
569 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
570 if (status < 0)
571 return status;
572
573 dev_dbg(&dm6446evm_msp->dev,
574 "PINS: %02x %02x %02x %02x\n",
575 buf[0], buf[1], buf[2], buf[3]);
576
577 return (buf[3] << 8) | buf[2];
578}
579
2dbf56ae
KH		 580static int dm6444evm_mmc_get_cd(int module)
581{
582 int status = dm6444evm_msp430_get_pins();
583
584 return (status < 0) ? status : !(status & BIT(1));
585}
586
587static int dm6444evm_mmc_get_ro(int module)
588{
589 int status = dm6444evm_msp430_get_pins();
590
591 return (status < 0) ? status : status & BIT(6 + 8);
592}
593
594static struct davinci_mmc_config dm6446evm_mmc_config = {
595 .get_cd = dm6444evm_mmc_get_cd,
596 .get_ro = dm6444evm_mmc_get_ro,
597 .wires = 4,
598 .version = MMC_CTLR_VERSION_1
599};
600
7bff3c4c 601static struct i2c_board_info __initdata i2c_info[] = {
d0e47fba
KH		 602 {
603 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
604 },
7bff3c4c
DB		 605 {
606 I2C_BOARD_INFO("pcf8574", 0x38),
607 .platform_data = &pcf_data_u2,
608 },
609 {
610 I2C_BOARD_INFO("pcf8574", 0x39),
611 .platform_data = &pcf_data_u18,
612 },
613 {
614 I2C_BOARD_INFO("pcf8574", 0x3a),
615 .platform_data = &pcf_data_u35,
616 },
617 {
618 I2C_BOARD_INFO("24c256", 0x50),
619 .platform_data = &eeprom_info,
620 },
1a7ff8ff
C		 621 {
622 I2C_BOARD_INFO("tlv320aic33", 0x1b),
623 },
7bff3c4c
DB		 624};
625
626/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
627 * which requires 100 usec of idle bus after i2c writes sent to it.
628 */
629static struct davinci_i2c_platform_data i2c_pdata = {
630 .bus_freq = 20 /* kHz */,
631 .bus_delay = 100 /* usec */,
632};
633
634static void __init evm_init_i2c(void)
635{
636 davinci_init_i2c(&i2c_pdata);
d0e47fba 637 i2c_add_driver(&dm6446evm_msp_driver);
7bff3c4c
DB		 638 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
639}
640
7c6337e2 641static struct platform_device *davinci_evm_devices[] __initdata = {
d0e47fba
KH		 642 &davinci_fb_device,
643 &rtc_dev,
644};
645
646static struct davinci_uart_config uart_config __initdata = {
647 .enabled_uarts = (1 << 0),
7c6337e2
KH		 648};
649
650static void __init
651davinci_evm_map_io(void)
652{
ab8e8df8
MK		 653 /* setup input configuration for VPFE input devices */
654 dm644x_set_vpfe_config(&vpfe_cfg);
d0e47fba 655 dm644x_init();
7c6337e2
KH		 656}
657
d0e47fba 658static int davinci_phy_fixup(struct phy_device *phydev)
7c6337e2 659{
d0e47fba
KH		 660 unsigned int control;
661 /* CRITICAL: Fix for increasing PHY signal drive strength for
662 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
663 * signal strength was low causing TX to fail randomly. The
664 * fix is to Set bit 11 (Increased MII drive strength) of PHY
665 * register 26 (Digital Config register) on this phy. */
666 control = phy_read(phydev, 26);
667 phy_write(phydev, 26, (control | 0x800));
668 return 0;
669}
670
7bff3c4c
DB		 671#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
672 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
d0e47fba
KH		 673#define HAS_ATA 1
674#else
675#define HAS_ATA 0
676#endif
677
7bff3c4c
DB		 678#if defined(CONFIG_MTD_PHYSMAP) || \
679 defined(CONFIG_MTD_PHYSMAP_MODULE)
d0e47fba
KH		 680#define HAS_NOR 1
681#else
682#define HAS_NOR 0
7bff3c4c 683#endif
d0e47fba
KH		 684
685#if defined(CONFIG_MTD_NAND_DAVINCI) || \
686 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
687#define HAS_NAND 1
688#else
689#define HAS_NAND 0
7c6337e2
KH		 690#endif
691
d0e47fba
KH		 692static __init void davinci_evm_init(void)
693{
694 struct clk *aemif_clk;
972412b6 695 struct davinci_soc_info *soc_info = &davinci_soc_info;
d0e47fba
KH		 696
697 aemif_clk = clk_get(NULL, "aemif");
698 clk_enable(aemif_clk);
699
700 if (HAS_ATA) {
701 if (HAS_NAND || HAS_NOR)
702 pr_warning("WARNING: both IDE and Flash are "
703 "enabled, but they share AEMIF pins.\n"
704 "\tDisable IDE for NAND/NOR support.\n");
705 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
706 davinci_cfg_reg(DM644X_ATAEN);
707 davinci_cfg_reg(DM644X_HDIREN);
708 platform_device_register(&ide_dev);
709 } else if (HAS_NAND || HAS_NOR) {
710 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
711 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
712
713 /* only one device will be jumpered and detected */
714 if (HAS_NAND) {
715 platform_device_register(&davinci_evm_nandflash_device);
716 evm_leds[7].default_trigger = "nand-disk";
717 if (HAS_NOR)
718 pr_warning("WARNING: both NAND and NOR flash "
719 "are enabled; disable one of them.\n");
720 } else if (HAS_NOR)
721 platform_device_register(&davinci_evm_norflash_device);
722 }
723
7c6337e2
KH		 724 platform_add_devices(davinci_evm_devices,
725 ARRAY_SIZE(davinci_evm_devices));
7bff3c4c 726 evm_init_i2c();
d0e47fba 727
2dbf56ae
KH		 728 davinci_setup_mmc(0, &dm6446evm_mmc_config);
729
d0e47fba 730 davinci_serial_init(&uart_config);
25acf553 731 dm644x_init_asp(&dm644x_evm_snd_data);
d0e47fba 732
972412b6
MG		 733 soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
734 soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
ac7b75b5 735
d0e47fba
KH		 736 /* Register the fixup for PHY on DaVinci */
737 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
738 davinci_phy_fixup);
739
7c6337e2
KH		 740}
741
742static __init void davinci_evm_irq_init(void)
743{
744 davinci_irq_init();
745}
746
d0e47fba 747MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
7c6337e2
KH		 748 /* Maintainer: MontaVista Software <source@mvista.com> */
749 .phys_io = IO_PHYS,
ac7643e4 750 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
7c6337e2
KH		 751 .boot_params = (DAVINCI_DDR_BASE + 0x100),
752 .map_io = davinci_evm_map_io,
753 .init_irq = davinci_evm_irq_init,
754 .timer = &davinci_timer,
755 .init_machine = davinci_evm_init,
756MACHINE_END
Linux 6.x block layer and io_uring tree(s)