projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'mvebu-dt-4.19-1' of git://git.infradead.org/linux-mvebu into next/dt
[linux-block.git] / arch / arm / mach-davinci / board-da850-evm.c
CommitLineData
0fbc5592
SR		 1/*
2 * TI DA850/OMAP-L138 EVM board
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/board-da830-evm.c
7 * Original Copyrights follow:
8 *
9 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
0fbc5592 14#include <linux/console.h>
6809084a
MP		 15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <linux/gpio_keys.h>
bdf0e836 18#include <linux/gpio/machine.h>
6809084a
MP		 19#include <linux/init.h>
20#include <linux/kernel.h>
f46f335c 21#include <linux/leds.h>
0fbc5592 22#include <linux/i2c.h>
25f73ed5 23#include <linux/platform_data/at24.h>
5877457a 24#include <linux/platform_data/pca953x.h>
75929f5e 25#include <linux/input.h>
6809084a 26#include <linux/input/tps6507x-ts.h>
0bc20bba 27#include <linux/mfd/tps6507x.h>
38beb929 28#include <linux/mtd/mtd.h>
d4092d76 29#include <linux/mtd/rawnand.h>
38beb929 30#include <linux/mtd/partitions.h>
7c5ec609 31#include <linux/mtd/physmap.h>
6809084a 32#include <linux/platform_device.h>
b856671e 33#include <linux/platform_data/gpio-davinci.h>
6809084a
MP		 34#include <linux/platform_data/mtd-davinci.h>
35#include <linux/platform_data/mtd-davinci-aemif.h>
36#include <linux/platform_data/spi-davinci.h>
ae41d17a 37#include <linux/platform_data/uio_pruss.h>
a9eb1f67 38#include <linux/regulator/machine.h>
8b24599e 39#include <linux/regulator/tps6507x.h>
9e9bc235 40#include <linux/regulator/fixed.h>
fdce5568
SN		 41#include <linux/spi/spi.h>
42#include <linux/spi/flash.h>
0fbc5592 43
b856671e 44#include <mach/common.h>
3acf731c 45#include "cp_intc.h"
0fbc5592 46#include <mach/da8xx.h>
7761ef67 47#include <mach/mux.h>
3acf731c 48#include "sram.h"
6809084a
MP		 49
50#include <asm/mach-types.h>
51#include <asm/mach/arch.h>
52#include <asm/system_info.h>
0fbc5592 53
b5dcee22
MCC		 54#include <media/i2c/tvp514x.h>
55#include <media/i2c/adv7343.h>
1e046d17 56
f6f97588 57#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
7761ef67 58#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
5cbdf276 59#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
5cbdf276 60
2206771c
C		 61#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
62
fdce5568
SN		 63static struct mtd_partition da850evm_spiflash_part[] = {
64 [0] = {
65 .name = "UBL",
66 .offset = 0,
67 .size = SZ_64K,
68 .mask_flags = MTD_WRITEABLE,
69 },
70 [1] = {
71 .name = "U-Boot",
72 .offset = MTDPART_OFS_APPEND,
73 .size = SZ_512K,
74 .mask_flags = MTD_WRITEABLE,
75 },
76 [2] = {
77 .name = "U-Boot-Env",
78 .offset = MTDPART_OFS_APPEND,
79 .size = SZ_64K,
80 .mask_flags = MTD_WRITEABLE,
81 },
82 [3] = {
83 .name = "Kernel",
84 .offset = MTDPART_OFS_APPEND,
85 .size = SZ_2M + SZ_512K,
86 .mask_flags = 0,
87 },
88 [4] = {
89 .name = "Filesystem",
90 .offset = MTDPART_OFS_APPEND,
91 .size = SZ_4M,
92 .mask_flags = 0,
93 },
94 [5] = {
95 .name = "MAC-Address",
96 .offset = SZ_8M - SZ_64K,
97 .size = SZ_64K,
98 .mask_flags = MTD_WRITEABLE,
99 },
100};
101
102static struct flash_platform_data da850evm_spiflash_data = {
103 .name = "m25p80",
104 .parts = da850evm_spiflash_part,
105 .nr_parts = ARRAY_SIZE(da850evm_spiflash_part),
106 .type = "m25p64",
107};
108
109static struct davinci_spi_config da850evm_spiflash_cfg = {
110 .io_type = SPI_IO_TYPE_DMA,
111 .c2tdelay = 8,
112 .t2cdelay = 8,
113};
114
115static struct spi_board_info da850evm_spi_info[] = {
116 {
117 .modalias = "m25p80",
118 .platform_data = &da850evm_spiflash_data,
119 .controller_data = &da850evm_spiflash_cfg,
120 .mode = SPI_MODE_0,
121 .max_speed_hz = 30000000,
122 .bus_num = 1,
123 .chip_select = 0,
124 },
125};
126
810198bc
RS		 127#ifdef CONFIG_MTD
128static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
129{
130 char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
131 size_t retlen;
132
133 if (!strcmp(mtd->name, "MAC-Address")) {
329ad399 134 mtd_read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
810198bc
RS		 135 if (retlen == ETH_ALEN)
136 pr_info("Read MAC addr from SPI Flash: %pM\n",
137 mac_addr);
138 }
139}
140
141static struct mtd_notifier da850evm_spi_notifier = {
142 .add = da850_evm_m25p80_notify_add,
143};
144
145static void da850_evm_setup_mac_addr(void)
146{
147 register_mtd_user(&da850evm_spi_notifier);
148}
149#else
150static void da850_evm_setup_mac_addr(void) { }
151#endif
152
7c5ec609
SR		 153static struct mtd_partition da850_evm_norflash_partition[] = {
154 {
e2abd5a2 155 .name = "bootloaders + env",
7c5ec609 156 .offset = 0,
e2abd5a2
SR		 157 .size = SZ_512K,
158 .mask_flags = MTD_WRITEABLE,
159 },
160 {
161 .name = "kernel",
162 .offset = MTDPART_OFS_APPEND,
163 .size = SZ_2M,
164 .mask_flags = 0,
165 },
166 {
167 .name = "filesystem",
168 .offset = MTDPART_OFS_APPEND,
7c5ec609
SR		 169 .size = MTDPART_SIZ_FULL,
170 .mask_flags = 0,
171 },
172};
173
174static struct physmap_flash_data da850_evm_norflash_data = {
175 .width = 2,
176 .parts = da850_evm_norflash_partition,
177 .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
178};
179
180static struct resource da850_evm_norflash_resource[] = {
181 {
182 .start = DA8XX_AEMIF_CS2_BASE,
183 .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
184 .flags = IORESOURCE_MEM,
185 },
186};
187
188static struct platform_device da850_evm_norflash_device = {
189 .name = "physmap-flash",
190 .id = 0,
191 .dev = {
192 .platform_data = &da850_evm_norflash_data,
193 },
194 .num_resources = 1,
195 .resource = da850_evm_norflash_resource,
196};
197
38beb929
SR		 198/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
199 * (128K blocks). It may be used instead of the (default) SPI flash
200 * to boot, using TI's tools to install the secondary boot loader
201 * (UBL) and U-Boot.
202 */
db549d22 203static struct mtd_partition da850_evm_nandflash_partition[] = {
38beb929
SR		 204 {
205 .name = "u-boot env",
206 .offset = 0,
207 .size = SZ_128K,
208 .mask_flags = MTD_WRITEABLE,
209 },
210 {
211 .name = "UBL",
212 .offset = MTDPART_OFS_APPEND,
213 .size = SZ_128K,
214 .mask_flags = MTD_WRITEABLE,
215 },
216 {
217 .name = "u-boot",
218 .offset = MTDPART_OFS_APPEND,
219 .size = 4 * SZ_128K,
220 .mask_flags = MTD_WRITEABLE,
221 },
222 {
223 .name = "kernel",
224 .offset = 0x200000,
225 .size = SZ_2M,
226 .mask_flags = 0,
227 },
228 {
229 .name = "filesystem",
230 .offset = MTDPART_OFS_APPEND,
231 .size = MTDPART_SIZ_FULL,
232 .mask_flags = 0,
233 },
234};
235
18a8505c
SN		 236static struct davinci_aemif_timing da850_evm_nandflash_timing = {
237 .wsetup = 24,
238 .wstrobe = 21,
239 .whold = 14,
240 .rsetup = 19,
241 .rstrobe = 50,
242 .rhold = 0,
243 .ta = 20,
244};
245
38beb929 246static struct davinci_nand_pdata da850_evm_nandflash_data = {
4fe714c0 247 .core_chipsel = 1,
38beb929
SR		 248 .parts = da850_evm_nandflash_partition,
249 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
250 .ecc_mode = NAND_ECC_HW,
fc42e335 251 .ecc_bits = 4,
bb9ebd4e 252 .bbt_options = NAND_BBT_USE_FLASH,
18a8505c 253 .timing = &da850_evm_nandflash_timing,
38beb929
SR		 254};
255
256static struct resource da850_evm_nandflash_resource[] = {
257 {
258 .start = DA8XX_AEMIF_CS3_BASE,
259 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .start = DA8XX_AEMIF_CTL_BASE,
264 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
265 .flags = IORESOURCE_MEM,
266 },
267};
268
269static struct platform_device da850_evm_nandflash_device = {
270 .name = "davinci_nand",
271 .id = 1,
272 .dev = {
273 .platform_data = &da850_evm_nandflash_data,
274 },
275 .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
276 .resource = da850_evm_nandflash_resource,
277};
278
59858b71 279static struct platform_device *da850_evm_devices[] = {
039c5ee3
SR		 280 &da850_evm_nandflash_device,
281 &da850_evm_norflash_device,
282};
283
284#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
285#define DA8XX_AEMIF_ASIZE_16BIT 0x1
286
287static void __init da850_evm_init_nor(void)
288{
289 void __iomem *aemif_addr;
290
291 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
292
293 /* Configure data bus width of CS2 to 16 bit */
294 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
295 DA8XX_AEMIF_ASIZE_16BIT,
296 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
297
298 iounmap(aemif_addr);
299}
300
f48ecc2f
SS		 301static const short da850_evm_nand_pins[] = {
302 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
303 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
304 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
305 DA850_NEMA_WE, DA850_NEMA_OE,
306 -1
307};
308
309static const short da850_evm_nor_pins[] = {
310 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
311 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
312 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
313 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
314 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
315 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
316 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
317 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
318 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
319 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
320 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
321 DA850_EMA_A_22, DA850_EMA_A_23,
322 -1
323};
324
a0a56db9 325#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
039c5ee3 326
f48ecc2f 327static inline void da850_evm_setup_nor_nand(void)
039c5ee3
SR		 328{
329 int ret = 0;
330
b688c2fb 331 if (!HAS_MMC) {
f48ecc2f 332 ret = davinci_cfg_reg_list(da850_evm_nand_pins);
039c5ee3 333 if (ret)
6c7c23cc
RT		 334 pr_warn("%s: NAND mux setup failed: %d\n",
335 __func__, ret);
039c5ee3 336
f48ecc2f 337 ret = davinci_cfg_reg_list(da850_evm_nor_pins);
039c5ee3 338 if (ret)
6c7c23cc
RT		 339 pr_warn("%s: NOR mux setup failed: %d\n",
340 __func__, ret);
039c5ee3
SR		 341
342 da850_evm_init_nor();
343
344 platform_add_devices(da850_evm_devices,
345 ARRAY_SIZE(da850_evm_devices));
67f5185c
IK		 346
347 if (davinci_aemif_setup(&da850_evm_nandflash_device))
348 pr_warn("%s: Cannot configure AEMIF.\n", __func__);
039c5ee3
SR		 349 }
350}
75e2ea64 351
bae10587
SN		 352#ifdef CONFIG_DA850_UI_RMII
353static inline void da850_evm_setup_emac_rmii(int rmii_sel)
354{
355 struct davinci_soc_info *soc_info = &davinci_soc_info;
356
357 soc_info->emac_pdata->rmii_en = 1;
47e7cb14 358 gpio_set_value_cansleep(rmii_sel, 0);
bae10587
SN		 359}
360#else
361static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
362#endif
363
75929f5e
BG		 364
365#define DA850_KEYS_DEBOUNCE_MS 10
366/*
367 * At 200ms polling interval it is possible to miss an
368 * event by tapping very lightly on the push button but most
369 * pushes do result in an event; longer intervals require the
370 * user to hold the button whereas shorter intervals require
371 * more CPU time for polling.
372 */
373#define DA850_GPIO_KEYS_POLL_MS 200
374
375enum da850_evm_ui_exp_pins {
376 DA850_EVM_UI_EXP_SEL_C = 5,
377 DA850_EVM_UI_EXP_SEL_B,
378 DA850_EVM_UI_EXP_SEL_A,
379 DA850_EVM_UI_EXP_PB8,
380 DA850_EVM_UI_EXP_PB7,
381 DA850_EVM_UI_EXP_PB6,
382 DA850_EVM_UI_EXP_PB5,
383 DA850_EVM_UI_EXP_PB4,
384 DA850_EVM_UI_EXP_PB3,
385 DA850_EVM_UI_EXP_PB2,
386 DA850_EVM_UI_EXP_PB1,
387};
388
58b6c5a1 389static const char * const da850_evm_ui_exp[] = {
75929f5e
BG		 390 [DA850_EVM_UI_EXP_SEL_C] = "sel_c",
391 [DA850_EVM_UI_EXP_SEL_B] = "sel_b",
392 [DA850_EVM_UI_EXP_SEL_A] = "sel_a",
393 [DA850_EVM_UI_EXP_PB8] = "pb8",
394 [DA850_EVM_UI_EXP_PB7] = "pb7",
395 [DA850_EVM_UI_EXP_PB6] = "pb6",
396 [DA850_EVM_UI_EXP_PB5] = "pb5",
397 [DA850_EVM_UI_EXP_PB4] = "pb4",
398 [DA850_EVM_UI_EXP_PB3] = "pb3",
399 [DA850_EVM_UI_EXP_PB2] = "pb2",
400 [DA850_EVM_UI_EXP_PB1] = "pb1",
401};
402
403#define DA850_N_UI_PB 8
404
405static struct gpio_keys_button da850_evm_ui_keys[] = {
406 [0 ... DA850_N_UI_PB - 1] = {
407 .type = EV_KEY,
408 .active_low = 1,
409 .wakeup = 0,
410 .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
411 .code = -1, /* assigned at runtime */
412 .gpio = -1, /* assigned at runtime */
413 .desc = NULL, /* assigned at runtime */
414 },
415};
416
417static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
418 .buttons = da850_evm_ui_keys,
419 .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
420 .poll_interval = DA850_GPIO_KEYS_POLL_MS,
421};
422
423static struct platform_device da850_evm_ui_keys_device = {
424 .name = "gpio-keys-polled",
425 .id = 0,
426 .dev = {
427 .platform_data = &da850_evm_ui_keys_pdata
428 },
429};
430
431static void da850_evm_ui_keys_init(unsigned gpio)
432{
433 int i;
434 struct gpio_keys_button *button;
435
436 for (i = 0; i < DA850_N_UI_PB; i++) {
437 button = &da850_evm_ui_keys[i];
438 button->code = KEY_F8 - i;
14f6aeb4 439 button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
75929f5e
BG		 440 button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
441 }
442}
443
1e046d17
MH		 444#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
445static inline void da850_evm_setup_video_port(int video_sel)
446{
447 gpio_set_value_cansleep(video_sel, 0);
448}
449#else
450static inline void da850_evm_setup_video_port(int video_sel) { }
451#endif
452
75e2ea64
C		 453static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
454 unsigned ngpio, void *c)
455{
456 int sel_a, sel_b, sel_c, ret;
457
53c2897d
BG		 458 sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
459 sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
460 sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
75e2ea64 461
53c2897d 462 ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
75e2ea64 463 if (ret) {
6c7c23cc 464 pr_warn("Cannot open UI expander pin %d\n", sel_a);
75e2ea64
C		 465 goto exp_setup_sela_fail;
466 }
467
53c2897d 468 ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
75e2ea64 469 if (ret) {
6c7c23cc 470 pr_warn("Cannot open UI expander pin %d\n", sel_b);
75e2ea64
C		 471 goto exp_setup_selb_fail;
472 }
473
53c2897d 474 ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
75e2ea64 475 if (ret) {
6c7c23cc 476 pr_warn("Cannot open UI expander pin %d\n", sel_c);
75e2ea64
C		 477 goto exp_setup_selc_fail;
478 }
479
480 /* deselect all functionalities */
481 gpio_direction_output(sel_a, 1);
482 gpio_direction_output(sel_b, 1);
483 gpio_direction_output(sel_c, 1);
484
75929f5e
BG		 485 da850_evm_ui_keys_init(gpio);
486 ret = platform_device_register(&da850_evm_ui_keys_device);
487 if (ret) {
6c7c23cc 488 pr_warn("Could not register UI GPIO expander push-buttons");
75929f5e
BG		 489 goto exp_setup_keys_fail;
490 }
491
75e2ea64
C		 492 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
493
494 da850_evm_setup_nor_nand();
495
bae10587 496 da850_evm_setup_emac_rmii(sel_a);
2206771c 497
1e046d17
MH		 498 da850_evm_setup_video_port(sel_c);
499
75e2ea64
C		 500 return 0;
501
75929f5e
BG		 502exp_setup_keys_fail:
503 gpio_free(sel_c);
75e2ea64
C		 504exp_setup_selc_fail:
505 gpio_free(sel_b);
506exp_setup_selb_fail:
507 gpio_free(sel_a);
508exp_setup_sela_fail:
509 return ret;
510}
511
512static int da850_evm_ui_expander_teardown(struct i2c_client *client,
513 unsigned gpio, unsigned ngpio, void *c)
514{
75929f5e
BG		 515 platform_device_unregister(&da850_evm_ui_keys_device);
516
75e2ea64 517 /* deselect all functionalities */
53c2897d
BG		 518 gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
519 gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
520 gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
75e2ea64 521
53c2897d
BG		 522 gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
523 gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
524 gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
75e2ea64
C		 525
526 return 0;
527}
528
70b30939
BG		 529/* assign the baseboard expander's GPIOs after the UI board's */
530#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
531#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
532
533enum da850_evm_bb_exp_pins {
534 DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
535 DA850_EVM_BB_EXP_SW_RST,
536 DA850_EVM_BB_EXP_TP_23,
537 DA850_EVM_BB_EXP_TP_22,
538 DA850_EVM_BB_EXP_TP_21,
539 DA850_EVM_BB_EXP_USER_PB1,
540 DA850_EVM_BB_EXP_USER_LED2,
541 DA850_EVM_BB_EXP_USER_LED1,
542 DA850_EVM_BB_EXP_USER_SW1,
543 DA850_EVM_BB_EXP_USER_SW2,
544 DA850_EVM_BB_EXP_USER_SW3,
545 DA850_EVM_BB_EXP_USER_SW4,
546 DA850_EVM_BB_EXP_USER_SW5,
547 DA850_EVM_BB_EXP_USER_SW6,
548 DA850_EVM_BB_EXP_USER_SW7,
549 DA850_EVM_BB_EXP_USER_SW8
550};
551
58b6c5a1 552static const char * const da850_evm_bb_exp[] = {
70b30939
BG		 553 [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en",
554 [DA850_EVM_BB_EXP_SW_RST] = "sw_rst",
555 [DA850_EVM_BB_EXP_TP_23] = "tp_23",
556 [DA850_EVM_BB_EXP_TP_22] = "tp_22",
557 [DA850_EVM_BB_EXP_TP_21] = "tp_21",
558 [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1",
559 [DA850_EVM_BB_EXP_USER_LED2] = "user_led2",
560 [DA850_EVM_BB_EXP_USER_LED1] = "user_led1",
561 [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1",
562 [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2",
563 [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3",
564 [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4",
565 [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5",
566 [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6",
567 [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7",
568 [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8",
569};
570
571#define DA850_N_BB_USER_SW 8
572
573static struct gpio_keys_button da850_evm_bb_keys[] = {
574 [0] = {
575 .type = EV_KEY,
576 .active_low = 1,
577 .wakeup = 0,
578 .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
579 .code = KEY_PROG1,
580 .desc = NULL, /* assigned at runtime */
581 .gpio = -1, /* assigned at runtime */
582 },
583 [1 ... DA850_N_BB_USER_SW] = {
584 .type = EV_SW,
585 .active_low = 1,
586 .wakeup = 0,
587 .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
588 .code = -1, /* assigned at runtime */
589 .desc = NULL, /* assigned at runtime */
590 .gpio = -1, /* assigned at runtime */
591 },
592};
593
594static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
595 .buttons = da850_evm_bb_keys,
596 .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
597 .poll_interval = DA850_GPIO_KEYS_POLL_MS,
598};
599
600static struct platform_device da850_evm_bb_keys_device = {
601 .name = "gpio-keys-polled",
602 .id = 1,
603 .dev = {
604 .platform_data = &da850_evm_bb_keys_pdata
605 },
606};
607
608static void da850_evm_bb_keys_init(unsigned gpio)
609{
610 int i;
611 struct gpio_keys_button *button;
612
613 button = &da850_evm_bb_keys[0];
14f6aeb4 614 button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
70b30939
BG		 615 button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
616
617 for (i = 0; i < DA850_N_BB_USER_SW; i++) {
618 button = &da850_evm_bb_keys[i + 1];
619 button->code = SW_LID + i;
14f6aeb4 620 button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
70b30939
BG		 621 button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
622 }
623}
624
625#define DA850_N_BB_USER_LED 2
626
627static struct gpio_led da850_evm_bb_leds[] = {
628 [0 ... DA850_N_BB_USER_LED - 1] = {
629 .active_low = 1,
630 .gpio = -1, /* assigned at runtime */
631 .name = NULL, /* assigned at runtime */
632 },
633};
634
635static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
636 .leds = da850_evm_bb_leds,
637 .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
638};
639
640static struct platform_device da850_evm_bb_leds_device = {
641 .name = "leds-gpio",
642 .id = -1,
643 .dev = {
644 .platform_data = &da850_evm_bb_leds_pdata
645 }
646};
647
648static void da850_evm_bb_leds_init(unsigned gpio)
649{
650 int i;
651 struct gpio_led *led;
652
653 for (i = 0; i < DA850_N_BB_USER_LED; i++) {
654 led = &da850_evm_bb_leds[i];
655
656 led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i;
657 led->name =
658 da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i];
659 }
660}
661
662static int da850_evm_bb_expander_setup(struct i2c_client *client,
663 unsigned gpio, unsigned ngpio,
664 void *c)
665{
666 int ret;
667
668 /*
669 * Register the switches and pushbutton on the baseboard as a gpio-keys
670 * device.
671 */
672 da850_evm_bb_keys_init(gpio);
673 ret = platform_device_register(&da850_evm_bb_keys_device);
674 if (ret) {
6c7c23cc 675 pr_warn("Could not register baseboard GPIO expander keys");
70b30939
BG		 676 goto io_exp_setup_sw_fail;
677 }
678
679 da850_evm_bb_leds_init(gpio);
680 ret = platform_device_register(&da850_evm_bb_leds_device);
681 if (ret) {
6c7c23cc 682 pr_warn("Could not register baseboard GPIO expander LEDs");
70b30939
BG		 683 goto io_exp_setup_leds_fail;
684 }
685
686 return 0;
687
688io_exp_setup_leds_fail:
689 platform_device_unregister(&da850_evm_bb_keys_device);
690io_exp_setup_sw_fail:
691 return ret;
692}
693
694static int da850_evm_bb_expander_teardown(struct i2c_client *client,
695 unsigned gpio, unsigned ngpio, void *c)
696{
697 platform_device_unregister(&da850_evm_bb_leds_device);
698 platform_device_unregister(&da850_evm_bb_keys_device);
699
700 return 0;
701}
702
75e2ea64
C		 703static struct pca953x_platform_data da850_evm_ui_expander_info = {
704 .gpio_base = DAVINCI_N_GPIO,
705 .setup = da850_evm_ui_expander_setup,
706 .teardown = da850_evm_ui_expander_teardown,
75929f5e 707 .names = da850_evm_ui_exp,
75e2ea64
C		 708};
709
70b30939
BG		 710static struct pca953x_platform_data da850_evm_bb_expander_info = {
711 .gpio_base = DA850_BB_EXPANDER_GPIO_BASE,
712 .setup = da850_evm_bb_expander_setup,
713 .teardown = da850_evm_bb_expander_teardown,
714 .names = da850_evm_bb_exp,
715};
716
1a7ff8ff
C		 717static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
718 {
719 I2C_BOARD_INFO("tlv320aic3x", 0x18),
75e2ea64
C		 720 },
721 {
722 I2C_BOARD_INFO("tca6416", 0x20),
723 .platform_data = &da850_evm_ui_expander_info,
724 },
70b30939
BG		 725 {
726 I2C_BOARD_INFO("tca6416", 0x21),
727 .platform_data = &da850_evm_bb_expander_info,
728 },
1a7ff8ff
C		 729};
730
0fbc5592
SR		 731static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
732 .bus_freq = 100, /* kHz */
733 .bus_delay = 0, /* usec */
734};
735
491214e1
C		 736/* davinci da850 evm audio machine driver */
737static u8 da850_iis_serializer_direction[] = {
738 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
739 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
740 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
741 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
742};
743
744static struct snd_platform_data da850_evm_snd_data = {
88abfd5b
MP		 745 .tx_dma_offset = 0x2000,
746 .rx_dma_offset = 0x2000,
747 .op_mode = DAVINCI_MCASP_IIS_MODE,
748 .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
749 .tdm_slots = 2,
750 .serial_dir = da850_iis_serializer_direction,
751 .asp_chan_q = EVENTQ_0,
752 .ram_chan_q = EVENTQ_1,
753 .version = MCASP_VERSION_2,
754 .txnumevt = 1,
755 .rxnumevt = 1,
756 .sram_size_playback = SZ_8K,
757 .sram_size_capture = SZ_8K,
491214e1
C		 758};
759
c840fc74
MW		 760static const short da850_evm_mcasp_pins[] __initconst = {
761 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
762 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
763 DA850_AXR_11, DA850_AXR_12,
764 -1
765};
766
67c6b6ff
SN		 767#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
768#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
769
bdf0e836
AH		 770static struct gpiod_lookup_table mmc_gpios_table = {
771 .dev_id = "da830-mmc.0",
772 .table = {
773 /* gpio chip 2 contains gpio range 64-95 */
67c6b6ff
SN		 774 GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
775 GPIO_ACTIVE_LOW),
776 GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
1b6fe979 777 GPIO_ACTIVE_HIGH),
bdf0e836
AH		 778 },
779};
700691f2
SR		 780
781static struct davinci_mmc_config da850_mmc_config = {
700691f2 782 .wires = 4,
0046d0bf
C		 783 .max_freq = 50000000,
784 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
700691f2
SR		 785};
786
5a0d80ea
MW		 787static const short da850_evm_mmcsd0_pins[] __initconst = {
788 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
789 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
790 DA850_GPIO4_0, DA850_GPIO4_1,
791 -1
792};
793
d52f235f
C		 794static void da850_panel_power_ctrl(int val)
795{
796 /* lcd backlight */
797 gpio_set_value(DA850_LCD_BL_PIN, val);
798
799 /* lcd power */
800 gpio_set_value(DA850_LCD_PWR_PIN, val);
801}
802
5cbdf276
SR		 803static int da850_lcd_hw_init(void)
804{
805 int status;
806
d6693b59 807 status = gpio_request(DA850_LCD_BL_PIN, "lcd bl");
5cbdf276
SR		 808 if (status < 0)
809 return status;
810
d6693b59 811 status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr");
5cbdf276
SR		 812 if (status < 0) {
813 gpio_free(DA850_LCD_BL_PIN);
814 return status;
815 }
816
817 gpio_direction_output(DA850_LCD_BL_PIN, 0);
818 gpio_direction_output(DA850_LCD_PWR_PIN, 0);
819
d52f235f
C		 820 /* Switch off panel power and backlight */
821 da850_panel_power_ctrl(0);
5cbdf276 822
d52f235f
C		 823 /* Switch on panel power and backlight */
824 da850_panel_power_ctrl(1);
5cbdf276
SR		 825
826 return 0;
827}
491214e1 828
9e9bc235
PU		 829/* Fixed regulator support */
830static struct regulator_consumer_supply fixed_supplies[] = {
831 /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */
832 REGULATOR_SUPPLY("AVDD", "1-0018"),
833 REGULATOR_SUPPLY("DRVDD", "1-0018"),
834
835 /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */
836 REGULATOR_SUPPLY("DVDD", "1-0018"),
e503eaa3
BG		 837
838 /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */
839 REGULATOR_SUPPLY("vcc", "1-0020"),
9e9bc235
PU		 840};
841
a9eb1f67
SN		 842/* TPS65070 voltage regulator support */
843
844/* 3.3V */
db549d22 845static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
a9eb1f67
SN		 846 {
847 .supply = "usb0_vdda33",
848 },
849 {
850 .supply = "usb1_vdda33",
851 },
852};
853
854/* 3.3V or 1.8V */
db549d22 855static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
a9eb1f67
SN		 856 {
857 .supply = "dvdd3318_a",
858 },
859 {
860 .supply = "dvdd3318_b",
861 },
862 {
863 .supply = "dvdd3318_c",
864 },
9e9bc235 865 REGULATOR_SUPPLY("IOVDD", "1-0018"),
a9eb1f67
SN		 866};
867
868/* 1.2V */
db549d22 869static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
a9eb1f67
SN		 870 {
871 .supply = "cvdd",
872 },
873};
874
875/* 1.8V LDO */
db549d22 876static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
a9eb1f67
SN		 877 {
878 .supply = "sata_vddr",
879 },
880 {
881 .supply = "usb0_vdda18",
882 },
883 {
884 .supply = "usb1_vdda18",
885 },
886 {
887 .supply = "ddr_dvdd18",
888 },
889};
890
891/* 1.2V LDO */
db549d22 892static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
a9eb1f67
SN		 893 {
894 .supply = "sata_vdd",
895 },
896 {
897 .supply = "pll0_vdda",
898 },
899 {
900 .supply = "pll1_vdda",
901 },
902 {
903 .supply = "usbs_cvdd",
904 },
905 {
906 .supply = "vddarnwa1",
907 },
908};
909
8b24599e
SN		 910/* We take advantage of the fact that both defdcdc{2,3} are tied high */
911static struct tps6507x_reg_platform_data tps6507x_platform_data = {
912 .defdcdc_default = true,
913};
914
db549d22 915static struct regulator_init_data tps65070_regulator_data[] = {
a9eb1f67
SN		 916 /* dcdc1 */
917 {
918 .constraints = {
919 .min_uV = 3150000,
920 .max_uV = 3450000,
921 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
922 REGULATOR_CHANGE_STATUS),
923 .boot_on = 1,
924 },
925 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
926 .consumer_supplies = tps65070_dcdc1_consumers,
927 },
928
929 /* dcdc2 */
930 {
931 .constraints = {
932 .min_uV = 1710000,
933 .max_uV = 3450000,
934 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
935 REGULATOR_CHANGE_STATUS),
936 .boot_on = 1,
79436f87 937 .always_on = 1,
a9eb1f67
SN		 938 },
939 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
940 .consumer_supplies = tps65070_dcdc2_consumers,
8b24599e 941 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 942 },
943
944 /* dcdc3 */
945 {
946 .constraints = {
947 .min_uV = 950000,
28bd2c34 948 .max_uV = 1350000,
a9eb1f67
SN		 949 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
950 REGULATOR_CHANGE_STATUS),
951 .boot_on = 1,
952 },
953 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
954 .consumer_supplies = tps65070_dcdc3_consumers,
8b24599e 955 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 956 },
957
958 /* ldo1 */
959 {
960 .constraints = {
961 .min_uV = 1710000,
962 .max_uV = 1890000,
963 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
964 REGULATOR_CHANGE_STATUS),
965 .boot_on = 1,
966 },
967 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
968 .consumer_supplies = tps65070_ldo1_consumers,
969 },
970
971 /* ldo2 */
972 {
973 .constraints = {
974 .min_uV = 1140000,
975 .max_uV = 1320000,
976 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
977 REGULATOR_CHANGE_STATUS),
978 .boot_on = 1,
979 },
980 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
981 .consumer_supplies = tps65070_ldo2_consumers,
982 },
983};
984
da1e3680
TF		 985static struct touchscreen_init_data tps6507x_touchscreen_data = {
986 .poll_period = 30, /* ms between touch samples */
987 .min_pressure = 0x30, /* minimum pressure to trigger touch */
da1e3680
TF		 988 .vendor = 0, /* /sys/class/input/input?/id/vendor */
989 .product = 65070, /* /sys/class/input/input?/id/product */
990 .version = 0x100, /* /sys/class/input/input?/id/version */
991};
992
0bc20bba
TF		 993static struct tps6507x_board tps_board = {
994 .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
da1e3680 995 .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
0bc20bba
TF		 996};
997
3506f277 998static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
a9eb1f67
SN		 999 {
1000 I2C_BOARD_INFO("tps6507x", 0x48),
0bc20bba 1001 .platform_data = &tps_board,
a9eb1f67
SN		 1002 },
1003};
1004
1005static int __init pmic_tps65070_init(void)
1006{
3506f277
BG		 1007 return i2c_register_board_info(1, da850_evm_tps65070_info,
1008 ARRAY_SIZE(da850_evm_tps65070_info));
a9eb1f67
SN		 1009}
1010
7761ef67
SR		 1011static const short da850_evm_lcdc_pins[] = {
1012 DA850_GPIO2_8, DA850_GPIO2_15,
1013 -1
1014};
1015
85b8307f
SS		 1016static const short da850_evm_mii_pins[] = {
1017 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
1018 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
1019 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
1020 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
1021 DA850_MDIO_D,
1022 -1
1023};
1024
1025static const short da850_evm_rmii_pins[] = {
1026 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
1027 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
1028 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
1029 DA850_MDIO_D,
1030 -1
1031};
1032
bae10587 1033static int __init da850_evm_config_emac(void)
2206771c
C		 1034{
1035 void __iomem *cfg_chip3_base;
1036 int ret;
1037 u32 val;
bae10587
SN		 1038 struct davinci_soc_info *soc_info = &davinci_soc_info;
1039 u8 rmii_en = soc_info->emac_pdata->rmii_en;
1040
1041 if (!machine_is_davinci_da850_evm())
1042 return 0;
2206771c 1043
d2de0582 1044 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
2206771c 1045
2206771c 1046 val = __raw_readl(cfg_chip3_base);
17fadd9a
SN		 1047
1048 if (rmii_en) {
2206771c 1049 val |= BIT(8);
85b8307f 1050 ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
17fadd9a
SN		 1051 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
1052 " functional\n");
1053 } else {
2206771c 1054 val &= ~BIT(8);
85b8307f 1055 ret = davinci_cfg_reg_list(da850_evm_mii_pins);
17fadd9a
SN		 1056 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
1057 " functional\n");
1058 }
1059
2206771c 1060 if (ret)
6c7c23cc
RT		 1061 pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n",
1062 __func__, ret);
2206771c 1063
17fadd9a
SN		 1064 /* configure the CFGCHIP3 register for RMII or MII */
1065 __raw_writel(val, cfg_chip3_base);
1066
2206771c
C		 1067 ret = davinci_cfg_reg(DA850_GPIO2_6);
1068 if (ret)
6c7c23cc 1069 pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__);
2206771c
C		 1070
1071 ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
1072 if (ret) {
6c7c23cc 1073 pr_warn("Cannot open GPIO %d\n", DA850_MII_MDIO_CLKEN_PIN);
2206771c
C		 1074 return ret;
1075 }
1076
17fadd9a
SN		 1077 /* Enable/Disable MII MDIO clock */
1078 gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
2206771c 1079
782f2d78 1080 soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
bae10587
SN		 1081
1082 ret = da8xx_register_emac();
1083 if (ret)
6c7c23cc 1084 pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
bae10587 1085
2206771c
C		 1086 return 0;
1087}
bae10587 1088device_initcall(da850_evm_config_emac);
2206771c 1089
a941c503
RS		 1090/*
1091 * The following EDMA channels/slots are not being used by drivers (for
1092 * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
1093 * they are being reserved for codecs on the DSP side.
1094 */
1095static const s16 da850_dma0_rsv_chans[][2] = {
1096 /* (offset, number) */
1097 { 8, 6},
1098 {24, 4},
1099 {30, 2},
1100 {-1, -1}
1101};
1102
1103static const s16 da850_dma0_rsv_slots[][2] = {
1104 /* (offset, number) */
1105 { 8, 6},
1106 {24, 4},
1107 {30, 50},
1108 {-1, -1}
1109};
1110
1111static const s16 da850_dma1_rsv_chans[][2] = {
1112 /* (offset, number) */
1113 { 0, 28},
1114 {30, 2},
1115 {-1, -1}
1116};
1117
1118static const s16 da850_dma1_rsv_slots[][2] = {
1119 /* (offset, number) */
1120 { 0, 28},
1121 {30, 90},
1122 {-1, -1}
1123};
1124
1125static struct edma_rsv_info da850_edma_cc0_rsv = {
1126 .rsv_chans = da850_dma0_rsv_chans,
1127 .rsv_slots = da850_dma0_rsv_slots,
1128};
1129
1130static struct edma_rsv_info da850_edma_cc1_rsv = {
1131 .rsv_chans = da850_dma1_rsv_chans,
1132 .rsv_slots = da850_dma1_rsv_slots,
1133};
1134
1135static struct edma_rsv_info *da850_edma_rsv[2] = {
1136 &da850_edma_cc0_rsv,
1137 &da850_edma_cc1_rsv,
1138};
1139
28bd2c34
SN		 1140#ifdef CONFIG_CPU_FREQ
1141static __init int da850_evm_init_cpufreq(void)
1142{
1143 switch (system_rev & 0xF) {
1144 case 3:
1145 da850_max_speed = 456000;
1146 break;
1147 case 2:
1148 da850_max_speed = 408000;
1149 break;
1150 case 1:
1151 da850_max_speed = 372000;
1152 break;
1153 }
1154
1155 return da850_register_cpufreq("pll0_sysclk3");
1156}
1157#else
1158static __init int da850_evm_init_cpufreq(void) { return 0; }
1159#endif
1160
1e046d17
MH		 1161#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
1162
1163#define TVP5147_CH0 "tvp514x-0"
1164#define TVP5147_CH1 "tvp514x-1"
1165
1166/* VPIF capture configuration */
1167static struct tvp514x_platform_data tvp5146_pdata = {
1168 .clk_polarity = 0,
1169 .hs_polarity = 1,
1170 .vs_polarity = 1,
1171};
1172
1173#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
1174
8b974017 1175static struct vpif_input da850_ch0_inputs[] = {
1e046d17
MH		 1176 {
1177 .input = {
1178 .index = 0,
1179 .name = "Composite",
1180 .type = V4L2_INPUT_TYPE_CAMERA,
7aaad131 1181 .capabilities = V4L2_IN_CAP_STD,
1e046d17
MH		 1182 .std = TVP514X_STD_ALL,
1183 },
7aaad131
HV		 1184 .input_route = INPUT_CVBS_VI2B,
1185 .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
1e046d17
MH		 1186 .subdev_name = TVP5147_CH0,
1187 },
1188};
1189
8b974017 1190static struct vpif_input da850_ch1_inputs[] = {
1e046d17
MH		 1191 {
1192 .input = {
1193 .index = 0,
1194 .name = "S-Video",
1195 .type = V4L2_INPUT_TYPE_CAMERA,
7aaad131 1196 .capabilities = V4L2_IN_CAP_STD,
1e046d17
MH		 1197 .std = TVP514X_STD_ALL,
1198 },
7aaad131
HV		 1199 .input_route = INPUT_SVIDEO_VI2C_VI1C,
1200 .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
1e046d17
MH		 1201 .subdev_name = TVP5147_CH1,
1202 },
1203};
1204
1205static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
1206 {
1207 .name = TVP5147_CH0,
1208 .board_info = {
1209 I2C_BOARD_INFO("tvp5146", 0x5d),
1210 .platform_data = &tvp5146_pdata,
1211 },
1e046d17
MH		 1212 },
1213 {
1214 .name = TVP5147_CH1,
1215 .board_info = {
1216 I2C_BOARD_INFO("tvp5146", 0x5c),
1217 .platform_data = &tvp5146_pdata,
1218 },
1e046d17
MH		 1219 },
1220};
1221
1222static struct vpif_capture_config da850_vpif_capture_config = {
1223 .subdev_info = da850_vpif_capture_sdev_info,
1224 .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
ce932a0b 1225 .i2c_adapter_id = 1,
1e046d17
MH		 1226 .chan_config[0] = {
1227 .inputs = da850_ch0_inputs,
1228 .input_count = ARRAY_SIZE(da850_ch0_inputs),
0d4f35f3
HV		 1229 .vpif_if = {
1230 .if_type = VPIF_IF_BT656,
1231 .hd_pol = 1,
1232 .vd_pol = 1,
1233 .fid_pol = 0,
1234 },
1e046d17
MH		 1235 },
1236 .chan_config[1] = {
1237 .inputs = da850_ch1_inputs,
1238 .input_count = ARRAY_SIZE(da850_ch1_inputs),
0d4f35f3
HV		 1239 .vpif_if = {
1240 .if_type = VPIF_IF_BT656,
1241 .hd_pol = 1,
1242 .vd_pol = 1,
1243 .fid_pol = 0,
1244 },
1e046d17
MH		 1245 },
1246 .card_name = "DA850/OMAP-L138 Video Capture",
1247};
1248
1249/* VPIF display configuration */
3e85a44a
LP		 1250
1251static struct adv7343_platform_data adv7343_pdata = {
1252 .mode_config = {
5e95814f 1253 .dac = { 1, 1, 1 },
3e85a44a
LP		 1254 },
1255 .sd_config = {
5e95814f 1256 .sd_dac_out = { 1 },
3e85a44a
LP		 1257 },
1258};
1259
1e046d17
MH		 1260static struct vpif_subdev_info da850_vpif_subdev[] = {
1261 {
1262 .name = "adv7343",
1263 .board_info = {
1264 I2C_BOARD_INFO("adv7343", 0x2a),
3e85a44a 1265 .platform_data = &adv7343_pdata,
1e046d17
MH		 1266 },
1267 },
1268};
1269
2bd4e58c
LP		 1270static const struct vpif_output da850_ch0_outputs[] = {
1271 {
1272 .output = {
1273 .index = 0,
1274 .name = "Composite",
1275 .type = V4L2_OUTPUT_TYPE_ANALOG,
1276 .capabilities = V4L2_OUT_CAP_STD,
1277 .std = V4L2_STD_ALL,
1278 },
1279 .subdev_name = "adv7343",
1280 .output_route = ADV7343_COMPOSITE_ID,
1281 },
1282 {
1283 .output = {
1284 .index = 1,
1285 .name = "S-Video",
1286 .type = V4L2_OUTPUT_TYPE_ANALOG,
1287 .capabilities = V4L2_OUT_CAP_STD,
1288 .std = V4L2_STD_ALL,
1289 },
1290 .subdev_name = "adv7343",
1291 .output_route = ADV7343_SVIDEO_ID,
1292 },
1e046d17
MH		 1293};
1294
1295static struct vpif_display_config da850_vpif_display_config = {
1296 .subdevinfo = da850_vpif_subdev,
1297 .subdev_count = ARRAY_SIZE(da850_vpif_subdev),
2bd4e58c
LP		 1298 .chan_config[0] = {
1299 .outputs = da850_ch0_outputs,
1300 .output_count = ARRAY_SIZE(da850_ch0_outputs),
1301 },
1e046d17 1302 .card_name = "DA850/OMAP-L138 Video Display",
a16cb91a 1303 .i2c_adapter_id = 1,
1e046d17
MH		 1304};
1305
1306static __init void da850_vpif_init(void)
1307{
1308 int ret;
1309
1310 ret = da850_register_vpif();
1311 if (ret)
1312 pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
1313
1314 ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
1315 if (ret)
1316 pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n",
1317 ret);
1318
1319 ret = da850_register_vpif_capture(&da850_vpif_capture_config);
1320 if (ret)
1321 pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret);
1322
1323 ret = davinci_cfg_reg_list(da850_vpif_display_pins);
1324 if (ret)
1325 pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n",
1326 ret);
1327
1328 ret = da850_register_vpif_display(&da850_vpif_display_config);
1329 if (ret)
1330 pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret);
1331}
1332
1333#else
1334static __init void da850_vpif_init(void) {}
1335#endif
1336
8bb2c481
SN		 1337#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
1338
0fbc5592
SR		 1339static __init void da850_evm_init(void)
1340{
1341 int ret;
1342
b856671e
PA		 1343 ret = da850_register_gpio();
1344 if (ret)
1345 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
1346
9e9bc235
PU		 1347 regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies));
1348
a9eb1f67
SN		 1349 ret = pmic_tps65070_init();
1350 if (ret)
6c7c23cc 1351 pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
a9eb1f67 1352
a941c503 1353 ret = da850_register_edma(da850_edma_rsv);
0fbc5592 1354 if (ret)
6c7c23cc 1355 pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
0fbc5592 1356
3821d10a 1357 ret = davinci_cfg_reg_list(da850_i2c0_pins);
0fbc5592 1358 if (ret)
6c7c23cc 1359 pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret);
0fbc5592
SR		 1360
1361 ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
1362 if (ret)
6c7c23cc 1363 pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret);
0fbc5592 1364
5a4b1315 1365
0fbc5592
SR		 1366 ret = da8xx_register_watchdog();
1367 if (ret)
6c7c23cc
RT		 1368 pr_warn("%s: watchdog registration failed: %d\n",
1369 __func__, ret);
0fbc5592 1370
820c4fe3 1371 if (HAS_MMC) {
5a0d80ea 1372 ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
820c4fe3 1373 if (ret)
6c7c23cc
RT		 1374 pr_warn("%s: MMCSD0 mux setup failed: %d\n",
1375 __func__, ret);
820c4fe3 1376
bdf0e836 1377 gpiod_add_lookup_table(&mmc_gpios_table);
820c4fe3
SR		 1378
1379 ret = da8xx_register_mmcsd0(&da850_mmc_config);
1380 if (ret)
6c7c23cc
RT		 1381 pr_warn("%s: MMCSD0 registration failed: %d\n",
1382 __func__, ret);
820c4fe3 1383 }
700691f2 1384
fcf7157b 1385 davinci_serial_init(da8xx_serial_device);
0fbc5592 1386
1a7ff8ff
C		 1387 i2c_register_board_info(1, da850_evm_i2c_devices,
1388 ARRAY_SIZE(da850_evm_i2c_devices));
1389
0fbc5592
SR		 1390 /*
1391 * shut down uart 0 and 1; they are not used on the board and
1392 * accessing them causes endless "too much work in irq53" messages
1393 * with arago fs
1394 */
1395 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
1396 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
491214e1 1397
c840fc74 1398 ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
491214e1 1399 if (ret)
6c7c23cc 1400 pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret);
491214e1 1401
88abfd5b 1402 da850_evm_snd_data.sram_pool = sram_get_gen_pool();
b8864aa4 1403 da8xx_register_mcasp(0, &da850_evm_snd_data);
5cbdf276 1404
3821d10a 1405 ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
5cbdf276 1406 if (ret)
6c7c23cc 1407 pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret);
5cbdf276 1408
ae41d17a
MP		 1409 ret = da8xx_register_uio_pruss();
1410 if (ret)
1411 pr_warn("da850_evm_init: pruss initialization failed: %d\n",
1412 ret);
1413
7761ef67 1414 /* Handle board specific muxing for LCD here */
3821d10a 1415 ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
7761ef67 1416 if (ret)
6c7c23cc
RT		 1417 pr_warn("%s: EVM specific LCD mux setup failed: %d\n",
1418 __func__, ret);
7761ef67 1419
5cbdf276
SR		 1420 ret = da850_lcd_hw_init();
1421 if (ret)
6c7c23cc 1422 pr_warn("%s: LCD initialization failed: %d\n", __func__, ret);
5cbdf276 1423
d52f235f 1424 sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
b9e6342b 1425 ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
5cbdf276 1426 if (ret)
6c7c23cc 1427 pr_warn("%s: LCDC registration failed: %d\n", __func__, ret);
c51df70b
MG		 1428
1429 ret = da8xx_register_rtc();
1430 if (ret)
6c7c23cc 1431 pr_warn("%s: RTC setup failed: %d\n", __func__, ret);
09dc2d45 1432
28bd2c34 1433 ret = da850_evm_init_cpufreq();
09dc2d45 1434 if (ret)
6c7c23cc 1435 pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret);
5aeb15aa
SN		 1436
1437 ret = da8xx_register_cpuidle();
1438 if (ret)
6c7c23cc 1439 pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
63534443 1440
aa9aa1ec 1441 davinci_pm_init();
1e046d17
MH		 1442 da850_vpif_init();
1443
0273612c
VD		 1444 ret = spi_register_board_info(da850evm_spi_info,
1445 ARRAY_SIZE(da850evm_spi_info));
1446 if (ret)
1447 pr_warn("%s: spi info registration failed: %d\n", __func__,
1448 ret);
1449
1450 ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));
fdce5568 1451 if (ret)
6c7c23cc 1452 pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret);
8bb2c481
SN		 1453
1454 ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
1455 if (ret)
6c7c23cc 1456 pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
810198bc
RS		 1457
1458 da850_evm_setup_mac_addr();
54288134
RT		 1459
1460 ret = da8xx_register_rproc();
1461 if (ret)
1462 pr_warn("%s: dsp/rproc registration failed: %d\n",
1463 __func__, ret);
0fbc5592
SR		 1464}
1465
1466#ifdef CONFIG_SERIAL_8250_CONSOLE
1467static int __init da850_evm_console_init(void)
1468{
1aa5f2a9
MW		 1469 if (!machine_is_davinci_da850_evm())
1470 return 0;
1471
0fbc5592
SR		 1472 return add_preferred_console("ttyS", 2, "115200");
1473}
1474console_initcall(da850_evm_console_init);
1475#endif
1476
0fbc5592
SR		 1477static void __init da850_evm_map_io(void)
1478{
1479 da850_init();
1480}
1481
48ea89ea 1482MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
e7e56014 1483 .atag_offset = 0x100,
0fbc5592 1484 .map_io = da850_evm_map_io,
bd808947 1485 .init_irq = cp_intc_init,
96c08173 1486 .init_time = da850_init_time,
0fbc5592 1487 .init_machine = da850_evm_init,
3aa3e840 1488 .init_late = davinci_init_late,
f68deabf 1489 .dma_zone_size = SZ_128M,
54288134 1490 .reserve = da8xx_rproc_reserve_cma,
0fbc5592 1491MACHINE_END
Linux 6.x block layer and io_uring tree(s)