Merge tag 'trace-fixes-3.9-rc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / arch / arm / mach-davinci / board-da830-evm.c
CommitLineData
8593790d
MG
1/*
2 * TI DA830/OMAP L137 EVM board
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c
6 *
7 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/kernel.h>
8593790d
MG
13#include <linux/init.h>
14#include <linux/console.h>
0e9a3ddc 15#include <linux/interrupt.h>
13e1f044 16#include <linux/gpio.h>
733975a3 17#include <linux/platform_device.h>
8593790d 18#include <linux/i2c.h>
13e1f044 19#include <linux/i2c/pcf857x.h>
8593790d 20#include <linux/i2c/at24.h>
733975a3
DG
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/partitions.h>
16a3c832
SN
23#include <linux/spi/spi.h>
24#include <linux/spi/flash.h>
8593790d
MG
25
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28
8593790d 29#include <mach/cp_intc.h>
32bf078c 30#include <mach/mux.h>
ec2a0833 31#include <linux/platform_data/mtd-davinci.h>
8593790d 32#include <mach/da8xx.h>
ec2a0833
AB
33#include <linux/platform_data/usb-davinci.h>
34#include <linux/platform_data/mtd-davinci-aemif.h>
35#include <linux/platform_data/spi-davinci.h>
8593790d 36
782f2d78 37#define DA830_EVM_PHY_ID ""
0e9a3ddc
SS
38/*
39 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
40 */
41#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15)
42#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4)
43
44static const short da830_evm_usb11_pins[] = {
45 DA830_GPIO1_15, DA830_GPIO2_4,
46 -1
47};
48
49static da8xx_ocic_handler_t da830_evm_usb_ocic_handler;
50
51static int da830_evm_usb_set_power(unsigned port, int on)
52{
53 gpio_set_value(ON_BD_USB_DRV, on);
54 return 0;
55}
56
57static int da830_evm_usb_get_power(unsigned port)
58{
59 return gpio_get_value(ON_BD_USB_DRV);
60}
61
62static int da830_evm_usb_get_oci(unsigned port)
63{
64 return !gpio_get_value(ON_BD_USB_OVC);
65}
66
67static irqreturn_t da830_evm_usb_ocic_irq(int, void *);
68
69static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler)
70{
71 int irq = gpio_to_irq(ON_BD_USB_OVC);
72 int error = 0;
73
74 if (handler != NULL) {
75 da830_evm_usb_ocic_handler = handler;
76
77 error = request_irq(irq, da830_evm_usb_ocic_irq, IRQF_DISABLED |
78 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
79 "OHCI over-current indicator", NULL);
80 if (error)
81 printk(KERN_ERR "%s: could not request IRQ to watch "
82 "over-current indicator changes\n", __func__);
83 } else
84 free_irq(irq, NULL);
85
86 return error;
87}
88
89static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
90 .set_power = da830_evm_usb_set_power,
91 .get_power = da830_evm_usb_get_power,
92 .get_oci = da830_evm_usb_get_oci,
93 .ocic_notify = da830_evm_usb_ocic_notify,
94
95 /* TPS2065 switch @ 5V */
96 .potpgt = (3 + 1) / 2, /* 3 ms max */
97};
98
99static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id)
100{
101 da830_evm_usb_ocic_handler(&da830_evm_usb11_pdata, 1);
102 return IRQ_HANDLED;
103}
104
105static __init void da830_evm_usb_init(void)
106{
107 u32 cfgchip2;
108 int ret;
109
110 /*
111 * Set up USB clock/mode in the CFGCHIP2 register.
112 * FYI: CFGCHIP2 is 0x0000ef00 initially.
113 */
d2de0582 114 cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
0e9a3ddc
SS
115
116 /* USB2.0 PHY reference clock is 24 MHz */
117 cfgchip2 &= ~CFGCHIP2_REFFREQ;
118 cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
119
120 /*
121 * Select internal reference clock for USB 2.0 PHY
122 * and use it as a clock source for USB 1.1 PHY
123 * (this is the default setting anyway).
124 */
125 cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
126 cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX;
127
ca6a272a
SS
128 /*
129 * We have to override VBUS/ID signals when MUSB is configured into the
130 * host-only mode -- ID pin will float if no cable is connected, so the
131 * controller won't be able to drive VBUS thinking that it's a B-device.
132 * Otherwise, we want to use the OTG mode and enable VBUS comparators.
133 */
134 cfgchip2 &= ~CFGCHIP2_OTGMODE;
135#ifdef CONFIG_USB_MUSB_HOST
136 cfgchip2 |= CFGCHIP2_FORCE_HOST;
137#else
138 cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
139#endif
140
d2de0582 141 __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
0e9a3ddc 142
ca6a272a
SS
143 /* USB_REFCLKIN is not used. */
144 ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
145 if (ret)
146 pr_warning("%s: USB 2.0 PinMux setup failed: %d\n",
147 __func__, ret);
148 else {
149 /*
150 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
151 * with the power on to power good time of 3 ms.
152 */
153 ret = da8xx_register_usb20(1000, 3);
154 if (ret)
155 pr_warning("%s: USB 2.0 registration failed: %d\n",
156 __func__, ret);
157 }
158
3821d10a 159 ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
0e9a3ddc
SS
160 if (ret) {
161 pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
162 __func__, ret);
163 return;
164 }
165
166 ret = gpio_request(ON_BD_USB_DRV, "ON_BD_USB_DRV");
167 if (ret) {
168 printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
169 "power control: %d\n", __func__, ret);
170 return;
171 }
172 gpio_direction_output(ON_BD_USB_DRV, 0);
173
174 ret = gpio_request(ON_BD_USB_OVC, "ON_BD_USB_OVC");
175 if (ret) {
176 printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
177 "over-current indicator: %d\n", __func__, ret);
178 return;
179 }
180 gpio_direction_input(ON_BD_USB_OVC);
181
182 ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
183 if (ret)
184 pr_warning("%s: USB 1.1 registration failed: %d\n",
185 __func__, ret);
186}
187
8593790d
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188static struct davinci_uart_config da830_evm_uart_config __initdata = {
189 .enabled_uarts = 0x7,
190};
191
32bf078c
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192static const short da830_evm_mcasp1_pins[] = {
193 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
194 DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
195 DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10,
196 DA830_AXR1_11,
197 -1
198};
199
e33ef5e3
C
200static u8 da830_iis_serializer_direction[] = {
201 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
202 INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE,
203 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
204};
205
206static struct snd_platform_data da830_evm_snd_data = {
207 .tx_dma_offset = 0x2000,
208 .rx_dma_offset = 0x2000,
209 .op_mode = DAVINCI_MCASP_IIS_MODE,
210 .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction),
211 .tdm_slots = 2,
212 .serial_dir = da830_iis_serializer_direction,
48519f0a 213 .asp_chan_q = EVENTQ_0,
e33ef5e3
C
214 .version = MCASP_VERSION_2,
215 .txnumevt = 1,
216 .rxnumevt = 1,
217};
218
2eb30c81
DG
219/*
220 * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS.
221 */
222static const short da830_evm_mmc_sd_pins[] = {
223 DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
224 DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
225 DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
226 DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2,
227 -1
228};
229
230#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
8ccfd3f0 231#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
2eb30c81
DG
232
233static int da830_evm_mmc_get_ro(int index)
234{
235 return gpio_get_value(DA830_MMCSD_WP_PIN);
236}
237
8ccfd3f0
VB
238static int da830_evm_mmc_get_cd(int index)
239{
240 return !gpio_get_value(DA830_MMCSD_CD_PIN);
241}
242
2eb30c81
DG
243static struct davinci_mmc_config da830_evm_mmc_config = {
244 .get_ro = da830_evm_mmc_get_ro,
8ccfd3f0 245 .get_cd = da830_evm_mmc_get_cd,
d154fed7 246 .wires = 8,
0046d0bf
C
247 .max_freq = 50000000,
248 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
2eb30c81
DG
249 .version = MMC_CTLR_VERSION_2,
250};
251
252static inline void da830_evm_init_mmc(void)
253{
254 int ret;
255
3821d10a 256 ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
2eb30c81
DG
257 if (ret) {
258 pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
259 ret);
260 return;
261 }
262
263 ret = gpio_request(DA830_MMCSD_WP_PIN, "MMC WP");
264 if (ret) {
265 pr_warning("da830_evm_init: can not open GPIO %d\n",
266 DA830_MMCSD_WP_PIN);
267 return;
268 }
269 gpio_direction_input(DA830_MMCSD_WP_PIN);
270
8ccfd3f0
VB
271 ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
272 if (ret) {
273 pr_warning("da830_evm_init: can not open GPIO %d\n",
274 DA830_MMCSD_CD_PIN);
275 return;
276 }
277 gpio_direction_input(DA830_MMCSD_CD_PIN);
278
2eb30c81
DG
279 ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
280 if (ret) {
281 pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
282 ret);
283 gpio_free(DA830_MMCSD_WP_PIN);
284 }
285}
286
a0433ac3
SN
287/*
288 * UI board NAND/NOR flashes only use 8-bit data bus.
289 */
290static const short da830_evm_emif25_pins[] = {
291 DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
292 DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
293 DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
294 DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
295 DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
296 DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
297 DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
298 -1
299};
300
b5ebe4e1
SN
301#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
302#define HAS_MMC 1
303#else
304#define HAS_MMC 0
305#endif
306
733975a3
DG
307#ifdef CONFIG_DA830_UI_NAND
308static struct mtd_partition da830_evm_nand_partitions[] = {
309 /* bootloader (U-Boot, etc) in first sector */
310 [0] = {
311 .name = "bootloader",
312 .offset = 0,
313 .size = SZ_128K,
314 .mask_flags = MTD_WRITEABLE, /* force read-only */
315 },
316 /* bootloader params in the next sector */
317 [1] = {
318 .name = "params",
319 .offset = MTDPART_OFS_APPEND,
320 .size = SZ_128K,
321 .mask_flags = MTD_WRITEABLE, /* force read-only */
322 },
323 /* kernel */
324 [2] = {
325 .name = "kernel",
326 .offset = MTDPART_OFS_APPEND,
327 .size = SZ_2M,
328 .mask_flags = 0,
329 },
330 /* file system */
331 [3] = {
332 .name = "filesystem",
333 .offset = MTDPART_OFS_APPEND,
334 .size = MTDPART_SIZ_FULL,
335 .mask_flags = 0,
336 }
337};
338
339/* flash bbt decriptors */
340static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' };
341static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' };
342
343static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = {
344 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
345 NAND_BBT_WRITE | NAND_BBT_2BIT |
346 NAND_BBT_VERSION | NAND_BBT_PERCHIP,
347 .offs = 2,
348 .len = 4,
349 .veroffs = 16,
350 .maxblocks = 4,
351 .pattern = da830_evm_nand_bbt_pattern
352};
353
354static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
355 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
356 NAND_BBT_WRITE | NAND_BBT_2BIT |
357 NAND_BBT_VERSION | NAND_BBT_PERCHIP,
358 .offs = 2,
359 .len = 4,
360 .veroffs = 16,
361 .maxblocks = 4,
362 .pattern = da830_evm_nand_mirror_pattern
363};
364
217f1366
SR
365static struct davinci_aemif_timing da830_evm_nandflash_timing = {
366 .wsetup = 24,
367 .wstrobe = 21,
368 .whold = 14,
369 .rsetup = 19,
370 .rstrobe = 50,
371 .rhold = 0,
372 .ta = 20,
373};
374
733975a3
DG
375static struct davinci_nand_pdata da830_evm_nand_pdata = {
376 .parts = da830_evm_nand_partitions,
377 .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
378 .ecc_mode = NAND_ECC_HW,
379 .ecc_bits = 4,
bb9ebd4e 380 .bbt_options = NAND_BBT_USE_FLASH,
733975a3
DG
381 .bbt_td = &da830_evm_nand_bbt_main_descr,
382 .bbt_md = &da830_evm_nand_bbt_mirror_descr,
217f1366 383 .timing = &da830_evm_nandflash_timing,
733975a3
DG
384};
385
386static struct resource da830_evm_nand_resources[] = {
387 [0] = { /* First memory resource is NAND I/O window */
002cb2d2
SS
388 .start = DA8XX_AEMIF_CS3_BASE,
389 .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
733975a3
DG
390 .flags = IORESOURCE_MEM,
391 },
392 [1] = { /* Second memory resource is AEMIF control registers */
002cb2d2
SS
393 .start = DA8XX_AEMIF_CTL_BASE,
394 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
733975a3
DG
395 .flags = IORESOURCE_MEM,
396 },
397};
398
399static struct platform_device da830_evm_nand_device = {
400 .name = "davinci_nand",
401 .id = 1,
402 .dev = {
403 .platform_data = &da830_evm_nand_pdata,
404 },
405 .num_resources = ARRAY_SIZE(da830_evm_nand_resources),
406 .resource = da830_evm_nand_resources,
407};
a0433ac3 408
77316f05 409static inline void da830_evm_init_nand(int mux_mode)
a0433ac3
SN
410{
411 int ret;
412
b5ebe4e1
SN
413 if (HAS_MMC) {
414 pr_warning("WARNING: both MMC/SD and NAND are "
415 "enabled, but they share AEMIF pins.\n"
416 "\tDisable MMC/SD for NAND support.\n");
417 return;
418 }
419
3821d10a 420 ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
a0433ac3
SN
421 if (ret)
422 pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
423 ret);
424
425 ret = platform_device_register(&da830_evm_nand_device);
426 if (ret)
427 pr_warning("da830_evm_init: NAND device not registered.\n");
77316f05
SN
428
429 gpio_direction_output(mux_mode, 1);
a0433ac3
SN
430}
431#else
77316f05 432static inline void da830_evm_init_nand(int mux_mode) { }
733975a3
DG
433#endif
434
a0433ac3 435#ifdef CONFIG_DA830_UI_LCD
77316f05 436static inline void da830_evm_init_lcdc(int mux_mode)
a0433ac3
SN
437{
438 int ret;
439
3821d10a 440 ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
a0433ac3
SN
441 if (ret)
442 pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
443 ret);
444
445 ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata);
446 if (ret)
447 pr_warning("da830_evm_init: lcd setup failed: %d\n", ret);
77316f05
SN
448
449 gpio_direction_output(mux_mode, 0);
a0433ac3
SN
450}
451#else
77316f05 452static inline void da830_evm_init_lcdc(int mux_mode) { }
a0433ac3 453#endif
733975a3 454
77316f05
SN
455static struct at24_platform_data da830_evm_i2c_eeprom_info = {
456 .byte_len = SZ_256K / 8,
457 .page_size = 64,
458 .flags = AT24_FLAG_ADDR16,
459 .setup = davinci_get_mac_addr,
460 .context = (void *)0x7f00,
461};
462
1ef203c3
SR
463static int __init da830_evm_ui_expander_setup(struct i2c_client *client,
464 int gpio, unsigned ngpio, void *context)
77316f05
SN
465{
466 gpio_request(gpio + 6, "UI MUX_MODE");
467
b5ebe4e1
SN
468 /* Drive mux mode low to match the default without UI card */
469 gpio_direction_output(gpio + 6, 0);
470
77316f05
SN
471 da830_evm_init_lcdc(gpio + 6);
472
473 da830_evm_init_nand(gpio + 6);
474
475 return 0;
476}
477
478static int da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio,
479 unsigned ngpio, void *context)
480{
481 gpio_free(gpio + 6);
482 return 0;
483}
484
1ef203c3 485static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = {
77316f05
SN
486 .gpio_base = DAVINCI_N_GPIO,
487 .setup = da830_evm_ui_expander_setup,
488 .teardown = da830_evm_ui_expander_teardown,
489};
490
491static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
492 {
493 I2C_BOARD_INFO("24c256", 0x50),
494 .platform_data = &da830_evm_i2c_eeprom_info,
495 },
496 {
497 I2C_BOARD_INFO("tlv320aic3x", 0x18),
498 },
499 {
500 I2C_BOARD_INFO("pcf8574", 0x3f),
501 .platform_data = &da830_evm_ui_expander_info,
502 },
503};
504
505static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
506 .bus_freq = 100, /* kHz */
507 .bus_delay = 0, /* usec */
508};
509
a941c503
RS
510/*
511 * The following EDMA channels/slots are not being used by drivers (for
512 * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence
513 * they are being reserved for codecs on the DSP side.
514 */
515static const s16 da830_dma_rsv_chans[][2] = {
516 /* (offset, number) */
517 { 8, 2},
518 {12, 2},
519 {24, 4},
520 {30, 2},
521 {-1, -1}
522};
523
524static const s16 da830_dma_rsv_slots[][2] = {
525 /* (offset, number) */
526 { 8, 2},
527 {12, 2},
528 {24, 4},
529 {30, 26},
530 {-1, -1}
531};
532
533static struct edma_rsv_info da830_edma_rsv[] = {
534 {
535 .rsv_chans = da830_dma_rsv_chans,
536 .rsv_slots = da830_dma_rsv_slots,
537 },
538};
539
16a3c832
SN
540static struct mtd_partition da830evm_spiflash_part[] = {
541 [0] = {
542 .name = "DSP-UBL",
543 .offset = 0,
544 .size = SZ_8K,
545 .mask_flags = MTD_WRITEABLE,
546 },
547 [1] = {
548 .name = "ARM-UBL",
549 .offset = MTDPART_OFS_APPEND,
550 .size = SZ_16K + SZ_8K,
551 .mask_flags = MTD_WRITEABLE,
552 },
553 [2] = {
554 .name = "U-Boot",
555 .offset = MTDPART_OFS_APPEND,
556 .size = SZ_256K - SZ_32K,
557 .mask_flags = MTD_WRITEABLE,
558 },
559 [3] = {
560 .name = "U-Boot-Environment",
561 .offset = MTDPART_OFS_APPEND,
562 .size = SZ_16K,
563 .mask_flags = 0,
564 },
565 [4] = {
566 .name = "Kernel",
567 .offset = MTDPART_OFS_APPEND,
568 .size = MTDPART_SIZ_FULL,
569 .mask_flags = 0,
570 },
571};
572
573static struct flash_platform_data da830evm_spiflash_data = {
574 .name = "m25p80",
575 .parts = da830evm_spiflash_part,
576 .nr_parts = ARRAY_SIZE(da830evm_spiflash_part),
577 .type = "w25x32",
578};
579
580static struct davinci_spi_config da830evm_spiflash_cfg = {
581 .io_type = SPI_IO_TYPE_DMA,
582 .c2tdelay = 8,
583 .t2cdelay = 8,
584};
585
586static struct spi_board_info da830evm_spi_info[] = {
587 {
588 .modalias = "m25p80",
589 .platform_data = &da830evm_spiflash_data,
590 .controller_data = &da830evm_spiflash_cfg,
591 .mode = SPI_MODE_0,
592 .max_speed_hz = 30000000,
593 .bus_num = 0,
594 .chip_select = 0,
595 },
596};
597
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598static __init void da830_evm_init(void)
599{
600 struct davinci_soc_info *soc_info = &davinci_soc_info;
601 int ret;
602
a941c503 603 ret = da830_register_edma(da830_edma_rsv);
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604 if (ret)
605 pr_warning("da830_evm_init: edma registration failed: %d\n",
606 ret);
607
3821d10a 608 ret = davinci_cfg_reg_list(da830_i2c0_pins);
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609 if (ret)
610 pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
611 ret);
612
613 ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata);
614 if (ret)
615 pr_warning("da830_evm_init: i2c0 registration failed: %d\n",
616 ret);
617
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618 da830_evm_usb_init();
619
8593790d 620 soc_info->emac_pdata->rmii_en = 1;
782f2d78 621 soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID;
8593790d 622
3821d10a 623 ret = davinci_cfg_reg_list(da830_cpgmac_pins);
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624 if (ret)
625 pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
626 ret);
627
628 ret = da8xx_register_emac();
629 if (ret)
630 pr_warning("da830_evm_init: emac registration failed: %d\n",
631 ret);
632
633 ret = da8xx_register_watchdog();
634 if (ret)
635 pr_warning("da830_evm_init: watchdog registration failed: %d\n",
636 ret);
637
638 davinci_serial_init(&da830_evm_uart_config);
639 i2c_register_board_info(1, da830_evm_i2c_devices,
640 ARRAY_SIZE(da830_evm_i2c_devices));
e33ef5e3 641
3821d10a 642 ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
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643 if (ret)
644 pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
645 ret);
646
b8864aa4 647 da8xx_register_mcasp(1, &da830_evm_snd_data);
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648
649 da830_evm_init_mmc();
13e1f044 650
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651 ret = da8xx_register_rtc();
652 if (ret)
653 pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
16a3c832 654
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655 ret = spi_register_board_info(da830evm_spi_info,
656 ARRAY_SIZE(da830evm_spi_info));
657 if (ret)
658 pr_warn("%s: spi info registration failed: %d\n", __func__,
659 ret);
660
661 ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
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662 if (ret)
663 pr_warning("da830_evm_init: spi 0 registration failed: %d\n",
664 ret);
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665}
666
667#ifdef CONFIG_SERIAL_8250_CONSOLE
668static int __init da830_evm_console_init(void)
669{
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670 if (!machine_is_davinci_da830_evm())
671 return 0;
672
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673 return add_preferred_console("ttyS", 2, "115200");
674}
675console_initcall(da830_evm_console_init);
676#endif
677
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678static void __init da830_evm_map_io(void)
679{
680 da830_init();
681}
682
48ea89ea 683MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
e7e56014 684 .atag_offset = 0x100,
8593790d 685 .map_io = da830_evm_map_io,
bd808947 686 .init_irq = cp_intc_init,
6bb27d73 687 .init_time = davinci_timer_init,
8593790d 688 .init_machine = da830_evm_init,
3aa3e840 689 .init_late = davinci_init_late,
f68deabf 690 .dma_zone_size = SZ_128M,
c6121ddd 691 .restart = da8xx_restart,
8593790d 692MACHINE_END