[linux-2.6-block.git] / arch / arm / mach-cns3xxx / cns3420vb.c

/*
 * Cavium Networks CNS3420 Validation Board
 *
 * Copyright 2000 Deep Blue Solutions Ltd
 * Copyright 2008 ARM Limited
 * Copyright 2008 Cavium Networks
 *		  Scott Shu
 * Copyright 2010 MontaVista Software, LLC.
 *		  Anton Vorontsov <avorontsov@mvista.com>
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/partitions.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include <mach/pm.h>
#include "core.h"
#include "devices.h"

/*
 * NOR Flash
 */
static struct mtd_partition cns3420_nor_partitions[] = {
	{
		.name		= "uboot",
		.size		= 0x00040000,
		.offset		= 0,
		.mask_flags	= MTD_WRITEABLE,
	}, {
		.name		= "kernel",
		.size		= 0x004C0000,
		.offset		= MTDPART_OFS_APPEND,
	}, {
		.name		= "filesystem",
		.size		= 0x7000000,
		.offset		= MTDPART_OFS_APPEND,
	}, {
		.name		= "filesystem2",
		.size		= 0x0AE0000,
		.offset		= MTDPART_OFS_APPEND,
	}, {
		.name		= "ubootenv",
		.size		= MTDPART_SIZ_FULL,
		.offset		= MTDPART_OFS_APPEND,
	},
};

static struct physmap_flash_data cns3420_nor_pdata = {
	.width = 2,
	.parts = cns3420_nor_partitions,
	.nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
};

static struct resource cns3420_nor_res = {
	.start = CNS3XXX_FLASH_BASE,
	.end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
	.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
};

static struct platform_device cns3420_nor_pdev = {
	.name = "physmap-flash",
	.id = 0,
	.resource = &cns3420_nor_res,
	.num_resources = 1,
	.dev = {
		.platform_data = &cns3420_nor_pdata,
	},
};

/*
 * UART
 */
static void __init cns3420_early_serial_setup(void)
{
#ifdef CONFIG_SERIAL_8250_CONSOLE
	static struct uart_port cns3420_serial_port = {
		.membase        = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
		.mapbase        = CNS3XXX_UART0_BASE,
		.irq            = IRQ_CNS3XXX_UART0,
		.iotype         = UPIO_MEM,
		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
		.regshift       = 2,
		.uartclk        = 24000000,
		.line           = 0,
		.type           = PORT_16550A,
		.fifosize       = 16,
	};

	early_serial_setup(&cns3420_serial_port);
#endif
}

/*
 * USB
 */
static struct resource cns3xxx_usb_ehci_resources[] = {
	[0] = {
		.start = CNS3XXX_USB_BASE,
		.end   = CNS3XXX_USB_BASE + SZ_16M - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_CNS3XXX_USB_EHCI,
		.flags = IORESOURCE_IRQ,
	},
};

static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);

static int csn3xxx_usb_power_on(struct platform_device *pdev)
{
	/*
	 * EHCI and OHCI share the same clock and power,
	 * resetting twice would cause the 1st controller been reset.
	 * Therefore only do power up  at the first up device, and
	 * power down at the last down device.
	 *
	 * Set USB AHB INCR length to 16
	 */
	if (atomic_inc_return(&usb_pwr_ref) == 1) {
		cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
		cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
		cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
		__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
			MISC_CHIP_CONFIG_REG);
	}

	return 0;
}

static void csn3xxx_usb_power_off(struct platform_device *pdev)
{
	/*
	 * EHCI and OHCI share the same clock and power,
	 * resetting twice would cause the 1st controller been reset.
	 * Therefore only do power up  at the first up device, and
	 * power down at the last down device.
	 */
	if (atomic_dec_return(&usb_pwr_ref) == 0)
		cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
}

static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
	.power_on	= csn3xxx_usb_power_on,
	.power_off	= csn3xxx_usb_power_off,
};

static struct platform_device cns3xxx_usb_ehci_device = {
	.name          = "ehci-platform",
	.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
	.resource      = cns3xxx_usb_ehci_resources,
	.dev           = {
		.dma_mask          = &cns3xxx_usb_ehci_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.platform_data     = &cns3xxx_usb_ehci_pdata,
	},
};

static struct resource cns3xxx_usb_ohci_resources[] = {
	[0] = {
		.start = CNS3XXX_USB_OHCI_BASE,
		.end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_CNS3XXX_USB_OHCI,
		.flags = IORESOURCE_IRQ,
	},
};

static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);

static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
	.num_ports	= 1,
	.power_on	= csn3xxx_usb_power_on,
	.power_off	= csn3xxx_usb_power_off,
};

static struct platform_device cns3xxx_usb_ohci_device = {
	.name          = "ohci-platform",
	.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
	.resource      = cns3xxx_usb_ohci_resources,
	.dev           = {
		.dma_mask          = &cns3xxx_usb_ohci_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.platform_data	   = &cns3xxx_usb_ohci_pdata,
	},
};

/*
 * Initialization
 */
static struct platform_device *cns3420_pdevs[] __initdata = {
	&cns3420_nor_pdev,
	&cns3xxx_usb_ehci_device,
	&cns3xxx_usb_ohci_device,
};

static void __init cns3420_init(void)
{
	cns3xxx_l2x0_init();

	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));

	cns3xxx_ahci_init();
	cns3xxx_sdhci_init();

	pm_power_off = cns3xxx_power_off;
}

static struct map_desc cns3420_io_desc[] __initdata = {
	{
		.virtual	= CNS3XXX_UART0_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static void __init cns3420_map_io(void)
{
	cns3xxx_map_io();
	iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));

	cns3420_early_serial_setup();
}

MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
	.atag_offset	= 0x100,
	.map_io		= cns3420_map_io,
	.init_irq	= cns3xxx_init_irq,
	.init_time	= cns3xxx_timer_init,
	.init_machine	= cns3420_init,
	.restart	= cns3xxx_restart,
MACHINE_END
Commit	Line	Data
e94cdef0 AV	1	/*
	2	* Cavium Networks CNS3420 Validation Board
	3	*
	4	* Copyright 2000 Deep Blue Solutions Ltd
	5	* Copyright 2008 ARM Limited
	6	* Copyright 2008 Cavium Networks
	7	* Scott Shu
	8	* Copyright 2010 MontaVista Software, LLC.
	9	* Anton Vorontsov <avorontsov@mvista.com>
	10	*
	11	* This file is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License, Version 2, as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/kernel.h>
	18	#include <linux/compiler.h>
	19	#include <linux/io.h>
cf36797f	20	#include <linux/dma-mapping.h>
e94cdef0 AV	21	#include <linux/serial_core.h>
	22	#include <linux/serial_8250.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/physmap.h>
	26	#include <linux/mtd/partitions.h>
b898f5fa	27	#include <linux/usb/ehci_pdriver.h>
6da00dd7	28	#include <linux/usb/ohci_pdriver.h>
e94cdef0 AV	29	#include <asm/setup.h>
	30	#include <asm/mach-types.h>
	31	#include <asm/mach/arch.h>
	32	#include <asm/mach/map.h>
	33	#include <asm/mach/time.h>
e94cdef0 AV	34	#include <mach/cns3xxx.h>
e94cdef0 AV	35	#include <mach/irqs.h>
b898f5fa	36	#include <mach/pm.h>
e94cdef0	37	#include "core.h"
6279d0ea	38	#include "devices.h"
e94cdef0 AV	39
	40	/*
	41	* NOR Flash
	42	*/
	43	static struct mtd_partition cns3420_nor_partitions[] = {
	44	{
	45	.name = "uboot",
	46	.size = 0x00040000,
	47	.offset = 0,
	48	.mask_flags = MTD_WRITEABLE,
	49	}, {
	50	.name = "kernel",
	51	.size = 0x004C0000,
	52	.offset = MTDPART_OFS_APPEND,
	53	}, {
	54	.name = "filesystem",
	55	.size = 0x7000000,
	56	.offset = MTDPART_OFS_APPEND,
	57	}, {
	58	.name = "filesystem2",
	59	.size = 0x0AE0000,
	60	.offset = MTDPART_OFS_APPEND,
	61	}, {
	62	.name = "ubootenv",
	63	.size = MTDPART_SIZ_FULL,
	64	.offset = MTDPART_OFS_APPEND,
	65	},
	66	};
	67
	68	static struct physmap_flash_data cns3420_nor_pdata = {
	69	.width = 2,
	70	.parts = cns3420_nor_partitions,
	71	.nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
	72	};
	73
	74	static struct resource cns3420_nor_res = {
	75	.start = CNS3XXX_FLASH_BASE,
	76	.end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
	77	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	78	};
	79
	80	static struct platform_device cns3420_nor_pdev = {
	81	.name = "physmap-flash",
	82	.id = 0,
	83	.resource = &cns3420_nor_res,
	84	.num_resources = 1,
	85	.dev = {
	86	.platform_data = &cns3420_nor_pdata,
	87	},
	88	};
	89
	90	/*
	91	* UART
	92	*/
	93	static void __init cns3420_early_serial_setup(void)
	94	{
	95	#ifdef CONFIG_SERIAL_8250_CONSOLE
	96	static struct uart_port cns3420_serial_port = {
	97	.membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
	98	.mapbase = CNS3XXX_UART0_BASE,
	99	.irq = IRQ_CNS3XXX_UART0,
	100	.iotype = UPIO_MEM,
	101	.flags = UPF_BOOT_AUTOCONF \| UPF_FIXED_TYPE,
	102	.regshift = 2,
103	.uartclk = 24000000,
104	.line = 0,
105	.type = PORT_16550A,
106	.fifosize = 16,
107	};
108
109	early_serial_setup(&cns3420_serial_port);
110	#endif
111	}
112
cf36797f ML	113	/*
	114	* USB
	115	*/
	116	static struct resource cns3xxx_usb_ehci_resources[] = {
	117	[0] = {
	118	.start = CNS3XXX_USB_BASE,
	119	.end = CNS3XXX_USB_BASE + SZ_16M - 1,
	120	.flags = IORESOURCE_MEM,
	121	},
	122	[1] = {
	123	.start = IRQ_CNS3XXX_USB_EHCI,
	124	.flags = IORESOURCE_IRQ,
	125	},
	126	};
	127
	128	static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
	129
6da00dd7	130	static int csn3xxx_usb_power_on(struct platform_device *pdev)
b898f5fa FF	131	{
	132	/*
	133	* EHCI and OHCI share the same clock and power,
	134	* resetting twice would cause the 1st controller been reset.
	135	* Therefore only do power up at the first up device, and
	136	* power down at the last down device.
	137	*
	138	* Set USB AHB INCR length to 16
	139	*/
	140	if (atomic_inc_return(&usb_pwr_ref) == 1) {
	141	cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
	142	cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
	143	cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
	144	__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) \| (0X2 << 24)),
	145	MISC_CHIP_CONFIG_REG);
	146	}
	147
	148	return 0;
	149	}
	150
6da00dd7	151	static void csn3xxx_usb_power_off(struct platform_device *pdev)
b898f5fa FF	152	{
	153	/*
	154	* EHCI and OHCI share the same clock and power,
	155	* resetting twice would cause the 1st controller been reset.
	156	* Therefore only do power up at the first up device, and
	157	* power down at the last down device.
	158	*/
	159	if (atomic_dec_return(&usb_pwr_ref) == 0)
	160	cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
	161	}
	162
	163	static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
6da00dd7 FF	164	.power_on = csn3xxx_usb_power_on,
6da00dd7 FF	165	.power_off = csn3xxx_usb_power_off,
b898f5fa FF	166	};
b898f5fa FF	167
cf36797f	168	static struct platform_device cns3xxx_usb_ehci_device = {
b898f5fa	169	.name = "ehci-platform",
cf36797f ML	170	.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
	171	.resource = cns3xxx_usb_ehci_resources,
	172	.dev = {
	173	.dma_mask = &cns3xxx_usb_ehci_dma_mask,
	174	.coherent_dma_mask = DMA_BIT_MASK(32),
b898f5fa	175	.platform_data = &cns3xxx_usb_ehci_pdata,
cf36797f ML	176	},
	177	};
	178
	179	static struct resource cns3xxx_usb_ohci_resources[] = {
	180	[0] = {
	181	.start = CNS3XXX_USB_OHCI_BASE,
	182	.end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
	183	.flags = IORESOURCE_MEM,
	184	},
	185	[1] = {
	186	.start = IRQ_CNS3XXX_USB_OHCI,
	187	.flags = IORESOURCE_IRQ,
	188	},
	189	};
	190
	191	static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
	192
6da00dd7 FF	193	static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
	194	.num_ports = 1,
	195	.power_on = csn3xxx_usb_power_on,
	196	.power_off = csn3xxx_usb_power_off,
	197	};
	198
cf36797f	199	static struct platform_device cns3xxx_usb_ohci_device = {
6da00dd7	200	.name = "ohci-platform",
cf36797f ML	201	.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
	202	.resource = cns3xxx_usb_ohci_resources,
	203	.dev = {
	204	.dma_mask = &cns3xxx_usb_ohci_dma_mask,
	205	.coherent_dma_mask = DMA_BIT_MASK(32),
6da00dd7	206	.platform_data = &cns3xxx_usb_ohci_pdata,
cf36797f ML	207	},
	208	};
	209
e94cdef0 AV	210	/*
	211	* Initialization
	212	*/
	213	static struct platform_device *cns3420_pdevs[] __initdata = {
	214	&cns3420_nor_pdev,
cf36797f ML	215	&cns3xxx_usb_ehci_device,
cf36797f ML	216	&cns3xxx_usb_ohci_device,
e94cdef0 AV	217	};
	218
	219	static void __init cns3420_init(void)
	220	{
93e85d8e AV	221	cns3xxx_l2x0_init();
93e85d8e AV	222
e94cdef0 AV	223	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
e94cdef0 AV	224
23f5cace	225	cns3xxx_ahci_init();
6279d0ea AV	226	cns3xxx_sdhci_init();
6279d0ea AV	227
e94cdef0 AV	228	pm_power_off = cns3xxx_power_off;
	229	}
	230
	231	static struct map_desc cns3420_io_desc[] __initdata = {
	232	{
	233	.virtual = CNS3XXX_UART0_BASE_VIRT,
	234	.pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
	235	.length = SZ_4K,
	236	.type = MT_DEVICE,
	237	},
	238	};
	239
	240	static void __init cns3420_map_io(void)
	241	{
	242	cns3xxx_map_io();
	243	iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
	244
	245	cns3420_early_serial_setup();
	246	}
	247
	248	MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
03e67202	249	.atag_offset = 0x100,
e94cdef0 AV	250	.map_io = cns3420_map_io,
e94cdef0 AV	251	.init_irq = cns3xxx_init_irq,
6bb27d73	252	.init_time = cns3xxx_timer_init,
e94cdef0	253	.init_machine = cns3420_init,
39214705	254	.restart = cns3xxx_restart,
e94cdef0	255	MACHINE_END