[linux-2.6-block.git] / arch / arm / mach-cns3xxx / cns3420vb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Cavium Networks CNS3420 Validation Board
 *
 * Copyright 2000 Deep Blue Solutions Ltd
 * Copyright 2008 ARM Limited
 * Copyright 2008 Cavium Networks
 *		  Scott Shu
 * Copyright 2010 MontaVista Software, LLC.
 *		  Anton Vorontsov <avorontsov@mvista.com>
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/partitions.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
#include "devices.h"

/*
 * NOR Flash
 */
static struct mtd_partition cns3420_nor_partitions[] = {
	{
		.name		= "uboot",
		.size		= 0x00040000,
		.offset		= 0,
		.mask_flags	= MTD_WRITEABLE,
	}, {
		.name		= "kernel",
		.size		= 0x004C0000,
		.offset		= MTDPART_OFS_APPEND,
	}, {
		.name		= "filesystem",
		.size		= 0x7000000,
		.offset		= MTDPART_OFS_APPEND,
	}, {
		.name		= "filesystem2",
		.size		= 0x0AE0000,
		.offset		= MTDPART_OFS_APPEND,
	}, {
		.name		= "ubootenv",
		.size		= MTDPART_SIZ_FULL,
		.offset		= MTDPART_OFS_APPEND,
	},
};

static struct physmap_flash_data cns3420_nor_pdata = {
	.width = 2,
	.parts = cns3420_nor_partitions,
	.nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
};

static struct resource cns3420_nor_res = {
	.start = CNS3XXX_FLASH_BASE,
	.end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
	.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
};

static struct platform_device cns3420_nor_pdev = {
	.name = "physmap-flash",
	.id = 0,
	.resource = &cns3420_nor_res,
	.num_resources = 1,
	.dev = {
		.platform_data = &cns3420_nor_pdata,
	},
};

/*
 * UART
 */
static void __init cns3420_early_serial_setup(void)
{
#ifdef CONFIG_SERIAL_8250_CONSOLE
	static struct uart_port cns3420_serial_port = {
		.membase        = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
		.mapbase        = CNS3XXX_UART0_BASE,
		.irq            = IRQ_CNS3XXX_UART0,
		.iotype         = UPIO_MEM,
		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
		.regshift       = 2,
		.uartclk        = 24000000,
		.line           = 0,
		.type           = PORT_16550A,
		.fifosize       = 16,
	};

	early_serial_setup(&cns3420_serial_port);
#endif
}

/*
 * USB
 */
static struct resource cns3xxx_usb_ehci_resources[] = {
	[0] = {
		.start = CNS3XXX_USB_BASE,
		.end   = CNS3XXX_USB_BASE + SZ_16M - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_CNS3XXX_USB_EHCI,
		.flags = IORESOURCE_IRQ,
	},
};

static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);

static int csn3xxx_usb_power_on(struct platform_device *pdev)
{
	/*
	 * EHCI and OHCI share the same clock and power,
	 * resetting twice would cause the 1st controller been reset.
	 * Therefore only do power up  at the first up device, and
	 * power down at the last down device.
	 *
	 * Set USB AHB INCR length to 16
	 */
	if (atomic_inc_return(&usb_pwr_ref) == 1) {
		cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
		cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
		cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
		__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
			MISC_CHIP_CONFIG_REG);
	}

	return 0;
}

static void csn3xxx_usb_power_off(struct platform_device *pdev)
{
	/*
	 * EHCI and OHCI share the same clock and power,
	 * resetting twice would cause the 1st controller been reset.
	 * Therefore only do power up  at the first up device, and
	 * power down at the last down device.
	 */
	if (atomic_dec_return(&usb_pwr_ref) == 0)
		cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
}

static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
	.power_on	= csn3xxx_usb_power_on,
	.power_off	= csn3xxx_usb_power_off,
};

static struct platform_device cns3xxx_usb_ehci_device = {
	.name          = "ehci-platform",
	.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
	.resource      = cns3xxx_usb_ehci_resources,
	.dev           = {
		.dma_mask          = &cns3xxx_usb_ehci_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.platform_data     = &cns3xxx_usb_ehci_pdata,
	},
};

static struct resource cns3xxx_usb_ohci_resources[] = {
	[0] = {
		.start = CNS3XXX_USB_OHCI_BASE,
		.end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_CNS3XXX_USB_OHCI,
		.flags = IORESOURCE_IRQ,
	},
};

static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);

static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
	.num_ports	= 1,
	.power_on	= csn3xxx_usb_power_on,
	.power_off	= csn3xxx_usb_power_off,
};

static struct platform_device cns3xxx_usb_ohci_device = {
	.name          = "ohci-platform",
	.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
	.resource      = cns3xxx_usb_ohci_resources,
	.dev           = {
		.dma_mask          = &cns3xxx_usb_ohci_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.platform_data	   = &cns3xxx_usb_ohci_pdata,
	},
};

/*
 * Initialization
 */
static struct platform_device *cns3420_pdevs[] __initdata = {
	&cns3420_nor_pdev,
	&cns3xxx_usb_ehci_device,
	&cns3xxx_usb_ohci_device,
};

static void __init cns3420_init(void)
{
	cns3xxx_l2x0_init();

	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));

	cns3xxx_ahci_init();
	cns3xxx_sdhci_init();

	pm_power_off = cns3xxx_power_off;
}

static struct map_desc cns3420_io_desc[] __initdata = {
	{
		.virtual	= CNS3XXX_UART0_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static void __init cns3420_map_io(void)
{
	cns3xxx_map_io();
	iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));

	cns3420_early_serial_setup();
}

MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
	.atag_offset	= 0x100,
	.map_io		= cns3420_map_io,
	.init_irq	= cns3xxx_init_irq,
	.init_time	= cns3xxx_timer_init,
	.init_machine	= cns3420_init,
	.init_late      = cns3xxx_pcie_init_late,
	.restart	= cns3xxx_restart,
MACHINE_END
Commit	Line	Data
25d5bf47	1	// SPDX-License-Identifier: GPL-2.0-only
e94cdef0 AV	2	/*
	3	* Cavium Networks CNS3420 Validation Board
	4	*
	5	* Copyright 2000 Deep Blue Solutions Ltd
	6	* Copyright 2008 ARM Limited
	7	* Copyright 2008 Cavium Networks
	8	* Scott Shu
	9	* Copyright 2010 MontaVista Software, LLC.
	10	* Anton Vorontsov <avorontsov@mvista.com>
e94cdef0 AV	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/kernel.h>
	15	#include <linux/compiler.h>
	16	#include <linux/io.h>
cf36797f	17	#include <linux/dma-mapping.h>
e94cdef0 AV	18	#include <linux/serial_core.h>
	19	#include <linux/serial_8250.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/mtd/mtd.h>
	22	#include <linux/mtd/physmap.h>
	23	#include <linux/mtd/partitions.h>
b898f5fa	24	#include <linux/usb/ehci_pdriver.h>
6da00dd7	25	#include <linux/usb/ohci_pdriver.h>
e94cdef0 AV	26	#include <asm/setup.h>
	27	#include <asm/mach-types.h>
	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/time.h>
3f9fb2a0 AB	31	#include "cns3xxx.h"
3f9fb2a0 AB	32	#include "pm.h"
e94cdef0	33	#include "core.h"
6279d0ea	34	#include "devices.h"
e94cdef0 AV	35
	36	/*
	37	* NOR Flash
	38	*/
	39	static struct mtd_partition cns3420_nor_partitions[] = {
	40	{
	41	.name = "uboot",
	42	.size = 0x00040000,
	43	.offset = 0,
	44	.mask_flags = MTD_WRITEABLE,
	45	}, {
	46	.name = "kernel",
	47	.size = 0x004C0000,
	48	.offset = MTDPART_OFS_APPEND,
	49	}, {
	50	.name = "filesystem",
	51	.size = 0x7000000,
	52	.offset = MTDPART_OFS_APPEND,
	53	}, {
	54	.name = "filesystem2",
	55	.size = 0x0AE0000,
	56	.offset = MTDPART_OFS_APPEND,
	57	}, {
	58	.name = "ubootenv",
	59	.size = MTDPART_SIZ_FULL,
	60	.offset = MTDPART_OFS_APPEND,
	61	},
	62	};
	63
	64	static struct physmap_flash_data cns3420_nor_pdata = {
	65	.width = 2,
	66	.parts = cns3420_nor_partitions,
	67	.nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
	68	};
	69
	70	static struct resource cns3420_nor_res = {
	71	.start = CNS3XXX_FLASH_BASE,
	72	.end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
	73	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	74	};
	75
	76	static struct platform_device cns3420_nor_pdev = {
	77	.name = "physmap-flash",
	78	.id = 0,
	79	.resource = &cns3420_nor_res,
	80	.num_resources = 1,
	81	.dev = {
	82	.platform_data = &cns3420_nor_pdata,
	83	},
	84	};
	85
	86	/*
	87	* UART
	88	*/
	89	static void __init cns3420_early_serial_setup(void)
	90	{
	91	#ifdef CONFIG_SERIAL_8250_CONSOLE
	92	static struct uart_port cns3420_serial_port = {
	93	.membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
	94	.mapbase = CNS3XXX_UART0_BASE,
	95	.irq = IRQ_CNS3XXX_UART0,
	96	.iotype = UPIO_MEM,
	97	.flags = UPF_BOOT_AUTOCONF \| UPF_FIXED_TYPE,
	98	.regshift = 2,
99	.uartclk = 24000000,
100	.line = 0,
101	.type = PORT_16550A,
102	.fifosize = 16,
103	};
104
105	early_serial_setup(&cns3420_serial_port);
106	#endif
107	}
108
cf36797f ML	109	/*
	110	* USB
	111	*/
	112	static struct resource cns3xxx_usb_ehci_resources[] = {
	113	[0] = {
	114	.start = CNS3XXX_USB_BASE,
	115	.end = CNS3XXX_USB_BASE + SZ_16M - 1,
	116	.flags = IORESOURCE_MEM,
	117	},
	118	[1] = {
	119	.start = IRQ_CNS3XXX_USB_EHCI,
	120	.flags = IORESOURCE_IRQ,
	121	},
	122	};
	123
	124	static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
	125
6da00dd7	126	static int csn3xxx_usb_power_on(struct platform_device *pdev)
b898f5fa FF	127	{
	128	/*
	129	* EHCI and OHCI share the same clock and power,
	130	* resetting twice would cause the 1st controller been reset.
	131	* Therefore only do power up at the first up device, and
	132	* power down at the last down device.
	133	*
	134	* Set USB AHB INCR length to 16
	135	*/
	136	if (atomic_inc_return(&usb_pwr_ref) == 1) {
	137	cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
	138	cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
	139	cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
	140	__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) \| (0X2 << 24)),
	141	MISC_CHIP_CONFIG_REG);
	142	}
	143
	144	return 0;
	145	}
	146
6da00dd7	147	static void csn3xxx_usb_power_off(struct platform_device *pdev)
b898f5fa FF	148	{
	149	/*
	150	* EHCI and OHCI share the same clock and power,
	151	* resetting twice would cause the 1st controller been reset.
	152	* Therefore only do power up at the first up device, and
	153	* power down at the last down device.
	154	*/
	155	if (atomic_dec_return(&usb_pwr_ref) == 0)
	156	cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
	157	}
	158
	159	static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
6da00dd7 FF	160	.power_on = csn3xxx_usb_power_on,
6da00dd7 FF	161	.power_off = csn3xxx_usb_power_off,
b898f5fa FF	162	};
b898f5fa FF	163
cf36797f	164	static struct platform_device cns3xxx_usb_ehci_device = {
b898f5fa	165	.name = "ehci-platform",
cf36797f ML	166	.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
	167	.resource = cns3xxx_usb_ehci_resources,
	168	.dev = {
	169	.dma_mask = &cns3xxx_usb_ehci_dma_mask,
	170	.coherent_dma_mask = DMA_BIT_MASK(32),
b898f5fa	171	.platform_data = &cns3xxx_usb_ehci_pdata,
cf36797f ML	172	},
	173	};
	174
	175	static struct resource cns3xxx_usb_ohci_resources[] = {
	176	[0] = {
	177	.start = CNS3XXX_USB_OHCI_BASE,
	178	.end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
	179	.flags = IORESOURCE_MEM,
	180	},
	181	[1] = {
	182	.start = IRQ_CNS3XXX_USB_OHCI,
	183	.flags = IORESOURCE_IRQ,
	184	},
	185	};
	186
	187	static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
	188
6da00dd7 FF	189	static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
	190	.num_ports = 1,
	191	.power_on = csn3xxx_usb_power_on,
	192	.power_off = csn3xxx_usb_power_off,
	193	};
	194
cf36797f	195	static struct platform_device cns3xxx_usb_ohci_device = {
6da00dd7	196	.name = "ohci-platform",
cf36797f ML	197	.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
	198	.resource = cns3xxx_usb_ohci_resources,
	199	.dev = {
	200	.dma_mask = &cns3xxx_usb_ohci_dma_mask,
	201	.coherent_dma_mask = DMA_BIT_MASK(32),
6da00dd7	202	.platform_data = &cns3xxx_usb_ohci_pdata,
cf36797f ML	203	},
	204	};
	205
e94cdef0 AV	206	/*
	207	* Initialization
	208	*/
	209	static struct platform_device *cns3420_pdevs[] __initdata = {
	210	&cns3420_nor_pdev,
cf36797f ML	211	&cns3xxx_usb_ehci_device,
cf36797f ML	212	&cns3xxx_usb_ohci_device,
e94cdef0 AV	213	};
	214
	215	static void __init cns3420_init(void)
	216	{
93e85d8e AV	217	cns3xxx_l2x0_init();
93e85d8e AV	218
e94cdef0 AV	219	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
e94cdef0 AV	220
23f5cace	221	cns3xxx_ahci_init();
6279d0ea AV	222	cns3xxx_sdhci_init();
6279d0ea AV	223
e94cdef0 AV	224	pm_power_off = cns3xxx_power_off;
	225	}
	226
	227	static struct map_desc cns3420_io_desc[] __initdata = {
	228	{
	229	.virtual = CNS3XXX_UART0_BASE_VIRT,
	230	.pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
	231	.length = SZ_4K,
	232	.type = MT_DEVICE,
	233	},
	234	};
	235
	236	static void __init cns3420_map_io(void)
	237	{
	238	cns3xxx_map_io();
	239	iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
	240
	241	cns3420_early_serial_setup();
	242	}
	243
	244	MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
03e67202	245	.atag_offset = 0x100,
e94cdef0 AV	246	.map_io = cns3420_map_io,
e94cdef0 AV	247	.init_irq = cns3xxx_init_irq,
6bb27d73	248	.init_time = cns3xxx_timer_init,
e94cdef0	249	.init_machine = cns3420_init,
0a2e912d	250	.init_late = cns3xxx_pcie_init_late,
39214705	251	.restart = cns3xxx_restart,
e94cdef0	252	MACHINE_END