projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b7462d65 LC |
1 | /* |
| 2 | * | |
| 3 | * Copyright (C) 1999 ARM Limited | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | */ | |
| 19 | #include <linux/init.h> | |
| 20 | #include <linux/stddef.h> | |
| 21 | #include <linux/list.h> | |
| 22 | #include <linux/timer.h> | |
| 23 | #include <linux/version.h> | |
| 24 | #include <linux/io.h> | |
| 25 | ||
| 26 | #include <mach/hardware.h> | |
| 27 | #include <asm/irq.h> | |
| 28 | ||
| 29 | #include <asm/mach/irq.h> | |
| 30 | #include <mach/csp/intcHw_reg.h> | |
| 31 | #include <mach/csp/mm_io.h> | |
| 32 | ||
| 33 | static void bcmring_mask_irq0(unsigned int irq) | |
| 34 | { | |
| 35 | writel(1 << (irq - IRQ_INTC0_START), | |
| 36 | MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR); | |
| 37 | } | |
| 38 | ||
| 39 | static void bcmring_unmask_irq0(unsigned int irq) | |
| 40 | { | |
| 41 | writel(1 << (irq - IRQ_INTC0_START), | |
| 42 | MM_IO_BASE_INTC0 + INTCHW_INTENABLE); | |
| 43 | } | |
| 44 | ||
| 45 | static void bcmring_mask_irq1(unsigned int irq) | |
| 46 | { | |
| 47 | writel(1 << (irq - IRQ_INTC1_START), | |
| 48 | MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR); | |
| 49 | } | |
| 50 | ||
| 51 | static void bcmring_unmask_irq1(unsigned int irq) | |
| 52 | { | |
| 53 | writel(1 << (irq - IRQ_INTC1_START), | |
| 54 | MM_IO_BASE_INTC1 + INTCHW_INTENABLE); | |
| 55 | } | |
| 56 | ||
| 57 | static void bcmring_mask_irq2(unsigned int irq) | |
| 58 | { | |
| 59 | writel(1 << (irq - IRQ_SINTC_START), | |
| 60 | MM_IO_BASE_SINTC + INTCHW_INTENCLEAR); | |
| 61 | } | |
| 62 | ||
| 63 | static void bcmring_unmask_irq2(unsigned int irq) | |
| 64 | { | |
| 65 | writel(1 << (irq - IRQ_SINTC_START), | |
| 66 | MM_IO_BASE_SINTC + INTCHW_INTENABLE); | |
| 67 | } | |
| 68 | ||
| 69 | static struct irq_chip bcmring_irq0_chip = { | |
| 70 | .typename = "ARM-INTC0", | |
| 71 | .ack = bcmring_mask_irq0, | |
| 72 | .mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */ | |
| 73 | .unmask = bcmring_unmask_irq0, /* unmaks an interrupt */ | |
| 74 | }; | |
| 75 | ||
| 76 | static struct irq_chip bcmring_irq1_chip = { | |
| 77 | .typename = "ARM-INTC1", | |
| 78 | .ack = bcmring_mask_irq1, | |
| 79 | .mask = bcmring_mask_irq1, | |
| 80 | .unmask = bcmring_unmask_irq1, | |
| 81 | }; | |
| 82 | ||
| 83 | static struct irq_chip bcmring_irq2_chip = { | |
| 84 | .typename = "ARM-SINTC", | |
| 85 | .ack = bcmring_mask_irq2, | |
| 86 | .mask = bcmring_mask_irq2, | |
| 87 | .unmask = bcmring_unmask_irq2, | |
| 88 | }; | |
| 89 | ||
| 90 | static void vic_init(void __iomem *base, struct irq_chip *chip, | |
| 91 | unsigned int irq_start, unsigned int vic_sources) | |
| 92 | { | |
| 93 | unsigned int i; | |
| 94 | for (i = 0; i < 32; i++) { | |
| 95 | unsigned int irq = irq_start + i; | |
| 96 | set_irq_chip(irq, chip); | |
| 97 | set_irq_chip_data(irq, base); | |
| 98 | ||
| 99 | if (vic_sources & (1 << i)) { | |
| 100 | set_irq_handler(irq, handle_level_irq); | |
| 101 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
| 102 | } | |
| 103 | } | |
| 104 | writel(0, base + INTCHW_INTSELECT); | |
| 105 | writel(0, base + INTCHW_INTENABLE); | |
| 106 | writel(~0, base + INTCHW_INTENCLEAR); | |
| 107 | writel(0, base + INTCHW_IRQSTATUS); | |
| 108 | writel(~0, base + INTCHW_SOFTINTCLEAR); | |
| 109 | } | |
| 110 | ||
| 111 | void __init bcmring_init_irq(void) | |
| 112 | { | |
| 113 | vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip, | |
| 114 | IRQ_INTC0_START, IRQ_INTC0_VALID_MASK); | |
| 115 | vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip, | |
| 116 | IRQ_INTC1_START, IRQ_INTC1_VALID_MASK); | |
| 117 | vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip, | |
| 118 | IRQ_SINTC_START, IRQ_SINTC_VALID_MASK); | |
| 119 | ||
| 120 | /* special cases */ | |
| 121 | if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { | |
| 122 | set_irq_handler(IRQ_GPIO0, handle_simple_irq); | |
| 123 | } | |
| 124 | if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { | |
| 125 | set_irq_handler(IRQ_GPIO1, handle_simple_irq); | |
| 126 | } | |
| 127 | } |