Commit | Line | Data |
---|---|---|
73a59c1c SP |
1 | /* |
2 | * linux/arch/arm/mach-at91rm9200/clock.c | |
3 | * | |
4 | * Copyright (C) 2005 David Brownell | |
5 | * Copyright (C) 2005 Ivan Kokshaysky | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/fs.h> | |
17 | #include <linux/debugfs.h> | |
18 | #include <linux/seq_file.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/clk.h> | |
25 | ||
26 | #include <asm/semaphore.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/mach-types.h> | |
29 | ||
30 | #include <asm/arch/hardware.h> | |
31 | #include <asm/arch/board.h> /* for master clock global */ | |
32 | ||
33 | #include "generic.h" | |
34 | ||
35 | #undef DEBUG | |
36 | ||
37 | /* | |
38 | * There's a lot more which can be done with clocks, including cpufreq | |
39 | * integration, slow clock mode support (for system suspend), letting | |
40 | * PLLB be used at other rates (on boards that don't need USB), etc. | |
41 | */ | |
42 | ||
43 | struct clk { | |
44 | const char *name; | |
45 | unsigned long rate_hz; | |
46 | struct clk *parent; | |
47 | u32 pmc_mask; | |
48 | void (*mode)(struct clk *, int); | |
49 | unsigned id:2; /* PCK0..3, or 32k/main/a/b */ | |
50 | unsigned primary:1; | |
51 | unsigned pll:1; | |
52 | unsigned programmable:1; | |
53 | u16 users; | |
54 | }; | |
55 | ||
56 | static spinlock_t clk_lock; | |
57 | static u32 at91_pllb_usb_init; | |
58 | ||
59 | /* | |
60 | * Four primary clock sources: two crystal oscillators (32K, main), and | |
61 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at | |
62 | * 48 MHz (unless no USB function clocks are needed). The main clock and | |
63 | * both PLLs are turned off to run in "slow clock mode" (system suspend). | |
64 | */ | |
65 | static struct clk clk32k = { | |
66 | .name = "clk32k", | |
67 | .rate_hz = AT91_SLOW_CLOCK, | |
68 | .users = 1, /* always on */ | |
69 | .id = 0, | |
70 | .primary = 1, | |
71 | }; | |
72 | static struct clk main_clk = { | |
73 | .name = "main", | |
74 | .pmc_mask = 1 << 0, /* in PMC_SR */ | |
75 | .users = 1, | |
76 | .id = 1, | |
77 | .primary = 1, | |
78 | }; | |
79 | static struct clk plla = { | |
80 | .name = "plla", | |
81 | .parent = &main_clk, | |
82 | .pmc_mask = 1 << 1, /* in PMC_SR */ | |
83 | .id = 2, | |
84 | .primary = 1, | |
85 | .pll = 1, | |
86 | }; | |
87 | ||
88 | static void pllb_mode(struct clk *clk, int is_on) | |
89 | { | |
90 | u32 value; | |
91 | ||
92 | if (is_on) { | |
93 | is_on = AT91_PMC_LOCKB; | |
94 | value = at91_pllb_usb_init; | |
95 | } else | |
96 | value = 0; | |
97 | ||
98 | at91_sys_write(AT91_CKGR_PLLBR, value); | |
99 | ||
100 | do { | |
101 | cpu_relax(); | |
102 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); | |
103 | } | |
104 | ||
105 | static struct clk pllb = { | |
106 | .name = "pllb", | |
107 | .parent = &main_clk, | |
108 | .pmc_mask = 1 << 2, /* in PMC_SR */ | |
109 | .mode = pllb_mode, | |
110 | .id = 3, | |
111 | .primary = 1, | |
112 | .pll = 1, | |
113 | }; | |
114 | ||
115 | static void pmc_sys_mode(struct clk *clk, int is_on) | |
116 | { | |
117 | if (is_on) | |
118 | at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); | |
119 | else | |
120 | at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); | |
121 | } | |
122 | ||
123 | /* USB function clocks (PLLB must be 48 MHz) */ | |
124 | static struct clk udpck = { | |
125 | .name = "udpck", | |
126 | .parent = &pllb, | |
127 | .pmc_mask = AT91_PMC_UDP, | |
128 | .mode = pmc_sys_mode, | |
129 | }; | |
130 | static struct clk uhpck = { | |
131 | .name = "uhpck", | |
132 | .parent = &pllb, | |
133 | .pmc_mask = AT91_PMC_UHP, | |
134 | .mode = pmc_sys_mode, | |
135 | }; | |
136 | ||
137 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS | |
138 | /* | |
139 | * The four programmable clocks can be parented by any primary clock. | |
140 | * You must configure pin multiplexing to bring these signals out. | |
141 | */ | |
142 | static struct clk pck0 = { | |
143 | .name = "pck0", | |
144 | .pmc_mask = AT91_PMC_PCK0, | |
145 | .mode = pmc_sys_mode, | |
146 | .programmable = 1, | |
147 | .id = 0, | |
148 | }; | |
149 | static struct clk pck1 = { | |
150 | .name = "pck1", | |
151 | .pmc_mask = AT91_PMC_PCK1, | |
152 | .mode = pmc_sys_mode, | |
153 | .programmable = 1, | |
154 | .id = 1, | |
155 | }; | |
156 | static struct clk pck2 = { | |
157 | .name = "pck2", | |
158 | .pmc_mask = AT91_PMC_PCK2, | |
159 | .mode = pmc_sys_mode, | |
160 | .programmable = 1, | |
161 | .id = 2, | |
162 | }; | |
163 | static struct clk pck3 = { | |
164 | .name = "pck3", | |
165 | .pmc_mask = AT91_PMC_PCK3, | |
166 | .mode = pmc_sys_mode, | |
167 | .programmable = 1, | |
168 | .id = 3, | |
169 | }; | |
170 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ | |
171 | ||
172 | ||
173 | /* | |
174 | * The master clock is divided from the CPU clock (by 1-4). It's used for | |
175 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more | |
176 | * (e.g baud rate generation). It's sourced from one of the primary clocks. | |
177 | */ | |
178 | static struct clk mck = { | |
179 | .name = "mck", | |
180 | .pmc_mask = 1 << 3, /* in PMC_SR */ | |
181 | .users = 1, /* (must be) always on */ | |
182 | }; | |
183 | ||
184 | static void pmc_periph_mode(struct clk *clk, int is_on) | |
185 | { | |
186 | if (is_on) | |
187 | at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); | |
188 | else | |
189 | at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); | |
190 | } | |
191 | ||
192 | static struct clk udc_clk = { | |
193 | .name = "udc_clk", | |
194 | .parent = &mck, | |
195 | .pmc_mask = 1 << AT91_ID_UDP, | |
196 | .mode = pmc_periph_mode, | |
197 | }; | |
198 | static struct clk ohci_clk = { | |
199 | .name = "ohci_clk", | |
200 | .parent = &mck, | |
201 | .pmc_mask = 1 << AT91_ID_UHP, | |
202 | .mode = pmc_periph_mode, | |
203 | }; | |
204 | ||
205 | static struct clk *const clock_list[] = { | |
206 | /* four primary clocks -- MUST BE FIRST! */ | |
207 | &clk32k, | |
208 | &main_clk, | |
209 | &plla, | |
210 | &pllb, | |
211 | ||
212 | /* PLLB children (USB) */ | |
213 | &udpck, | |
214 | &uhpck, | |
215 | ||
216 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS | |
217 | /* programmable clocks */ | |
218 | &pck0, | |
219 | &pck1, | |
220 | &pck2, | |
221 | &pck3, | |
222 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ | |
223 | ||
224 | /* MCK and peripherals */ | |
225 | &mck, | |
226 | // usart0..usart3 | |
227 | // mmc | |
228 | &udc_clk, | |
229 | // i2c | |
230 | // spi | |
231 | // ssc0..ssc2 | |
232 | // tc0..tc5 | |
233 | &ohci_clk, | |
234 | // ether | |
235 | }; | |
236 | ||
237 | ||
238 | /* clocks are all static for now; no refcounting necessary */ | |
239 | struct clk *clk_get(struct device *dev, const char *id) | |
240 | { | |
241 | int i; | |
242 | ||
243 | for (i = 0; i < ARRAY_SIZE(clock_list); i++) { | |
244 | if (strcmp(id, clock_list[i]->name) == 0) | |
245 | return clock_list[i]; | |
246 | } | |
247 | ||
248 | return ERR_PTR(-ENOENT); | |
249 | } | |
250 | EXPORT_SYMBOL(clk_get); | |
251 | ||
252 | void clk_put(struct clk *clk) | |
253 | { | |
254 | } | |
255 | EXPORT_SYMBOL(clk_put); | |
256 | ||
257 | static void __clk_enable(struct clk *clk) | |
258 | { | |
259 | if (clk->parent) | |
260 | __clk_enable(clk->parent); | |
261 | if (clk->users++ == 0 && clk->mode) | |
262 | clk->mode(clk, 1); | |
263 | } | |
264 | ||
265 | int clk_enable(struct clk *clk) | |
266 | { | |
267 | unsigned long flags; | |
268 | ||
269 | spin_lock_irqsave(&clk_lock, flags); | |
270 | __clk_enable(clk); | |
271 | spin_unlock_irqrestore(&clk_lock, flags); | |
272 | return 0; | |
273 | } | |
274 | EXPORT_SYMBOL(clk_enable); | |
275 | ||
276 | static void __clk_disable(struct clk *clk) | |
277 | { | |
278 | BUG_ON(clk->users == 0); | |
279 | if (--clk->users == 0 && clk->mode) | |
280 | clk->mode(clk, 0); | |
281 | if (clk->parent) | |
282 | __clk_disable(clk->parent); | |
283 | } | |
284 | ||
285 | void clk_disable(struct clk *clk) | |
286 | { | |
287 | unsigned long flags; | |
288 | ||
289 | spin_lock_irqsave(&clk_lock, flags); | |
290 | __clk_disable(clk); | |
291 | spin_unlock_irqrestore(&clk_lock, flags); | |
292 | } | |
293 | EXPORT_SYMBOL(clk_disable); | |
294 | ||
295 | unsigned long clk_get_rate(struct clk *clk) | |
296 | { | |
297 | unsigned long flags; | |
298 | unsigned long rate; | |
299 | ||
300 | spin_lock_irqsave(&clk_lock, flags); | |
301 | for (;;) { | |
302 | rate = clk->rate_hz; | |
303 | if (rate || !clk->parent) | |
304 | break; | |
305 | clk = clk->parent; | |
306 | } | |
307 | spin_unlock_irqrestore(&clk_lock, flags); | |
308 | return rate; | |
309 | } | |
310 | EXPORT_SYMBOL(clk_get_rate); | |
311 | ||
312 | /*------------------------------------------------------------------------*/ | |
313 | ||
314 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS | |
315 | ||
316 | /* | |
317 | * For now, only the programmable clocks support reparenting (MCK could | |
318 | * do this too, with care) or rate changing (the PLLs could do this too, | |
319 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get | |
320 | * a better rate match; we don't. | |
321 | */ | |
322 | ||
323 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
324 | { | |
325 | unsigned long flags; | |
326 | unsigned prescale; | |
327 | unsigned long actual; | |
328 | ||
329 | if (!clk->programmable) | |
330 | return -EINVAL; | |
331 | spin_lock_irqsave(&clk_lock, flags); | |
332 | ||
333 | actual = clk->parent->rate_hz; | |
334 | for (prescale = 0; prescale < 7; prescale++) { | |
335 | if (actual && actual <= rate) | |
336 | break; | |
337 | actual >>= 1; | |
338 | } | |
339 | ||
340 | spin_unlock_irqrestore(&clk_lock, flags); | |
341 | return (prescale < 7) ? actual : -ENOENT; | |
342 | } | |
343 | EXPORT_SYMBOL(clk_round_rate); | |
344 | ||
345 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
346 | { | |
347 | unsigned long flags; | |
348 | unsigned prescale; | |
349 | unsigned long actual; | |
350 | ||
351 | if (!clk->programmable) | |
352 | return -EINVAL; | |
353 | if (clk->users) | |
354 | return -EBUSY; | |
355 | spin_lock_irqsave(&clk_lock, flags); | |
356 | ||
357 | actual = clk->parent->rate_hz; | |
358 | for (prescale = 0; prescale < 7; prescale++) { | |
359 | if (actual && actual <= rate) { | |
360 | u32 pckr; | |
361 | ||
362 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); | |
363 | pckr &= 0x03; | |
364 | pckr |= prescale << 2; | |
365 | at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); | |
366 | clk->rate_hz = actual; | |
367 | break; | |
368 | } | |
369 | actual >>= 1; | |
370 | } | |
371 | ||
372 | spin_unlock_irqrestore(&clk_lock, flags); | |
373 | return (prescale < 7) ? actual : -ENOENT; | |
374 | } | |
375 | EXPORT_SYMBOL(clk_set_rate); | |
376 | ||
377 | struct clk *clk_get_parent(struct clk *clk) | |
378 | { | |
379 | return clk->parent; | |
380 | } | |
381 | EXPORT_SYMBOL(clk_get_parent); | |
382 | ||
383 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
384 | { | |
385 | unsigned long flags; | |
386 | ||
387 | if (clk->users) | |
388 | return -EBUSY; | |
389 | if (!parent->primary || !clk->programmable) | |
390 | return -EINVAL; | |
391 | spin_lock_irqsave(&clk_lock, flags); | |
392 | ||
393 | clk->rate_hz = parent->rate_hz; | |
394 | clk->parent = parent; | |
395 | at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); | |
396 | ||
397 | spin_unlock_irqrestore(&clk_lock, flags); | |
398 | return 0; | |
399 | } | |
400 | EXPORT_SYMBOL(clk_set_parent); | |
401 | ||
402 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ | |
403 | ||
404 | /*------------------------------------------------------------------------*/ | |
405 | ||
406 | #ifdef CONFIG_DEBUG_FS | |
407 | ||
408 | static int at91_clk_show(struct seq_file *s, void *unused) | |
409 | { | |
410 | u32 scsr, pcsr, sr; | |
411 | unsigned i; | |
412 | ||
413 | seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); | |
414 | seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); | |
415 | ||
416 | seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); | |
417 | seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); | |
418 | seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); | |
419 | seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); | |
420 | ||
421 | seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); | |
422 | for (i = 0; i < 4; i++) | |
423 | seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i))); | |
424 | seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); | |
425 | ||
426 | seq_printf(s, "\n"); | |
427 | ||
428 | for (i = 0; i < ARRAY_SIZE(clock_list); i++) { | |
429 | char *state; | |
430 | struct clk *clk = clock_list[i]; | |
431 | ||
432 | if (clk->mode == pmc_sys_mode) | |
433 | state = (scsr & clk->pmc_mask) ? "on" : "off"; | |
434 | else if (clk->mode == pmc_periph_mode) | |
435 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | |
436 | else if (clk->pmc_mask) | |
437 | state = (sr & clk->pmc_mask) ? "on" : "off"; | |
438 | else if (clk == &clk32k || clk == &main_clk) | |
439 | state = "on"; | |
440 | else | |
441 | state = ""; | |
442 | ||
443 | seq_printf(s, "%-10s users=%d %-3s %9ld Hz %s\n", | |
444 | clk->name, clk->users, state, clk_get_rate(clk), | |
445 | clk->parent ? clk->parent->name : ""); | |
446 | } | |
447 | return 0; | |
448 | } | |
449 | ||
450 | static int at91_clk_open(struct inode *inode, struct file *file) | |
451 | { | |
452 | return single_open(file, at91_clk_show, NULL); | |
453 | } | |
454 | ||
455 | static struct file_operations at91_clk_operations = { | |
456 | .open = at91_clk_open, | |
457 | .read = seq_read, | |
458 | .llseek = seq_lseek, | |
459 | .release = single_release, | |
460 | }; | |
461 | ||
462 | static int __init at91_clk_debugfs_init(void) | |
463 | { | |
464 | /* /sys/kernel/debug/at91_clk */ | |
465 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); | |
466 | ||
467 | return 0; | |
468 | } | |
469 | postcore_initcall(at91_clk_debugfs_init); | |
470 | ||
471 | #endif | |
472 | ||
473 | /*------------------------------------------------------------------------*/ | |
474 | ||
475 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) | |
476 | { | |
477 | unsigned mul, div; | |
478 | ||
479 | div = reg & 0xff; | |
480 | mul = (reg >> 16) & 0x7ff; | |
481 | if (div && mul) { | |
482 | freq /= div; | |
483 | freq *= mul + 1; | |
484 | } else | |
485 | freq = 0; | |
486 | if (pll == &pllb && (reg & (1 << 28))) | |
487 | freq /= 2; | |
488 | return freq; | |
489 | } | |
490 | ||
491 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) | |
492 | { | |
493 | unsigned i, div = 0, mul = 0, diff = 1 << 30; | |
494 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; | |
495 | ||
496 | /* PLL output max 240 MHz (or 180 MHz per errata) */ | |
497 | if (out_freq > 240000000) | |
498 | goto fail; | |
499 | ||
500 | for (i = 1; i < 256; i++) { | |
501 | int diff1; | |
502 | unsigned input, mul1; | |
503 | ||
504 | /* | |
505 | * PLL input between 1MHz and 32MHz per spec, but lower | |
506 | * frequences seem necessary in some cases so allow 100K. | |
507 | */ | |
508 | input = main_freq / i; | |
509 | if (input < 100000) | |
510 | continue; | |
511 | if (input > 32000000) | |
512 | continue; | |
513 | ||
514 | mul1 = out_freq / input; | |
515 | if (mul1 > 2048) | |
516 | continue; | |
517 | if (mul1 < 2) | |
518 | goto fail; | |
519 | ||
520 | diff1 = out_freq - input * mul1; | |
521 | if (diff1 < 0) | |
522 | diff1 = -diff1; | |
523 | if (diff > diff1) { | |
524 | diff = diff1; | |
525 | div = i; | |
526 | mul = mul1; | |
527 | if (diff == 0) | |
528 | break; | |
529 | } | |
530 | } | |
531 | if (i == 256 && diff > (out_freq >> 5)) | |
532 | goto fail; | |
533 | return ret | ((mul - 1) << 16) | div; | |
534 | fail: | |
535 | return 0; | |
536 | } | |
537 | ||
538 | int __init at91_clock_init(unsigned long main_clock) | |
539 | { | |
540 | unsigned tmp, freq, mckr; | |
541 | ||
542 | spin_lock_init(&clk_lock); | |
543 | ||
544 | /* | |
545 | * When the bootloader initialized the main oscillator correctly, | |
546 | * there's no problem using the cycle counter. But if it didn't, | |
547 | * or when using oscillator bypass mode, we must be told the speed | |
548 | * of the main clock. | |
549 | */ | |
550 | if (!main_clock) { | |
551 | do { | |
552 | tmp = at91_sys_read(AT91_CKGR_MCFR); | |
553 | } while (!(tmp & 0x10000)); | |
554 | main_clock = (tmp & 0xffff) * (AT91_SLOW_CLOCK / 16); | |
555 | } | |
556 | main_clk.rate_hz = main_clock; | |
557 | ||
558 | /* report if PLLA is more than mildly overclocked */ | |
559 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); | |
560 | if (plla.rate_hz > 209000000) | |
561 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); | |
562 | ||
563 | /* | |
564 | * USB clock init: choose 48 MHz PLLB value, turn all clocks off, | |
565 | * disable 48MHz clock during usb peripheral suspend. | |
566 | * | |
567 | * REVISIT: assumes MCK doesn't derive from PLLB! | |
568 | */ | |
569 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | 0x10000000; | |
570 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); | |
571 | at91_sys_write(AT91_PMC_PCDR, (1 << AT91_ID_UHP) | (1 << AT91_ID_UDP)); | |
572 | at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP); | |
573 | at91_sys_write(AT91_CKGR_PLLBR, 0); | |
574 | at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP); | |
575 | ||
576 | /* | |
577 | * MCK and CPU derive from one of those primary clocks. | |
578 | * For now, assume this parentage won't change. | |
579 | */ | |
580 | mckr = at91_sys_read(AT91_PMC_MCKR); | |
581 | mck.parent = clock_list[mckr & AT91_PMC_CSS]; | |
582 | mck.parent->users++; | |
583 | freq = mck.parent->rate_hz; | |
584 | freq /= (1 << ((mckr >> 2) & 3)); /* prescale */ | |
585 | mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */ | |
586 | ||
587 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", | |
588 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, | |
589 | (unsigned) main_clock / 1000000, | |
590 | ((unsigned) main_clock % 1000000) / 1000); | |
591 | ||
592 | /* FIXME get rid of master_clock global */ | |
593 | at91_master_clock = mck.rate_hz; | |
594 | ||
595 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS | |
596 | /* establish PCK0..PCK3 parentage */ | |
597 | for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) { | |
598 | struct clk *clk = clock_list[tmp], *parent; | |
599 | u32 pckr; | |
600 | ||
601 | if (!clk->programmable) | |
602 | continue; | |
603 | ||
604 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); | |
605 | parent = clock_list[pckr & 3]; | |
606 | clk->parent = parent; | |
607 | clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3)); | |
608 | } | |
609 | #else | |
610 | /* disable unused clocks */ | |
611 | at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3); | |
612 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ | |
613 | ||
614 | /* FIXME several unused clocks may still be active... provide | |
615 | * a CONFIG option to turn off all unused clocks at some point | |
616 | * before driver init starts. | |
617 | */ | |
618 | ||
619 | return 0; | |
620 | } |