Commit | Line | Data |
---|---|---|
907d6deb | 1 | /* |
9d041268 | 2 | * arch/arm/mach-at91/pm.c |
907d6deb AV |
3 | * AT91 Power Management |
4 | * | |
5 | * Copyright (C) 2005 David Brownell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
2f8163ba | 13 | #include <linux/gpio.h> |
95d9ffbe | 14 | #include <linux/suspend.h> |
907d6deb AV |
15 | #include <linux/sched.h> |
16 | #include <linux/proc_fs.h> | |
d2e46790 | 17 | #include <linux/genalloc.h> |
907d6deb AV |
18 | #include <linux/interrupt.h> |
19 | #include <linux/sysfs.h> | |
20 | #include <linux/module.h> | |
f5598d34 | 21 | #include <linux/of.h> |
d2e46790 | 22 | #include <linux/of_platform.h> |
907d6deb | 23 | #include <linux/platform_device.h> |
fced80c7 | 24 | #include <linux/io.h> |
2edb90ae | 25 | #include <linux/clk/at91_pmc.h> |
907d6deb | 26 | |
907d6deb | 27 | #include <asm/irq.h> |
60063497 | 28 | #include <linux/atomic.h> |
907d6deb AV |
29 | #include <asm/mach/time.h> |
30 | #include <asm/mach/irq.h> | |
907d6deb | 31 | |
a09e64fb | 32 | #include <mach/cpu.h> |
ac11a1d4 | 33 | #include <mach/hardware.h> |
907d6deb AV |
34 | |
35 | #include "generic.h" | |
1ea60cf7 | 36 | #include "pm.h" |
907d6deb | 37 | |
f5598d34 AB |
38 | static struct { |
39 | unsigned long uhp_udp_mask; | |
40 | int memctrl; | |
41 | } at91_pm_data; | |
42 | ||
5ad945ea DL |
43 | static void (*at91_pm_standby)(void); |
44 | ||
907d6deb AV |
45 | static int at91_pm_valid_state(suspend_state_t state) |
46 | { | |
47 | switch (state) { | |
48 | case PM_SUSPEND_ON: | |
49 | case PM_SUSPEND_STANDBY: | |
50 | case PM_SUSPEND_MEM: | |
51 | return 1; | |
52 | ||
53 | default: | |
54 | return 0; | |
55 | } | |
56 | } | |
57 | ||
58 | ||
59 | static suspend_state_t target_state; | |
60 | ||
61 | /* | |
62 | * Called after processes are frozen, but before we shutdown devices. | |
63 | */ | |
c697eece | 64 | static int at91_pm_begin(suspend_state_t state) |
907d6deb AV |
65 | { |
66 | target_state = state; | |
67 | return 0; | |
68 | } | |
69 | ||
70 | /* | |
71 | * Verify that all the clocks are correct before entering | |
72 | * slow-clock mode. | |
73 | */ | |
74 | static int at91_pm_verify_clocks(void) | |
75 | { | |
76 | unsigned long scsr; | |
77 | int i; | |
78 | ||
b5514952 | 79 | scsr = at91_pmc_read(AT91_PMC_SCSR); |
907d6deb AV |
80 | |
81 | /* USB must not be using PLLB */ | |
f5598d34 AB |
82 | if ((scsr & at91_pm_data.uhp_udp_mask) != 0) { |
83 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); | |
84 | return 0; | |
907d6deb AV |
85 | } |
86 | ||
907d6deb AV |
87 | /* PCK0..PCK3 must be disabled, or configured to use clk32k */ |
88 | for (i = 0; i < 4; i++) { | |
89 | u32 css; | |
90 | ||
91 | if ((scsr & (AT91_PMC_PCK0 << i)) == 0) | |
92 | continue; | |
93 | ||
b5514952 | 94 | css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; |
907d6deb | 95 | if (css != AT91_PMC_CSS_SLOW) { |
7f96b1ca | 96 | pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); |
907d6deb AV |
97 | return 0; |
98 | } | |
99 | } | |
907d6deb AV |
100 | |
101 | return 1; | |
102 | } | |
103 | ||
104 | /* | |
105 | * Call this from platform driver suspend() to see how deeply to suspend. | |
106 | * For example, some controllers (like OHCI) need one of the PLL clocks | |
107 | * in order to act as a wakeup source, and those are not available when | |
108 | * going into slow clock mode. | |
109 | * | |
110 | * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have | |
111 | * the very same problem (but not using at91 main_clk), and it'd be better | |
112 | * to add one generic API rather than lots of platform-specific ones. | |
113 | */ | |
114 | int at91_suspend_entering_slow_clock(void) | |
115 | { | |
116 | return (target_state == PM_SUSPEND_MEM); | |
117 | } | |
118 | EXPORT_SYMBOL(at91_suspend_entering_slow_clock); | |
119 | ||
120 | ||
fb7e197b JCPV |
121 | static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0, |
122 | void __iomem *ramc1, int memctrl); | |
907d6deb | 123 | |
f5d0f457 | 124 | #ifdef CONFIG_AT91_SLOW_CLOCK |
fb7e197b JCPV |
125 | extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0, |
126 | void __iomem *ramc1, int memctrl); | |
f5d0f457 AV |
127 | extern u32 at91_slow_clock_sz; |
128 | #endif | |
129 | ||
907d6deb AV |
130 | static int at91_pm_enter(suspend_state_t state) |
131 | { | |
85c4b31e | 132 | at91_pinctrl_gpio_suspend(); |
907d6deb | 133 | |
907d6deb AV |
134 | switch (state) { |
135 | /* | |
136 | * Suspend-to-RAM is like STANDBY plus slow clock mode, so | |
137 | * drivers must suspend more deeply: only the master clock | |
138 | * controller may be using the main oscillator. | |
139 | */ | |
140 | case PM_SUSPEND_MEM: | |
141 | /* | |
142 | * Ensure that clocks are in a valid state. | |
143 | */ | |
144 | if (!at91_pm_verify_clocks()) | |
145 | goto error; | |
146 | ||
147 | /* | |
148 | * Enter slow clock mode by switching over to clk32k and | |
149 | * turning off the main oscillator; reverse on wakeup. | |
150 | */ | |
151 | if (slow_clock) { | |
f5d0f457 AV |
152 | #ifdef CONFIG_AT91_SLOW_CLOCK |
153 | /* copy slow_clock handler to SRAM, and call it */ | |
154 | memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); | |
155 | #endif | |
fb7e197b | 156 | slow_clock(at91_pmc_base, at91_ramc_base[0], |
f5598d34 AB |
157 | at91_ramc_base[1], |
158 | at91_pm_data.memctrl); | |
907d6deb AV |
159 | break; |
160 | } else { | |
f5d0f457 | 161 | pr_info("AT91: PM - no slow clock mode enabled ...\n"); |
907d6deb AV |
162 | /* FALLTHROUGH leaving master clock alone */ |
163 | } | |
164 | ||
165 | /* | |
166 | * STANDBY mode has *all* drivers suspended; ignores irqs not | |
167 | * marked as 'wakeup' event sources; and reduces DRAM power. | |
168 | * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and | |
169 | * nothing fancy done with main or cpu clocks. | |
170 | */ | |
171 | case PM_SUSPEND_STANDBY: | |
172 | /* | |
173 | * NOTE: the Wait-for-Interrupt instruction needs to be | |
f5d0f457 AV |
174 | * in icache so no SDRAM accesses are needed until the |
175 | * wakeup IRQ occurs and self-refresh is terminated. | |
8aeeda82 NF |
176 | * For ARM 926 based chips, this requirement is weaker |
177 | * as at91sam9 can access a RAM in self-refresh mode. | |
907d6deb | 178 | */ |
5ad945ea DL |
179 | if (at91_pm_standby) |
180 | at91_pm_standby(); | |
f5d0f457 | 181 | break; |
907d6deb AV |
182 | |
183 | case PM_SUSPEND_ON: | |
8aeeda82 | 184 | cpu_do_idle(); |
907d6deb AV |
185 | break; |
186 | ||
187 | default: | |
188 | pr_debug("AT91: PM - bogus suspend state %d\n", state); | |
189 | goto error; | |
190 | } | |
191 | ||
907d6deb AV |
192 | error: |
193 | target_state = PM_SUSPEND_ON; | |
07192604 | 194 | |
85c4b31e | 195 | at91_pinctrl_gpio_resume(); |
907d6deb AV |
196 | return 0; |
197 | } | |
198 | ||
c697eece RW |
199 | /* |
200 | * Called right prior to thawing processes. | |
201 | */ | |
202 | static void at91_pm_end(void) | |
203 | { | |
204 | target_state = PM_SUSPEND_ON; | |
205 | } | |
206 | ||
907d6deb | 207 | |
2f55ac07 | 208 | static const struct platform_suspend_ops at91_pm_ops = { |
c697eece RW |
209 | .valid = at91_pm_valid_state, |
210 | .begin = at91_pm_begin, | |
211 | .enter = at91_pm_enter, | |
212 | .end = at91_pm_end, | |
907d6deb AV |
213 | }; |
214 | ||
5ad945ea DL |
215 | static struct platform_device at91_cpuidle_device = { |
216 | .name = "cpuidle-at91", | |
217 | }; | |
218 | ||
219 | void at91_pm_set_standby(void (*at91_standby)(void)) | |
220 | { | |
221 | if (at91_standby) { | |
222 | at91_cpuidle_device.dev.platform_data = at91_standby; | |
223 | at91_pm_standby = at91_standby; | |
224 | } | |
225 | } | |
226 | ||
d2e46790 AB |
227 | #ifdef CONFIG_AT91_SLOW_CLOCK |
228 | static void __init at91_pm_sram_init(void) | |
229 | { | |
230 | struct gen_pool *sram_pool; | |
231 | phys_addr_t sram_pbase; | |
232 | unsigned long sram_base; | |
233 | struct device_node *node; | |
234 | struct platform_device *pdev; | |
235 | ||
236 | node = of_find_compatible_node(NULL, NULL, "mmio-sram"); | |
237 | if (!node) { | |
238 | pr_warn("%s: failed to find sram node!\n", __func__); | |
239 | return; | |
240 | } | |
241 | ||
242 | pdev = of_find_device_by_node(node); | |
243 | if (!pdev) { | |
244 | pr_warn("%s: failed to find sram device!\n", __func__); | |
245 | goto put_node; | |
246 | } | |
247 | ||
248 | sram_pool = dev_get_gen_pool(&pdev->dev); | |
249 | if (!sram_pool) { | |
250 | pr_warn("%s: sram pool unavailable!\n", __func__); | |
251 | goto put_node; | |
252 | } | |
253 | ||
254 | sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz); | |
255 | if (!sram_base) { | |
256 | pr_warn("%s: unable to alloc ocram!\n", __func__); | |
257 | goto put_node; | |
258 | } | |
259 | ||
260 | sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); | |
261 | slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false); | |
262 | ||
263 | put_node: | |
264 | of_node_put(node); | |
265 | } | |
266 | #endif | |
267 | ||
268 | ||
4db0ba22 | 269 | static void __init at91_pm_init(void) |
907d6deb | 270 | { |
f5d0f457 | 271 | #ifdef CONFIG_AT91_SLOW_CLOCK |
d2e46790 | 272 | at91_pm_sram_init(); |
907d6deb AV |
273 | #endif |
274 | ||
f5d0f457 AV |
275 | pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); |
276 | ||
5ad945ea DL |
277 | if (at91_cpuidle_device.dev.platform_data) |
278 | platform_device_register(&at91_cpuidle_device); | |
907d6deb | 279 | |
26398a70 | 280 | suspend_set_ops(&at91_pm_ops); |
4db0ba22 | 281 | } |
907d6deb | 282 | |
4db0ba22 AB |
283 | void __init at91_rm9200_pm_init(void) |
284 | { | |
285 | /* | |
286 | * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. | |
287 | */ | |
288 | at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); | |
289 | ||
290 | at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; | |
291 | at91_pm_data.memctrl = AT91_MEMCTRL_MC; | |
292 | ||
293 | at91_pm_init(); | |
294 | } | |
295 | ||
296 | void __init at91_sam9260_pm_init(void) | |
297 | { | |
298 | at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC; | |
299 | at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; | |
300 | return at91_pm_init(); | |
301 | } | |
302 | ||
303 | void __init at91_sam9g45_pm_init(void) | |
304 | { | |
305 | at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP; | |
306 | at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; | |
307 | return at91_pm_init(); | |
907d6deb | 308 | } |
bf02280e NF |
309 | |
310 | void __init at91_sam9x5_pm_init(void) | |
311 | { | |
312 | at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; | |
313 | at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; | |
314 | return at91_pm_init(); | |
315 | } |