[linux-2.6-block.git] / arch / arm / mach-at91 / pm.c

/*
 * arch/arm/mach-at91/pm.c
 * AT91 Power Management
 *
 * Copyright (C) 2005 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/genalloc.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/suspend.h>

#include <linux/clk/at91_pmc.h>

#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/system_misc.h>

#include "generic.h"
#include "pm.h"

static void __iomem *pmc;

/*
 * FIXME: this is needed to communicate between the pinctrl driver and
 * the PM implementation in the machine. Possibly part of the PM
 * implementation should be moved down into the pinctrl driver and get
 * called as part of the generic suspend/resume path.
 */
#ifdef CONFIG_PINCTRL_AT91
extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void);
#endif

static struct {
	unsigned long uhp_udp_mask;
	int memctrl;
} at91_pm_data;

static void __iomem *at91_ramc_base[2];

static int at91_pm_valid_state(suspend_state_t state)
{
	switch (state) {
		case PM_SUSPEND_ON:
		case PM_SUSPEND_STANDBY:
		case PM_SUSPEND_MEM:
			return 1;

		default:
			return 0;
	}
}


static suspend_state_t target_state;

/*
 * Called after processes are frozen, but before we shutdown devices.
 */
static int at91_pm_begin(suspend_state_t state)
{
	target_state = state;
	return 0;
}

/*
 * Verify that all the clocks are correct before entering
 * slow-clock mode.
 */
static int at91_pm_verify_clocks(void)
{
	unsigned long scsr;
	int i;

	scsr = readl(pmc + AT91_PMC_SCSR);

	/* USB must not be using PLLB */
	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
		pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
		return 0;
	}

	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	for (i = 0; i < 4; i++) {
		u32 css;

		if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
			continue;
		css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
		if (css != AT91_PMC_CSS_SLOW) {
			pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
			return 0;
		}
	}

	return 1;
}

/*
 * Call this from platform driver suspend() to see how deeply to suspend.
 * For example, some controllers (like OHCI) need one of the PLL clocks
 * in order to act as a wakeup source, and those are not available when
 * going into slow clock mode.
 *
 * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
 * the very same problem (but not using at91 main_clk), and it'd be better
 * to add one generic API rather than lots of platform-specific ones.
 */
int at91_suspend_entering_slow_clock(void)
{
	return (target_state == PM_SUSPEND_MEM);
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);

static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
			  void __iomem *ramc1, int memctrl);

extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
			    void __iomem *ramc1, int memctrl);
extern u32 at91_pm_suspend_in_sram_sz;

static void at91_pm_suspend(suspend_state_t state)
{
	unsigned int pm_data = at91_pm_data.memctrl;

	pm_data |= (state == PM_SUSPEND_MEM) ?
				AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;

	flush_cache_all();
	outer_disable();

	at91_suspend_sram_fn(pmc, at91_ramc_base[0],
			     at91_ramc_base[1], pm_data);

	outer_resume();
}

static int at91_pm_enter(suspend_state_t state)
{
#ifdef CONFIG_PINCTRL_AT91
	at91_pinctrl_gpio_suspend();
#endif
	switch (state) {
	/*
	 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
	 * drivers must suspend more deeply, the master clock switches
	 * to the clk32k and turns off the main oscillator
	 */
	case PM_SUSPEND_MEM:
		/*
		 * Ensure that clocks are in a valid state.
		 */
		if (!at91_pm_verify_clocks())
			goto error;

		at91_pm_suspend(state);

		break;

	/*
	 * STANDBY mode has *all* drivers suspended; ignores irqs not
	 * marked as 'wakeup' event sources; and reduces DRAM power.
	 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	 * nothing fancy done with main or cpu clocks.
	 */
	case PM_SUSPEND_STANDBY:
		at91_pm_suspend(state);
		break;

	case PM_SUSPEND_ON:
		cpu_do_idle();
		break;

	default:
		pr_debug("AT91: PM - bogus suspend state %d\n", state);
		goto error;
	}

error:
	target_state = PM_SUSPEND_ON;

#ifdef CONFIG_PINCTRL_AT91
	at91_pinctrl_gpio_resume();
#endif
	return 0;
}

/*
 * Called right prior to thawing processes.
 */
static void at91_pm_end(void)
{
	target_state = PM_SUSPEND_ON;
}


static const struct platform_suspend_ops at91_pm_ops = {
	.valid	= at91_pm_valid_state,
	.begin	= at91_pm_begin,
	.enter	= at91_pm_enter,
	.end	= at91_pm_end,
};

static struct platform_device at91_cpuidle_device = {
	.name = "cpuidle-at91",
};

static void at91_pm_set_standby(void (*at91_standby)(void))
{
	if (at91_standby)
		at91_cpuidle_device.dev.platform_data = at91_standby;
}

/*
 * The AT91RM9200 goes into self-refresh mode with this command, and will
 * terminate self-refresh automatically on the next SDRAM access.
 *
 * Self-refresh mode is exited as soon as a memory access is made, but we don't
 * know for sure when that happens. However, we need to restore the low-power
 * mode if it was enabled before going idle. Restoring low-power mode while
 * still in self-refresh is "not recommended", but seems to work.
 */
static void at91rm9200_standby(void)
{
	u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);

	asm volatile(
		"b    1f\n\t"
		".align    5\n\t"
		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
		"    str    %0, [%1, %2]\n\t"
		"    str    %3, [%1, %4]\n\t"
		"    mcr    p15, 0, %0, c7, c0, 4\n\t"
		"    str    %5, [%1, %2]"
		:
		: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
		  "r" (1), "r" (AT91_MC_SDRAMC_SRR),
		  "r" (lpr));
}

/* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
 */
static void at91_ddr_standby(void)
{
	/* Those two values allow us to delay self-refresh activation
	 * to the maximum. */
	u32 lpr0, lpr1 = 0;
	u32 saved_lpr0, saved_lpr1 = 0;

	if (at91_ramc_base[1]) {
		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	}

	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;

	/* self-refresh mode now */
	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);

	cpu_do_idle();

	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}

static void sama5d3_ddr_standby(void)
{
	u32 lpr0;
	u32 saved_lpr0;

	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;

	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);

	cpu_do_idle();

	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
}

/* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
 */
static void at91sam9_sdram_standby(void)
{
	u32 lpr0, lpr1 = 0;
	u32 saved_lpr0, saved_lpr1 = 0;

	if (at91_ramc_base[1]) {
		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
	}

	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;

	/* self-refresh mode now */
	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);

	cpu_do_idle();

	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
}

static const struct of_device_id const ramc_ids[] __initconst = {
	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
	{ .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby },
	{ /*sentinel*/ }
};

static __init void at91_dt_ramc(void)
{
	struct device_node *np;
	const struct of_device_id *of_id;
	int idx = 0;
	const void *standby = NULL;

	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
		at91_ramc_base[idx] = of_iomap(np, 0);
		if (!at91_ramc_base[idx])
			panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);

		if (!standby)
			standby = of_id->data;

		idx++;
	}

	if (!idx)
		panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));

	if (!standby) {
		pr_warn("ramc no standby function available\n");
		return;
	}

	at91_pm_set_standby(standby);
}

static void at91rm9200_idle(void)
{
	/*
	 * Disable the processor clock.  The processor will be automatically
	 * re-enabled by an interrupt or by a reset.
	 */
	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
}

static void at91sam9_idle(void)
{
	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
	cpu_do_idle();
}

static void __init at91_pm_sram_init(void)
{
	struct gen_pool *sram_pool;
	phys_addr_t sram_pbase;
	unsigned long sram_base;
	struct device_node *node;
	struct platform_device *pdev = NULL;

	for_each_compatible_node(node, NULL, "mmio-sram") {
		pdev = of_find_device_by_node(node);
		if (pdev) {
			of_node_put(node);
			break;
		}
	}

	if (!pdev) {
		pr_warn("%s: failed to find sram device!\n", __func__);
		return;
	}

	sram_pool = gen_pool_get(&pdev->dev, NULL);
	if (!sram_pool) {
		pr_warn("%s: sram pool unavailable!\n", __func__);
		return;
	}

	sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
	if (!sram_base) {
		pr_warn("%s: unable to alloc sram!\n", __func__);
		return;
	}

	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
	at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
					at91_pm_suspend_in_sram_sz, false);
	if (!at91_suspend_sram_fn) {
		pr_warn("SRAM: Could not map\n");
		return;
	}

	/* Copy the pm suspend handler to SRAM */
	at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
			&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
}

static const struct of_device_id atmel_pmc_ids[] __initconst = {
	{ .compatible = "atmel,at91rm9200-pmc"  },
	{ .compatible = "atmel,at91sam9260-pmc" },
	{ .compatible = "atmel,at91sam9g45-pmc" },
	{ .compatible = "atmel,at91sam9n12-pmc" },
	{ .compatible = "atmel,at91sam9x5-pmc" },
	{ .compatible = "atmel,sama5d3-pmc" },
	{ .compatible = "atmel,sama5d2-pmc" },
	{ /* sentinel */ },
};

static void __init at91_pm_init(void (*pm_idle)(void))
{
	struct device_node *pmc_np;

	if (at91_cpuidle_device.dev.platform_data)
		platform_device_register(&at91_cpuidle_device);

	pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
	pmc = of_iomap(pmc_np, 0);
	if (!pmc) {
		pr_err("AT91: PM not supported, PMC not found\n");
		return;
	}

	if (pm_idle)
		arm_pm_idle = pm_idle;

	at91_pm_sram_init();

	if (at91_suspend_sram_fn)
		suspend_set_ops(&at91_pm_ops);
	else
		pr_info("AT91: PM not supported, due to no SRAM allocated\n");
}

void __init at91rm9200_pm_init(void)
{
	at91_dt_ramc();

	/*
	 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	 */
	at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);

	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_MC;

	at91_pm_init(at91rm9200_idle);
}

void __init at91sam9260_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_init(at91sam9_idle);
}

void __init at91sam9g45_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	at91_pm_init(at91sam9_idle);
}

void __init at91sam9x5_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	at91_pm_init(at91sam9_idle);
}

void __init sama5_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	at91_pm_init(NULL);
}
Commit	Line	Data
907d6deb	1	/*
9d041268	2	* arch/arm/mach-at91/pm.c
907d6deb AV	3	* AT91 Power Management
	4	*
	5	* Copyright (C) 2005 David Brownell
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
d2e46790	13	#include <linux/genalloc.h>
9824c447 AB	14	#include <linux/io.h>
9824c447 AB	15	#include <linux/of_address.h>
f5598d34	16	#include <linux/of.h>
d2e46790	17	#include <linux/of_platform.h>
9824c447 AB	18	#include <linux/suspend.h>
9824c447 AB	19
2edb90ae	20	#include <linux/clk/at91_pmc.h>
907d6deb	21
385acc0d	22	#include <asm/cacheflush.h>
9824c447	23	#include <asm/fncpy.h>
fbc7edca	24	#include <asm/system_misc.h>
907d6deb	25
907d6deb	26	#include "generic.h"
1ea60cf7	27	#include "pm.h"
907d6deb	28
5737b73e AB	29	static void __iomem *pmc;
5737b73e AB	30
23b84082 AB	31	/*
	32	* FIXME: this is needed to communicate between the pinctrl driver and
	33	* the PM implementation in the machine. Possibly part of the PM
	34	* implementation should be moved down into the pinctrl driver and get
	35	* called as part of the generic suspend/resume path.
	36	*/
8423536f	37	#ifdef CONFIG_PINCTRL_AT91
23b84082 AB	38	extern void at91_pinctrl_gpio_suspend(void);
23b84082 AB	39	extern void at91_pinctrl_gpio_resume(void);
8423536f	40	#endif
23b84082	41
f5598d34 AB	42	static struct {
	43	unsigned long uhp_udp_mask;
	44	int memctrl;
	45	} at91_pm_data;
	46
6cc7fbdf	47	static void __iomem *at91_ramc_base[2];
5ad945ea	48
907d6deb AV	49	static int at91_pm_valid_state(suspend_state_t state)
	50	{
	51	switch (state) {
	52	case PM_SUSPEND_ON:
	53	case PM_SUSPEND_STANDBY:
	54	case PM_SUSPEND_MEM:
	55	return 1;
	56
	57	default:
	58	return 0;
	59	}
	60	}
	61
	62
	63	static suspend_state_t target_state;
	64
	65	/*
	66	* Called after processes are frozen, but before we shutdown devices.
	67	*/
c697eece	68	static int at91_pm_begin(suspend_state_t state)
907d6deb AV	69	{
	70	target_state = state;
	71	return 0;
	72	}
	73
	74	/*
	75	* Verify that all the clocks are correct before entering
	76	* slow-clock mode.
	77	*/
	78	static int at91_pm_verify_clocks(void)
	79	{
	80	unsigned long scsr;
	81	int i;
	82
5737b73e	83	scsr = readl(pmc + AT91_PMC_SCSR);
907d6deb AV	84
907d6deb AV	85	/* USB must not be using PLLB */
f5598d34 AB	86	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
	87	pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
	88	return 0;
907d6deb AV	89	}
907d6deb AV	90
907d6deb AV	91	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	92	for (i = 0; i < 4; i++) {
	93	u32 css;
	94
	95	if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
	96	continue;
5737b73e	97	css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
907d6deb	98	if (css != AT91_PMC_CSS_SLOW) {
7f96b1ca	99	pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
907d6deb AV	100	return 0;
	101	}
	102	}
907d6deb AV	103
	104	return 1;
	105	}
	106
	107	/*
	108	* Call this from platform driver suspend() to see how deeply to suspend.
	109	* For example, some controllers (like OHCI) need one of the PLL clocks
	110	* in order to act as a wakeup source, and those are not available when
	111	* going into slow clock mode.
	112	*
	113	* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
	114	* the very same problem (but not using at91 main_clk), and it'd be better
	115	* to add one generic API rather than lots of platform-specific ones.
	116	*/
	117	int at91_suspend_entering_slow_clock(void)
	118	{
	119	return (target_state == PM_SUSPEND_MEM);
	120	}
	121	EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
	122
5726a8b9	123	static void (at91_suspend_sram_fn)(void __iomem pmc, void __iomem *ramc0,
fb7e197b	124	void __iomem *ramc1, int memctrl);
907d6deb	125
5726a8b9	126	extern void at91_pm_suspend_in_sram(void __iomem pmc, void __iomem ramc0,
fb7e197b	127	void __iomem *ramc1, int memctrl);
5726a8b9	128	extern u32 at91_pm_suspend_in_sram_sz;
f5d0f457	129
23be4be5 WY	130	static void at91_pm_suspend(suspend_state_t state)
	131	{
	132	unsigned int pm_data = at91_pm_data.memctrl;
	133
	134	pm_data \|= (state == PM_SUSPEND_MEM) ?
	135	AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
	136
385acc0d WY	137	flush_cache_all();
	138	outer_disable();
	139
5737b73e AB	140	at91_suspend_sram_fn(pmc, at91_ramc_base[0],
5737b73e AB	141	at91_ramc_base[1], pm_data);
385acc0d WY	142
385acc0d WY	143	outer_resume();
23be4be5 WY	144	}
23be4be5 WY	145
907d6deb AV	146	static int at91_pm_enter(suspend_state_t state)
907d6deb AV	147	{
8423536f	148	#ifdef CONFIG_PINCTRL_AT91
85c4b31e	149	at91_pinctrl_gpio_suspend();
8423536f	150	#endif
907d6deb	151	switch (state) {
23be4be5 WY	152	/*
	153	* Suspend-to-RAM is like STANDBY plus slow clock mode, so
	154	* drivers must suspend more deeply, the master clock switches
	155	* to the clk32k and turns off the main oscillator
	156	*/
	157	case PM_SUSPEND_MEM:
907d6deb	158	/*
23be4be5	159	* Ensure that clocks are in a valid state.
907d6deb	160	*/
23be4be5 WY	161	if (!at91_pm_verify_clocks())
23be4be5 WY	162	goto error;
907d6deb	163
23be4be5	164	at91_pm_suspend(state);
907d6deb	165
23be4be5	166	break;
907d6deb	167
23be4be5 WY	168	/*
	169	* STANDBY mode has all drivers suspended; ignores irqs not
	170	* marked as 'wakeup' event sources; and reduces DRAM power.
	171	* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	172	* nothing fancy done with main or cpu clocks.
	173	*/
	174	case PM_SUSPEND_STANDBY:
	175	at91_pm_suspend(state);
	176	break;
	177
	178	case PM_SUSPEND_ON:
	179	cpu_do_idle();
	180	break;
	181
	182	default:
	183	pr_debug("AT91: PM - bogus suspend state %d\n", state);
	184	goto error;
907d6deb AV	185	}
907d6deb AV	186
907d6deb AV	187	error:
907d6deb AV	188	target_state = PM_SUSPEND_ON;
07192604	189
8423536f	190	#ifdef CONFIG_PINCTRL_AT91
85c4b31e	191	at91_pinctrl_gpio_resume();
8423536f	192	#endif
907d6deb AV	193	return 0;
	194	}
	195
c697eece RW	196	/*
	197	* Called right prior to thawing processes.
	198	*/
	199	static void at91_pm_end(void)
	200	{
	201	target_state = PM_SUSPEND_ON;
	202	}
	203
907d6deb	204
2f55ac07	205	static const struct platform_suspend_ops at91_pm_ops = {
c697eece RW	206	.valid = at91_pm_valid_state,
	207	.begin = at91_pm_begin,
	208	.enter = at91_pm_enter,
	209	.end = at91_pm_end,
907d6deb AV	210	};
907d6deb AV	211
5ad945ea DL	212	static struct platform_device at91_cpuidle_device = {
	213	.name = "cpuidle-at91",
	214	};
	215
047794e1	216	static void at91_pm_set_standby(void (*at91_standby)(void))
5ad945ea	217	{
e32d995c	218	if (at91_standby)
5ad945ea	219	at91_cpuidle_device.dev.platform_data = at91_standby;
5ad945ea DL	220	}
5ad945ea DL	221
a18d0699 AB	222	/*
	223	* The AT91RM9200 goes into self-refresh mode with this command, and will
	224	* terminate self-refresh automatically on the next SDRAM access.
	225	*
	226	* Self-refresh mode is exited as soon as a memory access is made, but we don't
	227	* know for sure when that happens. However, we need to restore the low-power
	228	* mode if it was enabled before going idle. Restoring low-power mode while
	229	* still in self-refresh is "not recommended", but seems to work.
	230	*/
	231	static void at91rm9200_standby(void)
	232	{
d7d45f25	233	u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
a18d0699 AB	234
	235	asm volatile(
	236	"b 1f\n\t"
	237	".align 5\n\t"
	238	"1: mcr p15, 0, %0, c7, c10, 4\n\t"
	239	" str %0, [%1, %2]\n\t"
	240	" str %3, [%1, %4]\n\t"
	241	" mcr p15, 0, %0, c7, c0, 4\n\t"
	242	" str %5, [%1, %2]"
	243	:
d7d45f25 AB	244	: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
d7d45f25 AB	245	"r" (1), "r" (AT91_MC_SDRAMC_SRR),
a18d0699 AB	246	"r" (lpr));
	247	}
	248
	249	/* We manage both DDRAM/SDRAM controllers, we need more than one value to
	250	* remember.
	251	*/
	252	static void at91_ddr_standby(void)
	253	{
	254	/* Those two values allow us to delay self-refresh activation
	255	* to the maximum. */
	256	u32 lpr0, lpr1 = 0;
	257	u32 saved_lpr0, saved_lpr1 = 0;
	258
	259	if (at91_ramc_base[1]) {
	260	saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
	261	lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
	262	lpr1 \|= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	263	}
	264
	265	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	266	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	267	lpr0 \|= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	268
	269	/* self-refresh mode now */
	270	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
	271	if (at91_ramc_base[1])
	272	at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
	273
	274	cpu_do_idle();
	275
	276	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
	277	if (at91_ramc_base[1])
	278	at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
	279	}
	280
60b89f19 NF	281	static void sama5d3_ddr_standby(void)
	282	{
	283	u32 lpr0;
	284	u32 saved_lpr0;
	285
	286	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	287	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	288	lpr0 \|= AT91_DDRSDRC_LPCB_POWER_DOWN;
	289
	290	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
	291
	292	cpu_do_idle();
	293
	294	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
	295	}
	296
a18d0699 AB	297	/* We manage both DDRAM/SDRAM controllers, we need more than one value to
	298	* remember.
	299	*/
	300	static void at91sam9_sdram_standby(void)
	301	{
	302	u32 lpr0, lpr1 = 0;
	303	u32 saved_lpr0, saved_lpr1 = 0;
	304
	305	if (at91_ramc_base[1]) {
	306	saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
	307	lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
	308	lpr1 \|= AT91_SDRAMC_LPCB_SELF_REFRESH;
	309	}
	310
	311	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
	312	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
	313	lpr0 \|= AT91_SDRAMC_LPCB_SELF_REFRESH;
	314
	315	/* self-refresh mode now */
	316	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
	317	if (at91_ramc_base[1])
	318	at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
	319
	320	cpu_do_idle();
	321
	322	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
	323	if (at91_ramc_base[1])
	324	at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
	325	}
	326
19c233b7	327	static const struct of_device_id const ramc_ids[] __initconst = {
827de1f1 AB	328	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	329	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	330	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
60b89f19	331	{ .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby },
827de1f1 AB	332	{ /sentinel/ }
	333	};
	334
444d2d33	335	static __init void at91_dt_ramc(void)
827de1f1 AB	336	{
	337	struct device_node *np;
	338	const struct of_device_id *of_id;
	339	int idx = 0;
	340	const void *standby = NULL;
	341
	342	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
	343	at91_ramc_base[idx] = of_iomap(np, 0);
	344	if (!at91_ramc_base[idx])
	345	panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
	346
	347	if (!standby)
	348	standby = of_id->data;
	349
	350	idx++;
	351	}
	352
	353	if (!idx)
	354	panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
	355
	356	if (!standby) {
	357	pr_warn("ramc no standby function available\n");
	358	return;
	359	}
	360
	361	at91_pm_set_standby(standby);
	362	}
	363
ab6778ee	364	static void at91rm9200_idle(void)
fbc7edca AB	365	{
	366	/*
	367	* Disable the processor clock. The processor will be automatically
	368	* re-enabled by an interrupt or by a reset.
	369	*/
	370	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
	371	}
	372
ab6778ee	373	static void at91sam9_idle(void)
fbc7edca AB	374	{
	375	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
	376	cpu_do_idle();
	377	}
	378
d2e46790 AB	379	static void __init at91_pm_sram_init(void)
	380	{
	381	struct gen_pool *sram_pool;
	382	phys_addr_t sram_pbase;
	383	unsigned long sram_base;
	384	struct device_node *node;
4a031f7d	385	struct platform_device *pdev = NULL;
d2e46790	386
4a031f7d AB	387	for_each_compatible_node(node, NULL, "mmio-sram") {
	388	pdev = of_find_device_by_node(node);
	389	if (pdev) {
	390	of_node_put(node);
	391	break;
	392	}
d2e46790 AB	393	}
d2e46790 AB	394
d2e46790 AB	395	if (!pdev) {
d2e46790 AB	396	pr_warn("%s: failed to find sram device!\n", __func__);
4a031f7d	397	return;
d2e46790 AB	398	}
d2e46790 AB	399
73858173	400	sram_pool = gen_pool_get(&pdev->dev, NULL);
d2e46790 AB	401	if (!sram_pool) {
d2e46790 AB	402	pr_warn("%s: sram pool unavailable!\n", __func__);
4a031f7d	403	return;
d2e46790 AB	404	}
d2e46790 AB	405
5726a8b9	406	sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
d2e46790	407	if (!sram_base) {
5726a8b9	408	pr_warn("%s: unable to alloc sram!\n", __func__);
4a031f7d	409	return;
d2e46790 AB	410	}
	411
	412	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
5726a8b9 WY	413	at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
	414	at91_pm_suspend_in_sram_sz, false);
	415	if (!at91_suspend_sram_fn) {
d94e688c WY	416	pr_warn("SRAM: Could not map\n");
	417	return;
	418	}
	419
5726a8b9 WY	420	/* Copy the pm suspend handler to SRAM */
	421	at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
	422	&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
d2e46790	423	}
d2e46790	424
5737b73e AB	425	static const struct of_device_id atmel_pmc_ids[] __initconst = {
	426	{ .compatible = "atmel,at91rm9200-pmc" },
	427	{ .compatible = "atmel,at91sam9260-pmc" },
	428	{ .compatible = "atmel,at91sam9g45-pmc" },
	429	{ .compatible = "atmel,at91sam9n12-pmc" },
	430	{ .compatible = "atmel,at91sam9x5-pmc" },
	431	{ .compatible = "atmel,sama5d3-pmc" },
	432	{ .compatible = "atmel,sama5d2-pmc" },
	433	{ /* sentinel */ },
	434	};
	435
fbc7edca	436	static void __init at91_pm_init(void (*pm_idle)(void))
907d6deb	437	{
5737b73e	438	struct device_node *pmc_np;
f5d0f457	439
5ad945ea DL	440	if (at91_cpuidle_device.dev.platform_data)
5ad945ea DL	441	platform_device_register(&at91_cpuidle_device);
907d6deb	442
5737b73e AB	443	pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
	444	pmc = of_iomap(pmc_np, 0);
	445	if (!pmc) {
	446	pr_err("AT91: PM not supported, PMC not found\n");
	447	return;
	448	}
	449
fbc7edca AB	450	if (pm_idle)
	451	arm_pm_idle = pm_idle;
	452
5737b73e AB	453	at91_pm_sram_init();
5737b73e AB	454
5726a8b9	455	if (at91_suspend_sram_fn)
d94e688c WY	456	suspend_set_ops(&at91_pm_ops);
	457	else
	458	pr_info("AT91: PM not supported, due to no SRAM allocated\n");
4db0ba22	459	}
907d6deb	460
ad3fc3e3	461	void __init at91rm9200_pm_init(void)
4db0ba22	462	{
827de1f1 AB	463	at91_dt_ramc();
827de1f1 AB	464
4db0ba22 AB	465	/*
	466	* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	467	*/
d7d45f25	468	at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
4db0ba22 AB	469
	470	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP \| AT91RM9200_PMC_UDP;
	471	at91_pm_data.memctrl = AT91_MEMCTRL_MC;
	472
fbc7edca	473	at91_pm_init(at91rm9200_idle);
4db0ba22 AB	474	}
4db0ba22 AB	475
ad3fc3e3	476	void __init at91sam9260_pm_init(void)
4db0ba22	477	{
827de1f1	478	at91_dt_ramc();
4db0ba22 AB	479	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
4db0ba22 AB	480	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
fbc7edca	481	at91_pm_init(at91sam9_idle);
4db0ba22 AB	482	}
4db0ba22 AB	483
ad3fc3e3	484	void __init at91sam9g45_pm_init(void)
4db0ba22	485	{
827de1f1	486	at91_dt_ramc();
4db0ba22 AB	487	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
4db0ba22 AB	488	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
fbc7edca	489	at91_pm_init(at91sam9_idle);
907d6deb	490	}
bf02280e	491
ad3fc3e3	492	void __init at91sam9x5_pm_init(void)
bf02280e	493	{
827de1f1	494	at91_dt_ramc();
bf02280e NF	495	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
bf02280e NF	496	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
fbc7edca AB	497	at91_pm_init(at91sam9_idle);
	498	}
	499
	500	void __init sama5_pm_init(void)
	501	{
	502	at91_dt_ramc();
	503	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
	504	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	505	at91_pm_init(NULL);
bf02280e	506	}