Commit | Line | Data |
---|---|---|
907d6deb | 1 | /* |
9d041268 | 2 | * arch/arm/mach-at91/pm.c |
907d6deb AV |
3 | * AT91 Power Management |
4 | * | |
5 | * Copyright (C) 2005 David Brownell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
d2e46790 | 13 | #include <linux/genalloc.h> |
9824c447 AB |
14 | #include <linux/io.h> |
15 | #include <linux/of_address.h> | |
f5598d34 | 16 | #include <linux/of.h> |
d2e46790 | 17 | #include <linux/of_platform.h> |
7693e18e | 18 | #include <linux/parser.h> |
9824c447 AB |
19 | #include <linux/suspend.h> |
20 | ||
2edb90ae | 21 | #include <linux/clk/at91_pmc.h> |
907d6deb | 22 | |
385acc0d | 23 | #include <asm/cacheflush.h> |
9824c447 | 24 | #include <asm/fncpy.h> |
fbc7edca | 25 | #include <asm/system_misc.h> |
24a0f5c5 | 26 | #include <asm/suspend.h> |
907d6deb | 27 | |
907d6deb | 28 | #include "generic.h" |
1ea60cf7 | 29 | #include "pm.h" |
907d6deb | 30 | |
23b84082 AB |
31 | /* |
32 | * FIXME: this is needed to communicate between the pinctrl driver and | |
33 | * the PM implementation in the machine. Possibly part of the PM | |
34 | * implementation should be moved down into the pinctrl driver and get | |
35 | * called as part of the generic suspend/resume path. | |
36 | */ | |
8423536f | 37 | #ifdef CONFIG_PINCTRL_AT91 |
23b84082 AB |
38 | extern void at91_pinctrl_gpio_suspend(void); |
39 | extern void at91_pinctrl_gpio_resume(void); | |
8423536f | 40 | #endif |
23b84082 | 41 | |
7693e18e | 42 | static const match_table_t pm_modes __initconst = { |
514e2a29 CB |
43 | { AT91_PM_STANDBY, "standby" }, |
44 | { AT91_PM_ULP0, "ulp0" }, | |
5b56c182 | 45 | { AT91_PM_ULP1, "ulp1" }, |
7693e18e AB |
46 | { AT91_PM_BACKUP, "backup" }, |
47 | { -1, NULL }, | |
48 | }; | |
49 | ||
50 | static struct at91_pm_data pm_data = { | |
514e2a29 CB |
51 | .standby_mode = AT91_PM_STANDBY, |
52 | .suspend_mode = AT91_PM_ULP0, | |
7693e18e | 53 | }; |
f5598d34 | 54 | |
4d767bc3 | 55 | #define at91_ramc_read(id, field) \ |
65cc1a59 | 56 | __raw_readl(pm_data.ramc[id] + field) |
4d767bc3 AB |
57 | |
58 | #define at91_ramc_write(id, field, value) \ | |
65cc1a59 | 59 | __raw_writel(value, pm_data.ramc[id] + field) |
5ad945ea | 60 | |
907d6deb AV |
61 | static int at91_pm_valid_state(suspend_state_t state) |
62 | { | |
63 | switch (state) { | |
64 | case PM_SUSPEND_ON: | |
65 | case PM_SUSPEND_STANDBY: | |
66 | case PM_SUSPEND_MEM: | |
67 | return 1; | |
68 | ||
69 | default: | |
70 | return 0; | |
71 | } | |
72 | } | |
73 | ||
24a0f5c5 | 74 | static int canary = 0xA5A5A5A5; |
907d6deb | 75 | |
24a0f5c5 AB |
76 | static struct at91_pm_bu { |
77 | int suspended; | |
78 | unsigned long reserved; | |
79 | phys_addr_t canary; | |
80 | phys_addr_t resume; | |
81 | } *pm_bu; | |
907d6deb AV |
82 | |
83 | /* | |
84 | * Called after processes are frozen, but before we shutdown devices. | |
85 | */ | |
c697eece | 86 | static int at91_pm_begin(suspend_state_t state) |
907d6deb | 87 | { |
7693e18e AB |
88 | switch (state) { |
89 | case PM_SUSPEND_MEM: | |
90 | pm_data.mode = pm_data.suspend_mode; | |
91 | break; | |
92 | ||
93 | case PM_SUSPEND_STANDBY: | |
94 | pm_data.mode = pm_data.standby_mode; | |
95 | break; | |
96 | ||
97 | default: | |
98 | pm_data.mode = -1; | |
99 | } | |
100 | ||
907d6deb AV |
101 | return 0; |
102 | } | |
103 | ||
104 | /* | |
105 | * Verify that all the clocks are correct before entering | |
106 | * slow-clock mode. | |
107 | */ | |
108 | static int at91_pm_verify_clocks(void) | |
109 | { | |
110 | unsigned long scsr; | |
111 | int i; | |
112 | ||
65cc1a59 | 113 | scsr = readl(pm_data.pmc + AT91_PMC_SCSR); |
907d6deb AV |
114 | |
115 | /* USB must not be using PLLB */ | |
65cc1a59 | 116 | if ((scsr & pm_data.uhp_udp_mask) != 0) { |
f5598d34 AB |
117 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); |
118 | return 0; | |
907d6deb AV |
119 | } |
120 | ||
907d6deb AV |
121 | /* PCK0..PCK3 must be disabled, or configured to use clk32k */ |
122 | for (i = 0; i < 4; i++) { | |
123 | u32 css; | |
124 | ||
125 | if ((scsr & (AT91_PMC_PCK0 << i)) == 0) | |
126 | continue; | |
65cc1a59 | 127 | css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; |
907d6deb | 128 | if (css != AT91_PMC_CSS_SLOW) { |
7f96b1ca | 129 | pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); |
907d6deb AV |
130 | return 0; |
131 | } | |
132 | } | |
907d6deb AV |
133 | |
134 | return 1; | |
135 | } | |
136 | ||
137 | /* | |
138 | * Call this from platform driver suspend() to see how deeply to suspend. | |
139 | * For example, some controllers (like OHCI) need one of the PLL clocks | |
140 | * in order to act as a wakeup source, and those are not available when | |
141 | * going into slow clock mode. | |
142 | * | |
143 | * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have | |
144 | * the very same problem (but not using at91 main_clk), and it'd be better | |
145 | * to add one generic API rather than lots of platform-specific ones. | |
146 | */ | |
147 | int at91_suspend_entering_slow_clock(void) | |
148 | { | |
514e2a29 | 149 | return (pm_data.mode >= AT91_PM_ULP0); |
907d6deb AV |
150 | } |
151 | EXPORT_SYMBOL(at91_suspend_entering_slow_clock); | |
152 | ||
65cc1a59 AB |
153 | static void (*at91_suspend_sram_fn)(struct at91_pm_data *); |
154 | extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); | |
5726a8b9 | 155 | extern u32 at91_pm_suspend_in_sram_sz; |
f5d0f457 | 156 | |
24a0f5c5 | 157 | static int at91_suspend_finish(unsigned long val) |
23be4be5 | 158 | { |
385acc0d WY |
159 | flush_cache_all(); |
160 | outer_disable(); | |
161 | ||
65cc1a59 | 162 | at91_suspend_sram_fn(&pm_data); |
385acc0d | 163 | |
24a0f5c5 AB |
164 | return 0; |
165 | } | |
166 | ||
167 | static void at91_pm_suspend(suspend_state_t state) | |
168 | { | |
24a0f5c5 AB |
169 | if (pm_data.mode == AT91_PM_BACKUP) { |
170 | pm_bu->suspended = 1; | |
171 | ||
172 | cpu_suspend(0, at91_suspend_finish); | |
173 | ||
174 | /* The SRAM is lost between suspend cycles */ | |
175 | at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, | |
176 | &at91_pm_suspend_in_sram, | |
177 | at91_pm_suspend_in_sram_sz); | |
178 | } else { | |
179 | at91_suspend_finish(0); | |
180 | } | |
181 | ||
385acc0d | 182 | outer_resume(); |
23be4be5 WY |
183 | } |
184 | ||
7693e18e AB |
185 | /* |
186 | * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' | |
187 | * event sources; and reduces DRAM power. But otherwise it's identical to | |
188 | * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. | |
189 | * | |
514e2a29 | 190 | * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must |
7693e18e AB |
191 | * suspend more deeply, the master clock switches to the clk32k and turns off |
192 | * the main oscillator | |
193 | * | |
194 | * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh | |
195 | */ | |
907d6deb AV |
196 | static int at91_pm_enter(suspend_state_t state) |
197 | { | |
8423536f | 198 | #ifdef CONFIG_PINCTRL_AT91 |
85c4b31e | 199 | at91_pinctrl_gpio_suspend(); |
8423536f | 200 | #endif |
7693e18e | 201 | |
907d6deb | 202 | switch (state) { |
23be4be5 | 203 | case PM_SUSPEND_MEM: |
7693e18e | 204 | case PM_SUSPEND_STANDBY: |
907d6deb | 205 | /* |
23be4be5 | 206 | * Ensure that clocks are in a valid state. |
907d6deb | 207 | */ |
514e2a29 | 208 | if (pm_data.mode >= AT91_PM_ULP0 && |
7693e18e | 209 | !at91_pm_verify_clocks()) |
23be4be5 | 210 | goto error; |
907d6deb | 211 | |
23be4be5 | 212 | at91_pm_suspend(state); |
907d6deb | 213 | |
23be4be5 | 214 | break; |
907d6deb | 215 | |
23be4be5 WY |
216 | case PM_SUSPEND_ON: |
217 | cpu_do_idle(); | |
218 | break; | |
219 | ||
220 | default: | |
221 | pr_debug("AT91: PM - bogus suspend state %d\n", state); | |
222 | goto error; | |
907d6deb AV |
223 | } |
224 | ||
907d6deb | 225 | error: |
8423536f | 226 | #ifdef CONFIG_PINCTRL_AT91 |
85c4b31e | 227 | at91_pinctrl_gpio_resume(); |
8423536f | 228 | #endif |
907d6deb AV |
229 | return 0; |
230 | } | |
231 | ||
c697eece RW |
232 | /* |
233 | * Called right prior to thawing processes. | |
234 | */ | |
235 | static void at91_pm_end(void) | |
236 | { | |
c697eece RW |
237 | } |
238 | ||
907d6deb | 239 | |
2f55ac07 | 240 | static const struct platform_suspend_ops at91_pm_ops = { |
c697eece RW |
241 | .valid = at91_pm_valid_state, |
242 | .begin = at91_pm_begin, | |
243 | .enter = at91_pm_enter, | |
244 | .end = at91_pm_end, | |
907d6deb AV |
245 | }; |
246 | ||
5ad945ea DL |
247 | static struct platform_device at91_cpuidle_device = { |
248 | .name = "cpuidle-at91", | |
249 | }; | |
250 | ||
a18d0699 AB |
251 | /* |
252 | * The AT91RM9200 goes into self-refresh mode with this command, and will | |
253 | * terminate self-refresh automatically on the next SDRAM access. | |
254 | * | |
255 | * Self-refresh mode is exited as soon as a memory access is made, but we don't | |
256 | * know for sure when that happens. However, we need to restore the low-power | |
257 | * mode if it was enabled before going idle. Restoring low-power mode while | |
258 | * still in self-refresh is "not recommended", but seems to work. | |
259 | */ | |
260 | static void at91rm9200_standby(void) | |
261 | { | |
a18d0699 AB |
262 | asm volatile( |
263 | "b 1f\n\t" | |
264 | ".align 5\n\t" | |
265 | "1: mcr p15, 0, %0, c7, c10, 4\n\t" | |
5a2d4f05 | 266 | " str %2, [%1, %3]\n\t" |
a18d0699 | 267 | " mcr p15, 0, %0, c7, c0, 4\n\t" |
a18d0699 | 268 | : |
5a2d4f05 AB |
269 | : "r" (0), "r" (pm_data.ramc[0]), |
270 | "r" (1), "r" (AT91_MC_SDRAMC_SRR)); | |
a18d0699 AB |
271 | } |
272 | ||
273 | /* We manage both DDRAM/SDRAM controllers, we need more than one value to | |
274 | * remember. | |
275 | */ | |
276 | static void at91_ddr_standby(void) | |
277 | { | |
278 | /* Those two values allow us to delay self-refresh activation | |
279 | * to the maximum. */ | |
280 | u32 lpr0, lpr1 = 0; | |
56387634 | 281 | u32 mdr, saved_mdr0, saved_mdr1 = 0; |
a18d0699 AB |
282 | u32 saved_lpr0, saved_lpr1 = 0; |
283 | ||
56387634 AB |
284 | /* LPDDR1 --> force DDR2 mode during self-refresh */ |
285 | saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); | |
286 | if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { | |
287 | mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; | |
288 | mdr |= AT91_DDRSDRC_MD_DDR2; | |
289 | at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); | |
290 | } | |
291 | ||
65cc1a59 | 292 | if (pm_data.ramc[1]) { |
a18d0699 AB |
293 | saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); |
294 | lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; | |
295 | lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; | |
56387634 AB |
296 | saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); |
297 | if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { | |
298 | mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; | |
299 | mdr |= AT91_DDRSDRC_MD_DDR2; | |
300 | at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); | |
301 | } | |
a18d0699 AB |
302 | } |
303 | ||
304 | saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); | |
305 | lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; | |
306 | lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; | |
307 | ||
308 | /* self-refresh mode now */ | |
309 | at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); | |
65cc1a59 | 310 | if (pm_data.ramc[1]) |
a18d0699 AB |
311 | at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); |
312 | ||
313 | cpu_do_idle(); | |
314 | ||
56387634 | 315 | at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); |
a18d0699 | 316 | at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); |
56387634 AB |
317 | if (pm_data.ramc[1]) { |
318 | at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); | |
a18d0699 | 319 | at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); |
56387634 | 320 | } |
a18d0699 AB |
321 | } |
322 | ||
60b89f19 NF |
323 | static void sama5d3_ddr_standby(void) |
324 | { | |
325 | u32 lpr0; | |
326 | u32 saved_lpr0; | |
327 | ||
328 | saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); | |
329 | lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; | |
330 | lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; | |
331 | ||
332 | at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); | |
333 | ||
334 | cpu_do_idle(); | |
335 | ||
336 | at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); | |
337 | } | |
338 | ||
a18d0699 AB |
339 | /* We manage both DDRAM/SDRAM controllers, we need more than one value to |
340 | * remember. | |
341 | */ | |
342 | static void at91sam9_sdram_standby(void) | |
343 | { | |
344 | u32 lpr0, lpr1 = 0; | |
345 | u32 saved_lpr0, saved_lpr1 = 0; | |
346 | ||
65cc1a59 | 347 | if (pm_data.ramc[1]) { |
a18d0699 AB |
348 | saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); |
349 | lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; | |
350 | lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; | |
351 | } | |
352 | ||
353 | saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); | |
354 | lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; | |
355 | lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; | |
356 | ||
357 | /* self-refresh mode now */ | |
358 | at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); | |
65cc1a59 | 359 | if (pm_data.ramc[1]) |
a18d0699 AB |
360 | at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); |
361 | ||
362 | cpu_do_idle(); | |
363 | ||
364 | at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); | |
65cc1a59 | 365 | if (pm_data.ramc[1]) |
a18d0699 AB |
366 | at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); |
367 | } | |
368 | ||
aab02d61 AB |
369 | struct ramc_info { |
370 | void (*idle)(void); | |
371 | unsigned int memctrl; | |
372 | }; | |
373 | ||
374 | static const struct ramc_info ramc_infos[] __initconst = { | |
375 | { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, | |
376 | { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, | |
377 | { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, | |
378 | { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, | |
379 | }; | |
380 | ||
0527873b | 381 | static const struct of_device_id ramc_ids[] __initconst = { |
aab02d61 AB |
382 | { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, |
383 | { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, | |
384 | { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, | |
385 | { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, | |
827de1f1 AB |
386 | { /*sentinel*/ } |
387 | }; | |
388 | ||
444d2d33 | 389 | static __init void at91_dt_ramc(void) |
827de1f1 AB |
390 | { |
391 | struct device_node *np; | |
392 | const struct of_device_id *of_id; | |
393 | int idx = 0; | |
e56d75a9 | 394 | void *standby = NULL; |
aab02d61 | 395 | const struct ramc_info *ramc; |
827de1f1 AB |
396 | |
397 | for_each_matching_node_and_match(np, ramc_ids, &of_id) { | |
65cc1a59 AB |
398 | pm_data.ramc[idx] = of_iomap(np, 0); |
399 | if (!pm_data.ramc[idx]) | |
827de1f1 AB |
400 | panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); |
401 | ||
aab02d61 | 402 | ramc = of_id->data; |
827de1f1 | 403 | if (!standby) |
aab02d61 AB |
404 | standby = ramc->idle; |
405 | pm_data.memctrl = ramc->memctrl; | |
827de1f1 AB |
406 | |
407 | idx++; | |
408 | } | |
409 | ||
410 | if (!idx) | |
411 | panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); | |
412 | ||
413 | if (!standby) { | |
414 | pr_warn("ramc no standby function available\n"); | |
415 | return; | |
416 | } | |
417 | ||
e56d75a9 | 418 | at91_cpuidle_device.dev.platform_data = standby; |
827de1f1 AB |
419 | } |
420 | ||
ab6778ee | 421 | static void at91rm9200_idle(void) |
fbc7edca AB |
422 | { |
423 | /* | |
424 | * Disable the processor clock. The processor will be automatically | |
425 | * re-enabled by an interrupt or by a reset. | |
426 | */ | |
65cc1a59 | 427 | writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); |
fbc7edca AB |
428 | } |
429 | ||
ab6778ee | 430 | static void at91sam9_idle(void) |
fbc7edca | 431 | { |
65cc1a59 | 432 | writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); |
fbc7edca AB |
433 | cpu_do_idle(); |
434 | } | |
435 | ||
d2e46790 AB |
436 | static void __init at91_pm_sram_init(void) |
437 | { | |
438 | struct gen_pool *sram_pool; | |
439 | phys_addr_t sram_pbase; | |
440 | unsigned long sram_base; | |
441 | struct device_node *node; | |
4a031f7d | 442 | struct platform_device *pdev = NULL; |
d2e46790 | 443 | |
4a031f7d AB |
444 | for_each_compatible_node(node, NULL, "mmio-sram") { |
445 | pdev = of_find_device_by_node(node); | |
446 | if (pdev) { | |
447 | of_node_put(node); | |
448 | break; | |
449 | } | |
d2e46790 AB |
450 | } |
451 | ||
d2e46790 AB |
452 | if (!pdev) { |
453 | pr_warn("%s: failed to find sram device!\n", __func__); | |
4a031f7d | 454 | return; |
d2e46790 AB |
455 | } |
456 | ||
73858173 | 457 | sram_pool = gen_pool_get(&pdev->dev, NULL); |
d2e46790 AB |
458 | if (!sram_pool) { |
459 | pr_warn("%s: sram pool unavailable!\n", __func__); | |
4a031f7d | 460 | return; |
d2e46790 AB |
461 | } |
462 | ||
5726a8b9 | 463 | sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); |
d2e46790 | 464 | if (!sram_base) { |
5726a8b9 | 465 | pr_warn("%s: unable to alloc sram!\n", __func__); |
4a031f7d | 466 | return; |
d2e46790 AB |
467 | } |
468 | ||
469 | sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); | |
5726a8b9 WY |
470 | at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, |
471 | at91_pm_suspend_in_sram_sz, false); | |
472 | if (!at91_suspend_sram_fn) { | |
d94e688c WY |
473 | pr_warn("SRAM: Could not map\n"); |
474 | return; | |
475 | } | |
476 | ||
5726a8b9 WY |
477 | /* Copy the pm suspend handler to SRAM */ |
478 | at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, | |
479 | &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); | |
d2e46790 | 480 | } |
d2e46790 | 481 | |
24a0f5c5 AB |
482 | static void __init at91_pm_backup_init(void) |
483 | { | |
484 | struct gen_pool *sram_pool; | |
485 | struct device_node *np; | |
486 | struct platform_device *pdev = NULL; | |
487 | ||
7693e18e AB |
488 | if ((pm_data.standby_mode != AT91_PM_BACKUP) && |
489 | (pm_data.suspend_mode != AT91_PM_BACKUP)) | |
490 | return; | |
491 | ||
24a0f5c5 AB |
492 | pm_bu = NULL; |
493 | ||
494 | np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); | |
495 | if (!np) { | |
496 | pr_warn("%s: failed to find shdwc!\n", __func__); | |
497 | return; | |
498 | } | |
499 | ||
500 | pm_data.shdwc = of_iomap(np, 0); | |
501 | of_node_put(np); | |
502 | ||
503 | np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); | |
504 | if (!np) { | |
505 | pr_warn("%s: failed to find sfrbu!\n", __func__); | |
506 | goto sfrbu_fail; | |
507 | } | |
508 | ||
509 | pm_data.sfrbu = of_iomap(np, 0); | |
510 | of_node_put(np); | |
511 | pm_bu = NULL; | |
512 | ||
513 | np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); | |
514 | if (!np) | |
515 | goto securam_fail; | |
516 | ||
517 | pdev = of_find_device_by_node(np); | |
518 | of_node_put(np); | |
519 | if (!pdev) { | |
520 | pr_warn("%s: failed to find securam device!\n", __func__); | |
521 | goto securam_fail; | |
522 | } | |
523 | ||
524 | sram_pool = gen_pool_get(&pdev->dev, NULL); | |
525 | if (!sram_pool) { | |
526 | pr_warn("%s: securam pool unavailable!\n", __func__); | |
527 | goto securam_fail; | |
528 | } | |
529 | ||
530 | pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); | |
531 | if (!pm_bu) { | |
532 | pr_warn("%s: unable to alloc securam!\n", __func__); | |
533 | goto securam_fail; | |
534 | } | |
535 | ||
536 | pm_bu->suspended = 0; | |
093d79f6 AB |
537 | pm_bu->canary = __pa_symbol(&canary); |
538 | pm_bu->resume = __pa_symbol(cpu_resume); | |
24a0f5c5 AB |
539 | |
540 | return; | |
541 | ||
542 | sfrbu_fail: | |
543 | iounmap(pm_data.shdwc); | |
544 | pm_data.shdwc = NULL; | |
545 | securam_fail: | |
546 | iounmap(pm_data.sfrbu); | |
547 | pm_data.sfrbu = NULL; | |
28732238 AB |
548 | |
549 | if (pm_data.standby_mode == AT91_PM_BACKUP) | |
514e2a29 | 550 | pm_data.standby_mode = AT91_PM_ULP0; |
28732238 | 551 | if (pm_data.suspend_mode == AT91_PM_BACKUP) |
514e2a29 | 552 | pm_data.suspend_mode = AT91_PM_ULP0; |
24a0f5c5 AB |
553 | } |
554 | ||
13f16017 AB |
555 | struct pmc_info { |
556 | unsigned long uhp_udp_mask; | |
557 | }; | |
558 | ||
559 | static const struct pmc_info pmc_infos[] __initconst = { | |
560 | { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP }, | |
561 | { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP }, | |
562 | { .uhp_udp_mask = AT91SAM926x_PMC_UHP }, | |
563 | }; | |
564 | ||
5737b73e | 565 | static const struct of_device_id atmel_pmc_ids[] __initconst = { |
13f16017 AB |
566 | { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, |
567 | { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, | |
568 | { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, | |
569 | { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, | |
570 | { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, | |
571 | { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, | |
572 | { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, | |
5737b73e AB |
573 | { /* sentinel */ }, |
574 | }; | |
575 | ||
fbc7edca | 576 | static void __init at91_pm_init(void (*pm_idle)(void)) |
907d6deb | 577 | { |
5737b73e | 578 | struct device_node *pmc_np; |
13f16017 AB |
579 | const struct of_device_id *of_id; |
580 | const struct pmc_info *pmc; | |
f5d0f457 | 581 | |
5ad945ea DL |
582 | if (at91_cpuidle_device.dev.platform_data) |
583 | platform_device_register(&at91_cpuidle_device); | |
907d6deb | 584 | |
13f16017 | 585 | pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); |
65cc1a59 AB |
586 | pm_data.pmc = of_iomap(pmc_np, 0); |
587 | if (!pm_data.pmc) { | |
5737b73e AB |
588 | pr_err("AT91: PM not supported, PMC not found\n"); |
589 | return; | |
590 | } | |
591 | ||
13f16017 AB |
592 | pmc = of_id->data; |
593 | pm_data.uhp_udp_mask = pmc->uhp_udp_mask; | |
594 | ||
fbc7edca AB |
595 | if (pm_idle) |
596 | arm_pm_idle = pm_idle; | |
597 | ||
5737b73e AB |
598 | at91_pm_sram_init(); |
599 | ||
7693e18e | 600 | if (at91_suspend_sram_fn) { |
d94e688c | 601 | suspend_set_ops(&at91_pm_ops); |
7693e18e AB |
602 | pr_info("AT91: PM: standby: %s, suspend: %s\n", |
603 | pm_modes[pm_data.standby_mode].pattern, | |
604 | pm_modes[pm_data.suspend_mode].pattern); | |
605 | } else { | |
d94e688c | 606 | pr_info("AT91: PM not supported, due to no SRAM allocated\n"); |
7693e18e | 607 | } |
4db0ba22 | 608 | } |
907d6deb | 609 | |
ad3fc3e3 | 610 | void __init at91rm9200_pm_init(void) |
4db0ba22 | 611 | { |
dbeb0c8e AB |
612 | if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) |
613 | return; | |
614 | ||
827de1f1 AB |
615 | at91_dt_ramc(); |
616 | ||
4db0ba22 AB |
617 | /* |
618 | * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. | |
619 | */ | |
d7d45f25 | 620 | at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); |
4db0ba22 | 621 | |
fbc7edca | 622 | at91_pm_init(at91rm9200_idle); |
4db0ba22 AB |
623 | } |
624 | ||
13469192 | 625 | void __init at91sam9_pm_init(void) |
bf02280e | 626 | { |
dbeb0c8e AB |
627 | if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) |
628 | return; | |
629 | ||
827de1f1 | 630 | at91_dt_ramc(); |
fbc7edca AB |
631 | at91_pm_init(at91sam9_idle); |
632 | } | |
633 | ||
634 | void __init sama5_pm_init(void) | |
635 | { | |
dbeb0c8e AB |
636 | if (!IS_ENABLED(CONFIG_SOC_SAMA5)) |
637 | return; | |
638 | ||
fbc7edca | 639 | at91_dt_ramc(); |
fbc7edca | 640 | at91_pm_init(NULL); |
bf02280e | 641 | } |
24a0f5c5 AB |
642 | |
643 | void __init sama5d2_pm_init(void) | |
644 | { | |
dbeb0c8e AB |
645 | if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) |
646 | return; | |
647 | ||
24a0f5c5 AB |
648 | at91_pm_backup_init(); |
649 | sama5_pm_init(); | |
650 | } | |
7693e18e AB |
651 | |
652 | static int __init at91_pm_modes_select(char *str) | |
653 | { | |
654 | char *s; | |
655 | substring_t args[MAX_OPT_ARGS]; | |
656 | int standby, suspend; | |
657 | ||
658 | if (!str) | |
659 | return 0; | |
660 | ||
661 | s = strsep(&str, ","); | |
662 | standby = match_token(s, pm_modes, args); | |
663 | if (standby < 0) | |
664 | return 0; | |
665 | ||
666 | suspend = match_token(str, pm_modes, args); | |
667 | if (suspend < 0) | |
668 | return 0; | |
669 | ||
670 | pm_data.standby_mode = standby; | |
671 | pm_data.suspend_mode = suspend; | |
672 | ||
673 | return 0; | |
674 | } | |
675 | early_param("atmel.pm_modes", at91_pm_modes_select); |