Commit | Line | Data |
---|---|---|
907d6deb | 1 | /* |
9d041268 | 2 | * arch/arm/mach-at91/pm.c |
907d6deb AV |
3 | * AT91 Power Management |
4 | * | |
5 | * Copyright (C) 2005 David Brownell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
d2e46790 | 13 | #include <linux/genalloc.h> |
9824c447 AB |
14 | #include <linux/io.h> |
15 | #include <linux/of_address.h> | |
f5598d34 | 16 | #include <linux/of.h> |
d2e46790 | 17 | #include <linux/of_platform.h> |
7693e18e | 18 | #include <linux/parser.h> |
9824c447 AB |
19 | #include <linux/suspend.h> |
20 | ||
2edb90ae | 21 | #include <linux/clk/at91_pmc.h> |
907d6deb | 22 | |
385acc0d | 23 | #include <asm/cacheflush.h> |
9824c447 | 24 | #include <asm/fncpy.h> |
fbc7edca | 25 | #include <asm/system_misc.h> |
24a0f5c5 | 26 | #include <asm/suspend.h> |
907d6deb | 27 | |
907d6deb | 28 | #include "generic.h" |
1ea60cf7 | 29 | #include "pm.h" |
907d6deb | 30 | |
23b84082 AB |
31 | /* |
32 | * FIXME: this is needed to communicate between the pinctrl driver and | |
33 | * the PM implementation in the machine. Possibly part of the PM | |
34 | * implementation should be moved down into the pinctrl driver and get | |
35 | * called as part of the generic suspend/resume path. | |
36 | */ | |
8423536f | 37 | #ifdef CONFIG_PINCTRL_AT91 |
23b84082 AB |
38 | extern void at91_pinctrl_gpio_suspend(void); |
39 | extern void at91_pinctrl_gpio_resume(void); | |
8423536f | 40 | #endif |
23b84082 | 41 | |
7693e18e | 42 | static const match_table_t pm_modes __initconst = { |
514e2a29 CB |
43 | { AT91_PM_STANDBY, "standby" }, |
44 | { AT91_PM_ULP0, "ulp0" }, | |
5b56c182 | 45 | { AT91_PM_ULP1, "ulp1" }, |
7693e18e AB |
46 | { AT91_PM_BACKUP, "backup" }, |
47 | { -1, NULL }, | |
48 | }; | |
49 | ||
50 | static struct at91_pm_data pm_data = { | |
514e2a29 CB |
51 | .standby_mode = AT91_PM_STANDBY, |
52 | .suspend_mode = AT91_PM_ULP0, | |
7693e18e | 53 | }; |
f5598d34 | 54 | |
4d767bc3 | 55 | #define at91_ramc_read(id, field) \ |
65cc1a59 | 56 | __raw_readl(pm_data.ramc[id] + field) |
4d767bc3 AB |
57 | |
58 | #define at91_ramc_write(id, field, value) \ | |
65cc1a59 | 59 | __raw_writel(value, pm_data.ramc[id] + field) |
5ad945ea | 60 | |
907d6deb AV |
61 | static int at91_pm_valid_state(suspend_state_t state) |
62 | { | |
63 | switch (state) { | |
64 | case PM_SUSPEND_ON: | |
65 | case PM_SUSPEND_STANDBY: | |
66 | case PM_SUSPEND_MEM: | |
67 | return 1; | |
68 | ||
69 | default: | |
70 | return 0; | |
71 | } | |
72 | } | |
73 | ||
24a0f5c5 | 74 | static int canary = 0xA5A5A5A5; |
907d6deb | 75 | |
24a0f5c5 AB |
76 | static struct at91_pm_bu { |
77 | int suspended; | |
78 | unsigned long reserved; | |
79 | phys_addr_t canary; | |
80 | phys_addr_t resume; | |
81 | } *pm_bu; | |
907d6deb | 82 | |
d7484f5c CB |
83 | struct wakeup_source_info { |
84 | unsigned int pmc_fsmr_bit; | |
85 | unsigned int shdwc_mr_bit; | |
86 | bool set_polarity; | |
87 | }; | |
88 | ||
89 | static const struct wakeup_source_info ws_info[] = { | |
90 | { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, | |
91 | { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, | |
92 | { .pmc_fsmr_bit = AT91_PMC_USBAL }, | |
93 | { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, | |
94 | }; | |
95 | ||
96 | static const struct of_device_id sama5d2_ws_ids[] = { | |
97 | { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, | |
98 | { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, | |
99 | { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, | |
100 | { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, | |
101 | { .compatible = "usb-ohci", .data = &ws_info[2] }, | |
102 | { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, | |
103 | { .compatible = "usb-ehci", .data = &ws_info[2] }, | |
104 | { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, | |
105 | { /* sentinel */ } | |
106 | }; | |
107 | ||
108 | static int at91_pm_config_ws(unsigned int pm_mode, bool set) | |
109 | { | |
110 | const struct wakeup_source_info *wsi; | |
111 | const struct of_device_id *match; | |
112 | struct platform_device *pdev; | |
113 | struct device_node *np; | |
114 | unsigned int mode = 0, polarity = 0, val = 0; | |
115 | ||
116 | if (pm_mode != AT91_PM_ULP1) | |
117 | return 0; | |
118 | ||
119 | if (!pm_data.pmc || !pm_data.shdwc) | |
120 | return -EPERM; | |
121 | ||
122 | if (!set) { | |
123 | writel(mode, pm_data.pmc + AT91_PMC_FSMR); | |
124 | return 0; | |
125 | } | |
126 | ||
127 | /* SHDWC.WUIR */ | |
128 | val = readl(pm_data.shdwc + 0x0c); | |
129 | mode |= (val & 0x3ff); | |
130 | polarity |= ((val >> 16) & 0x3ff); | |
131 | ||
132 | /* SHDWC.MR */ | |
133 | val = readl(pm_data.shdwc + 0x04); | |
134 | ||
135 | /* Loop through defined wakeup sources. */ | |
136 | for_each_matching_node_and_match(np, sama5d2_ws_ids, &match) { | |
137 | pdev = of_find_device_by_node(np); | |
138 | if (!pdev) | |
139 | continue; | |
140 | ||
141 | if (device_may_wakeup(&pdev->dev)) { | |
142 | wsi = match->data; | |
143 | ||
144 | /* Check if enabled on SHDWC. */ | |
145 | if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) | |
95590a62 | 146 | goto put_device; |
d7484f5c CB |
147 | |
148 | mode |= wsi->pmc_fsmr_bit; | |
149 | if (wsi->set_polarity) | |
150 | polarity |= wsi->pmc_fsmr_bit; | |
151 | } | |
152 | ||
95590a62 | 153 | put_device: |
154 | put_device(&pdev->dev); | |
d7484f5c CB |
155 | } |
156 | ||
157 | if (mode) { | |
158 | writel(mode, pm_data.pmc + AT91_PMC_FSMR); | |
159 | writel(polarity, pm_data.pmc + AT91_PMC_FSPR); | |
160 | } else { | |
161 | pr_err("AT91: PM: no ULP1 wakeup sources found!"); | |
162 | } | |
163 | ||
164 | return mode ? 0 : -EPERM; | |
165 | } | |
166 | ||
907d6deb AV |
167 | /* |
168 | * Called after processes are frozen, but before we shutdown devices. | |
169 | */ | |
c697eece | 170 | static int at91_pm_begin(suspend_state_t state) |
907d6deb | 171 | { |
7693e18e AB |
172 | switch (state) { |
173 | case PM_SUSPEND_MEM: | |
174 | pm_data.mode = pm_data.suspend_mode; | |
175 | break; | |
176 | ||
177 | case PM_SUSPEND_STANDBY: | |
178 | pm_data.mode = pm_data.standby_mode; | |
179 | break; | |
180 | ||
181 | default: | |
182 | pm_data.mode = -1; | |
183 | } | |
184 | ||
d7484f5c | 185 | return at91_pm_config_ws(pm_data.mode, true); |
907d6deb AV |
186 | } |
187 | ||
188 | /* | |
189 | * Verify that all the clocks are correct before entering | |
190 | * slow-clock mode. | |
191 | */ | |
192 | static int at91_pm_verify_clocks(void) | |
193 | { | |
194 | unsigned long scsr; | |
195 | int i; | |
196 | ||
65cc1a59 | 197 | scsr = readl(pm_data.pmc + AT91_PMC_SCSR); |
907d6deb AV |
198 | |
199 | /* USB must not be using PLLB */ | |
65cc1a59 | 200 | if ((scsr & pm_data.uhp_udp_mask) != 0) { |
f5598d34 AB |
201 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); |
202 | return 0; | |
907d6deb AV |
203 | } |
204 | ||
907d6deb AV |
205 | /* PCK0..PCK3 must be disabled, or configured to use clk32k */ |
206 | for (i = 0; i < 4; i++) { | |
207 | u32 css; | |
208 | ||
209 | if ((scsr & (AT91_PMC_PCK0 << i)) == 0) | |
210 | continue; | |
65cc1a59 | 211 | css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; |
907d6deb | 212 | if (css != AT91_PMC_CSS_SLOW) { |
7f96b1ca | 213 | pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); |
907d6deb AV |
214 | return 0; |
215 | } | |
216 | } | |
907d6deb AV |
217 | |
218 | return 1; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Call this from platform driver suspend() to see how deeply to suspend. | |
223 | * For example, some controllers (like OHCI) need one of the PLL clocks | |
224 | * in order to act as a wakeup source, and those are not available when | |
225 | * going into slow clock mode. | |
226 | * | |
227 | * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have | |
228 | * the very same problem (but not using at91 main_clk), and it'd be better | |
229 | * to add one generic API rather than lots of platform-specific ones. | |
230 | */ | |
231 | int at91_suspend_entering_slow_clock(void) | |
232 | { | |
514e2a29 | 233 | return (pm_data.mode >= AT91_PM_ULP0); |
907d6deb AV |
234 | } |
235 | EXPORT_SYMBOL(at91_suspend_entering_slow_clock); | |
236 | ||
65cc1a59 AB |
237 | static void (*at91_suspend_sram_fn)(struct at91_pm_data *); |
238 | extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); | |
5726a8b9 | 239 | extern u32 at91_pm_suspend_in_sram_sz; |
f5d0f457 | 240 | |
24a0f5c5 | 241 | static int at91_suspend_finish(unsigned long val) |
23be4be5 | 242 | { |
385acc0d WY |
243 | flush_cache_all(); |
244 | outer_disable(); | |
245 | ||
65cc1a59 | 246 | at91_suspend_sram_fn(&pm_data); |
385acc0d | 247 | |
24a0f5c5 AB |
248 | return 0; |
249 | } | |
250 | ||
251 | static void at91_pm_suspend(suspend_state_t state) | |
252 | { | |
24a0f5c5 AB |
253 | if (pm_data.mode == AT91_PM_BACKUP) { |
254 | pm_bu->suspended = 1; | |
255 | ||
256 | cpu_suspend(0, at91_suspend_finish); | |
257 | ||
258 | /* The SRAM is lost between suspend cycles */ | |
259 | at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, | |
260 | &at91_pm_suspend_in_sram, | |
261 | at91_pm_suspend_in_sram_sz); | |
262 | } else { | |
263 | at91_suspend_finish(0); | |
264 | } | |
265 | ||
385acc0d | 266 | outer_resume(); |
23be4be5 WY |
267 | } |
268 | ||
7693e18e AB |
269 | /* |
270 | * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' | |
271 | * event sources; and reduces DRAM power. But otherwise it's identical to | |
272 | * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. | |
273 | * | |
514e2a29 | 274 | * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must |
7693e18e AB |
275 | * suspend more deeply, the master clock switches to the clk32k and turns off |
276 | * the main oscillator | |
277 | * | |
278 | * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh | |
279 | */ | |
907d6deb AV |
280 | static int at91_pm_enter(suspend_state_t state) |
281 | { | |
8423536f | 282 | #ifdef CONFIG_PINCTRL_AT91 |
85c4b31e | 283 | at91_pinctrl_gpio_suspend(); |
8423536f | 284 | #endif |
7693e18e | 285 | |
907d6deb | 286 | switch (state) { |
23be4be5 | 287 | case PM_SUSPEND_MEM: |
7693e18e | 288 | case PM_SUSPEND_STANDBY: |
907d6deb | 289 | /* |
23be4be5 | 290 | * Ensure that clocks are in a valid state. |
907d6deb | 291 | */ |
514e2a29 | 292 | if (pm_data.mode >= AT91_PM_ULP0 && |
7693e18e | 293 | !at91_pm_verify_clocks()) |
23be4be5 | 294 | goto error; |
907d6deb | 295 | |
23be4be5 | 296 | at91_pm_suspend(state); |
907d6deb | 297 | |
23be4be5 | 298 | break; |
907d6deb | 299 | |
23be4be5 WY |
300 | case PM_SUSPEND_ON: |
301 | cpu_do_idle(); | |
302 | break; | |
303 | ||
304 | default: | |
305 | pr_debug("AT91: PM - bogus suspend state %d\n", state); | |
306 | goto error; | |
907d6deb AV |
307 | } |
308 | ||
907d6deb | 309 | error: |
8423536f | 310 | #ifdef CONFIG_PINCTRL_AT91 |
85c4b31e | 311 | at91_pinctrl_gpio_resume(); |
8423536f | 312 | #endif |
907d6deb AV |
313 | return 0; |
314 | } | |
315 | ||
c697eece RW |
316 | /* |
317 | * Called right prior to thawing processes. | |
318 | */ | |
319 | static void at91_pm_end(void) | |
320 | { | |
d7484f5c | 321 | at91_pm_config_ws(pm_data.mode, false); |
c697eece RW |
322 | } |
323 | ||
907d6deb | 324 | |
2f55ac07 | 325 | static const struct platform_suspend_ops at91_pm_ops = { |
c697eece RW |
326 | .valid = at91_pm_valid_state, |
327 | .begin = at91_pm_begin, | |
328 | .enter = at91_pm_enter, | |
329 | .end = at91_pm_end, | |
907d6deb AV |
330 | }; |
331 | ||
5ad945ea DL |
332 | static struct platform_device at91_cpuidle_device = { |
333 | .name = "cpuidle-at91", | |
334 | }; | |
335 | ||
a18d0699 AB |
336 | /* |
337 | * The AT91RM9200 goes into self-refresh mode with this command, and will | |
338 | * terminate self-refresh automatically on the next SDRAM access. | |
339 | * | |
340 | * Self-refresh mode is exited as soon as a memory access is made, but we don't | |
341 | * know for sure when that happens. However, we need to restore the low-power | |
342 | * mode if it was enabled before going idle. Restoring low-power mode while | |
343 | * still in self-refresh is "not recommended", but seems to work. | |
344 | */ | |
345 | static void at91rm9200_standby(void) | |
346 | { | |
a18d0699 AB |
347 | asm volatile( |
348 | "b 1f\n\t" | |
349 | ".align 5\n\t" | |
350 | "1: mcr p15, 0, %0, c7, c10, 4\n\t" | |
5a2d4f05 | 351 | " str %2, [%1, %3]\n\t" |
a18d0699 | 352 | " mcr p15, 0, %0, c7, c0, 4\n\t" |
a18d0699 | 353 | : |
5a2d4f05 AB |
354 | : "r" (0), "r" (pm_data.ramc[0]), |
355 | "r" (1), "r" (AT91_MC_SDRAMC_SRR)); | |
a18d0699 AB |
356 | } |
357 | ||
358 | /* We manage both DDRAM/SDRAM controllers, we need more than one value to | |
359 | * remember. | |
360 | */ | |
361 | static void at91_ddr_standby(void) | |
362 | { | |
363 | /* Those two values allow us to delay self-refresh activation | |
364 | * to the maximum. */ | |
365 | u32 lpr0, lpr1 = 0; | |
56387634 | 366 | u32 mdr, saved_mdr0, saved_mdr1 = 0; |
a18d0699 AB |
367 | u32 saved_lpr0, saved_lpr1 = 0; |
368 | ||
56387634 AB |
369 | /* LPDDR1 --> force DDR2 mode during self-refresh */ |
370 | saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); | |
371 | if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { | |
372 | mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; | |
373 | mdr |= AT91_DDRSDRC_MD_DDR2; | |
374 | at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); | |
375 | } | |
376 | ||
65cc1a59 | 377 | if (pm_data.ramc[1]) { |
a18d0699 AB |
378 | saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); |
379 | lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; | |
380 | lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; | |
56387634 AB |
381 | saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); |
382 | if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { | |
383 | mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; | |
384 | mdr |= AT91_DDRSDRC_MD_DDR2; | |
385 | at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); | |
386 | } | |
a18d0699 AB |
387 | } |
388 | ||
389 | saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); | |
390 | lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; | |
391 | lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; | |
392 | ||
393 | /* self-refresh mode now */ | |
394 | at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); | |
65cc1a59 | 395 | if (pm_data.ramc[1]) |
a18d0699 AB |
396 | at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); |
397 | ||
398 | cpu_do_idle(); | |
399 | ||
56387634 | 400 | at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); |
a18d0699 | 401 | at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); |
56387634 AB |
402 | if (pm_data.ramc[1]) { |
403 | at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); | |
a18d0699 | 404 | at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); |
56387634 | 405 | } |
a18d0699 AB |
406 | } |
407 | ||
60b89f19 NF |
408 | static void sama5d3_ddr_standby(void) |
409 | { | |
410 | u32 lpr0; | |
411 | u32 saved_lpr0; | |
412 | ||
413 | saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); | |
414 | lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; | |
415 | lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; | |
416 | ||
417 | at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); | |
418 | ||
419 | cpu_do_idle(); | |
420 | ||
421 | at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); | |
422 | } | |
423 | ||
a18d0699 AB |
424 | /* We manage both DDRAM/SDRAM controllers, we need more than one value to |
425 | * remember. | |
426 | */ | |
427 | static void at91sam9_sdram_standby(void) | |
428 | { | |
429 | u32 lpr0, lpr1 = 0; | |
430 | u32 saved_lpr0, saved_lpr1 = 0; | |
431 | ||
65cc1a59 | 432 | if (pm_data.ramc[1]) { |
a18d0699 AB |
433 | saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); |
434 | lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; | |
435 | lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; | |
436 | } | |
437 | ||
438 | saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); | |
439 | lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; | |
440 | lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; | |
441 | ||
442 | /* self-refresh mode now */ | |
443 | at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); | |
65cc1a59 | 444 | if (pm_data.ramc[1]) |
a18d0699 AB |
445 | at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); |
446 | ||
447 | cpu_do_idle(); | |
448 | ||
449 | at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); | |
65cc1a59 | 450 | if (pm_data.ramc[1]) |
a18d0699 AB |
451 | at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); |
452 | } | |
453 | ||
aab02d61 AB |
454 | struct ramc_info { |
455 | void (*idle)(void); | |
456 | unsigned int memctrl; | |
457 | }; | |
458 | ||
459 | static const struct ramc_info ramc_infos[] __initconst = { | |
460 | { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, | |
461 | { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, | |
462 | { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, | |
463 | { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, | |
464 | }; | |
465 | ||
0527873b | 466 | static const struct of_device_id ramc_ids[] __initconst = { |
aab02d61 AB |
467 | { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, |
468 | { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, | |
469 | { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, | |
470 | { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, | |
827de1f1 AB |
471 | { /*sentinel*/ } |
472 | }; | |
473 | ||
444d2d33 | 474 | static __init void at91_dt_ramc(void) |
827de1f1 AB |
475 | { |
476 | struct device_node *np; | |
477 | const struct of_device_id *of_id; | |
478 | int idx = 0; | |
e56d75a9 | 479 | void *standby = NULL; |
aab02d61 | 480 | const struct ramc_info *ramc; |
827de1f1 AB |
481 | |
482 | for_each_matching_node_and_match(np, ramc_ids, &of_id) { | |
65cc1a59 AB |
483 | pm_data.ramc[idx] = of_iomap(np, 0); |
484 | if (!pm_data.ramc[idx]) | |
827de1f1 AB |
485 | panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); |
486 | ||
aab02d61 | 487 | ramc = of_id->data; |
827de1f1 | 488 | if (!standby) |
aab02d61 AB |
489 | standby = ramc->idle; |
490 | pm_data.memctrl = ramc->memctrl; | |
827de1f1 AB |
491 | |
492 | idx++; | |
493 | } | |
494 | ||
495 | if (!idx) | |
496 | panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); | |
497 | ||
498 | if (!standby) { | |
499 | pr_warn("ramc no standby function available\n"); | |
500 | return; | |
501 | } | |
502 | ||
e56d75a9 | 503 | at91_cpuidle_device.dev.platform_data = standby; |
827de1f1 AB |
504 | } |
505 | ||
ab6778ee | 506 | static void at91rm9200_idle(void) |
fbc7edca AB |
507 | { |
508 | /* | |
509 | * Disable the processor clock. The processor will be automatically | |
510 | * re-enabled by an interrupt or by a reset. | |
511 | */ | |
65cc1a59 | 512 | writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); |
fbc7edca AB |
513 | } |
514 | ||
ab6778ee | 515 | static void at91sam9_idle(void) |
fbc7edca | 516 | { |
65cc1a59 | 517 | writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); |
fbc7edca AB |
518 | cpu_do_idle(); |
519 | } | |
520 | ||
d2e46790 AB |
521 | static void __init at91_pm_sram_init(void) |
522 | { | |
523 | struct gen_pool *sram_pool; | |
524 | phys_addr_t sram_pbase; | |
525 | unsigned long sram_base; | |
526 | struct device_node *node; | |
4a031f7d | 527 | struct platform_device *pdev = NULL; |
d2e46790 | 528 | |
4a031f7d AB |
529 | for_each_compatible_node(node, NULL, "mmio-sram") { |
530 | pdev = of_find_device_by_node(node); | |
531 | if (pdev) { | |
532 | of_node_put(node); | |
533 | break; | |
534 | } | |
d2e46790 AB |
535 | } |
536 | ||
d2e46790 AB |
537 | if (!pdev) { |
538 | pr_warn("%s: failed to find sram device!\n", __func__); | |
4a031f7d | 539 | return; |
d2e46790 AB |
540 | } |
541 | ||
73858173 | 542 | sram_pool = gen_pool_get(&pdev->dev, NULL); |
d2e46790 AB |
543 | if (!sram_pool) { |
544 | pr_warn("%s: sram pool unavailable!\n", __func__); | |
4a031f7d | 545 | return; |
d2e46790 AB |
546 | } |
547 | ||
5726a8b9 | 548 | sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); |
d2e46790 | 549 | if (!sram_base) { |
5726a8b9 | 550 | pr_warn("%s: unable to alloc sram!\n", __func__); |
4a031f7d | 551 | return; |
d2e46790 AB |
552 | } |
553 | ||
554 | sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); | |
5726a8b9 WY |
555 | at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, |
556 | at91_pm_suspend_in_sram_sz, false); | |
557 | if (!at91_suspend_sram_fn) { | |
d94e688c WY |
558 | pr_warn("SRAM: Could not map\n"); |
559 | return; | |
560 | } | |
561 | ||
5726a8b9 WY |
562 | /* Copy the pm suspend handler to SRAM */ |
563 | at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, | |
564 | &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); | |
d2e46790 | 565 | } |
d2e46790 | 566 | |
d7484f5c CB |
567 | static bool __init at91_is_pm_mode_active(int pm_mode) |
568 | { | |
569 | return (pm_data.standby_mode == pm_mode || | |
570 | pm_data.suspend_mode == pm_mode); | |
571 | } | |
572 | ||
573 | static int __init at91_pm_backup_init(void) | |
24a0f5c5 AB |
574 | { |
575 | struct gen_pool *sram_pool; | |
576 | struct device_node *np; | |
577 | struct platform_device *pdev = NULL; | |
d7484f5c | 578 | int ret = -ENODEV; |
24a0f5c5 | 579 | |
d7484f5c CB |
580 | if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) |
581 | return 0; | |
7693e18e | 582 | |
24a0f5c5 AB |
583 | np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); |
584 | if (!np) { | |
585 | pr_warn("%s: failed to find sfrbu!\n", __func__); | |
d7484f5c | 586 | return ret; |
24a0f5c5 AB |
587 | } |
588 | ||
589 | pm_data.sfrbu = of_iomap(np, 0); | |
590 | of_node_put(np); | |
24a0f5c5 AB |
591 | |
592 | np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); | |
593 | if (!np) | |
ba5e60c9 | 594 | goto securam_fail_no_ref_dev; |
24a0f5c5 AB |
595 | |
596 | pdev = of_find_device_by_node(np); | |
597 | of_node_put(np); | |
598 | if (!pdev) { | |
599 | pr_warn("%s: failed to find securam device!\n", __func__); | |
ba5e60c9 | 600 | goto securam_fail_no_ref_dev; |
24a0f5c5 AB |
601 | } |
602 | ||
603 | sram_pool = gen_pool_get(&pdev->dev, NULL); | |
604 | if (!sram_pool) { | |
605 | pr_warn("%s: securam pool unavailable!\n", __func__); | |
606 | goto securam_fail; | |
607 | } | |
608 | ||
609 | pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); | |
610 | if (!pm_bu) { | |
611 | pr_warn("%s: unable to alloc securam!\n", __func__); | |
d7484f5c | 612 | ret = -ENOMEM; |
24a0f5c5 AB |
613 | goto securam_fail; |
614 | } | |
615 | ||
616 | pm_bu->suspended = 0; | |
093d79f6 AB |
617 | pm_bu->canary = __pa_symbol(&canary); |
618 | pm_bu->resume = __pa_symbol(cpu_resume); | |
24a0f5c5 | 619 | |
d7484f5c | 620 | return 0; |
24a0f5c5 | 621 | |
24a0f5c5 | 622 | securam_fail: |
ba5e60c9 PH |
623 | put_device(&pdev->dev); |
624 | securam_fail_no_ref_dev: | |
24a0f5c5 AB |
625 | iounmap(pm_data.sfrbu); |
626 | pm_data.sfrbu = NULL; | |
d7484f5c CB |
627 | return ret; |
628 | } | |
28732238 | 629 | |
d7484f5c CB |
630 | static void __init at91_pm_use_default_mode(int pm_mode) |
631 | { | |
632 | if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP) | |
633 | return; | |
634 | ||
635 | if (pm_data.standby_mode == pm_mode) | |
514e2a29 | 636 | pm_data.standby_mode = AT91_PM_ULP0; |
d7484f5c | 637 | if (pm_data.suspend_mode == pm_mode) |
514e2a29 | 638 | pm_data.suspend_mode = AT91_PM_ULP0; |
24a0f5c5 AB |
639 | } |
640 | ||
d7484f5c CB |
641 | static void __init at91_pm_modes_init(void) |
642 | { | |
643 | struct device_node *np; | |
644 | int ret; | |
645 | ||
646 | if (!at91_is_pm_mode_active(AT91_PM_BACKUP) && | |
647 | !at91_is_pm_mode_active(AT91_PM_ULP1)) | |
648 | return; | |
649 | ||
650 | np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); | |
651 | if (!np) { | |
652 | pr_warn("%s: failed to find shdwc!\n", __func__); | |
653 | goto ulp1_default; | |
654 | } | |
655 | ||
656 | pm_data.shdwc = of_iomap(np, 0); | |
657 | of_node_put(np); | |
658 | ||
659 | ret = at91_pm_backup_init(); | |
660 | if (ret) { | |
661 | if (!at91_is_pm_mode_active(AT91_PM_ULP1)) | |
662 | goto unmap; | |
663 | else | |
664 | goto backup_default; | |
665 | } | |
666 | ||
667 | return; | |
668 | ||
669 | unmap: | |
670 | iounmap(pm_data.shdwc); | |
671 | pm_data.shdwc = NULL; | |
672 | ulp1_default: | |
673 | at91_pm_use_default_mode(AT91_PM_ULP1); | |
674 | backup_default: | |
675 | at91_pm_use_default_mode(AT91_PM_BACKUP); | |
676 | } | |
677 | ||
13f16017 AB |
678 | struct pmc_info { |
679 | unsigned long uhp_udp_mask; | |
680 | }; | |
681 | ||
682 | static const struct pmc_info pmc_infos[] __initconst = { | |
683 | { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP }, | |
684 | { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP }, | |
685 | { .uhp_udp_mask = AT91SAM926x_PMC_UHP }, | |
91f87180 | 686 | { .uhp_udp_mask = 0 }, |
13f16017 AB |
687 | }; |
688 | ||
5737b73e | 689 | static const struct of_device_id atmel_pmc_ids[] __initconst = { |
13f16017 AB |
690 | { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, |
691 | { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, | |
91f87180 AB |
692 | { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, |
693 | { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, | |
13f16017 AB |
694 | { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, |
695 | { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, | |
91f87180 | 696 | { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, |
13f16017 AB |
697 | { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, |
698 | { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, | |
91f87180 | 699 | { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, |
13f16017 | 700 | { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, |
5737b73e AB |
701 | { /* sentinel */ }, |
702 | }; | |
703 | ||
fbc7edca | 704 | static void __init at91_pm_init(void (*pm_idle)(void)) |
907d6deb | 705 | { |
5737b73e | 706 | struct device_node *pmc_np; |
13f16017 AB |
707 | const struct of_device_id *of_id; |
708 | const struct pmc_info *pmc; | |
f5d0f457 | 709 | |
5ad945ea DL |
710 | if (at91_cpuidle_device.dev.platform_data) |
711 | platform_device_register(&at91_cpuidle_device); | |
907d6deb | 712 | |
13f16017 | 713 | pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); |
65cc1a59 AB |
714 | pm_data.pmc = of_iomap(pmc_np, 0); |
715 | if (!pm_data.pmc) { | |
5737b73e AB |
716 | pr_err("AT91: PM not supported, PMC not found\n"); |
717 | return; | |
718 | } | |
719 | ||
13f16017 AB |
720 | pmc = of_id->data; |
721 | pm_data.uhp_udp_mask = pmc->uhp_udp_mask; | |
722 | ||
fbc7edca AB |
723 | if (pm_idle) |
724 | arm_pm_idle = pm_idle; | |
725 | ||
5737b73e AB |
726 | at91_pm_sram_init(); |
727 | ||
7693e18e | 728 | if (at91_suspend_sram_fn) { |
d94e688c | 729 | suspend_set_ops(&at91_pm_ops); |
7693e18e AB |
730 | pr_info("AT91: PM: standby: %s, suspend: %s\n", |
731 | pm_modes[pm_data.standby_mode].pattern, | |
732 | pm_modes[pm_data.suspend_mode].pattern); | |
733 | } else { | |
d94e688c | 734 | pr_info("AT91: PM not supported, due to no SRAM allocated\n"); |
7693e18e | 735 | } |
4db0ba22 | 736 | } |
907d6deb | 737 | |
ad3fc3e3 | 738 | void __init at91rm9200_pm_init(void) |
4db0ba22 | 739 | { |
dbeb0c8e AB |
740 | if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) |
741 | return; | |
742 | ||
827de1f1 AB |
743 | at91_dt_ramc(); |
744 | ||
4db0ba22 AB |
745 | /* |
746 | * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. | |
747 | */ | |
d7d45f25 | 748 | at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); |
4db0ba22 | 749 | |
fbc7edca | 750 | at91_pm_init(at91rm9200_idle); |
4db0ba22 AB |
751 | } |
752 | ||
13469192 | 753 | void __init at91sam9_pm_init(void) |
bf02280e | 754 | { |
dbeb0c8e AB |
755 | if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) |
756 | return; | |
757 | ||
827de1f1 | 758 | at91_dt_ramc(); |
fbc7edca AB |
759 | at91_pm_init(at91sam9_idle); |
760 | } | |
761 | ||
762 | void __init sama5_pm_init(void) | |
763 | { | |
dbeb0c8e AB |
764 | if (!IS_ENABLED(CONFIG_SOC_SAMA5)) |
765 | return; | |
766 | ||
fbc7edca | 767 | at91_dt_ramc(); |
fbc7edca | 768 | at91_pm_init(NULL); |
bf02280e | 769 | } |
24a0f5c5 AB |
770 | |
771 | void __init sama5d2_pm_init(void) | |
772 | { | |
dbeb0c8e AB |
773 | if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) |
774 | return; | |
775 | ||
d7484f5c | 776 | at91_pm_modes_init(); |
24a0f5c5 AB |
777 | sama5_pm_init(); |
778 | } | |
7693e18e AB |
779 | |
780 | static int __init at91_pm_modes_select(char *str) | |
781 | { | |
782 | char *s; | |
783 | substring_t args[MAX_OPT_ARGS]; | |
784 | int standby, suspend; | |
785 | ||
786 | if (!str) | |
787 | return 0; | |
788 | ||
789 | s = strsep(&str, ","); | |
790 | standby = match_token(s, pm_modes, args); | |
791 | if (standby < 0) | |
792 | return 0; | |
793 | ||
794 | suspend = match_token(str, pm_modes, args); | |
795 | if (suspend < 0) | |
796 | return 0; | |
797 | ||
798 | pm_data.standby_mode = standby; | |
799 | pm_data.suspend_mode = suspend; | |
800 | ||
801 | return 0; | |
802 | } | |
803 | early_param("atmel.pm_modes", at91_pm_modes_select); |