[linux-block.git] / arch / arm / mach-at91 / include / mach / at91rm9200.h

/*
 * arch/arm/mach-at91/include/mach/at91rm9200.h
 *
 * Copyright (C) 2005 Ivan Kokshaysky
 * Copyright (C) SAN People
 *
 * Common definitions.
 * Based on AT91RM9200 datasheet revision E.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef AT91RM9200_H
#define AT91RM9200_H

/*
 * Peripheral identifiers/interrupts.
 */
#define AT91RM9200_ID_PIOA	2	/* Parallel IO Controller A */
#define AT91RM9200_ID_PIOB	3	/* Parallel IO Controller B */
#define AT91RM9200_ID_PIOC	4	/* Parallel IO Controller C */
#define AT91RM9200_ID_PIOD	5	/* Parallel IO Controller D */
#define AT91RM9200_ID_US0	6	/* USART 0 */
#define AT91RM9200_ID_US1	7	/* USART 1 */
#define AT91RM9200_ID_US2	8	/* USART 2 */
#define AT91RM9200_ID_US3	9	/* USART 3 */
#define AT91RM9200_ID_MCI	10	/* Multimedia Card Interface */
#define AT91RM9200_ID_UDP	11	/* USB Device Port */
#define AT91RM9200_ID_TWI	12	/* Two-Wire Interface */
#define AT91RM9200_ID_SPI	13	/* Serial Peripheral Interface */
#define AT91RM9200_ID_SSC0	14	/* Serial Synchronous Controller 0 */
#define AT91RM9200_ID_SSC1	15	/* Serial Synchronous Controller 1 */
#define AT91RM9200_ID_SSC2	16	/* Serial Synchronous Controller 2 */
#define AT91RM9200_ID_TC0	17	/* Timer Counter 0 */
#define AT91RM9200_ID_TC1	18	/* Timer Counter 1 */
#define AT91RM9200_ID_TC2	19	/* Timer Counter 2 */
#define AT91RM9200_ID_TC3	20	/* Timer Counter 3 */
#define AT91RM9200_ID_TC4	21	/* Timer Counter 4 */
#define AT91RM9200_ID_TC5	22	/* Timer Counter 5 */
#define AT91RM9200_ID_UHP	23	/* USB Host port */
#define AT91RM9200_ID_EMAC	24	/* Ethernet MAC */
#define AT91RM9200_ID_IRQ0	25	/* Advanced Interrupt Controller (IRQ0) */
#define AT91RM9200_ID_IRQ1	26	/* Advanced Interrupt Controller (IRQ1) */
#define AT91RM9200_ID_IRQ2	27	/* Advanced Interrupt Controller (IRQ2) */
#define AT91RM9200_ID_IRQ3	28	/* Advanced Interrupt Controller (IRQ3) */
#define AT91RM9200_ID_IRQ4	29	/* Advanced Interrupt Controller (IRQ4) */
#define AT91RM9200_ID_IRQ5	30	/* Advanced Interrupt Controller (IRQ5) */
#define AT91RM9200_ID_IRQ6	31	/* Advanced Interrupt Controller (IRQ6) */


/*
 * Peripheral physical base addresses.
 */
#define AT91RM9200_BASE_TCB0	0xfffa0000
#define AT91RM9200_BASE_TC0	0xfffa0000
#define AT91RM9200_BASE_TC1	0xfffa0040
#define AT91RM9200_BASE_TC2	0xfffa0080
#define AT91RM9200_BASE_TCB1	0xfffa4000
#define AT91RM9200_BASE_TC3	0xfffa4000
#define AT91RM9200_BASE_TC4	0xfffa4040
#define AT91RM9200_BASE_TC5	0xfffa4080
#define AT91RM9200_BASE_UDP	0xfffb0000
#define AT91RM9200_BASE_MCI	0xfffb4000
#define AT91RM9200_BASE_TWI	0xfffb8000
#define AT91RM9200_BASE_EMAC	0xfffbc000
#define AT91RM9200_BASE_US0	0xfffc0000
#define AT91RM9200_BASE_US1	0xfffc4000
#define AT91RM9200_BASE_US2	0xfffc8000
#define AT91RM9200_BASE_US3	0xfffcc000
#define AT91RM9200_BASE_SSC0	0xfffd0000
#define AT91RM9200_BASE_SSC1	0xfffd4000
#define AT91RM9200_BASE_SSC2	0xfffd8000
#define AT91RM9200_BASE_SPI	0xfffe0000


/*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)	/* Advanced Interrupt Controller */
#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)	/* Power Management Controller */
#define AT91_ST		(0xfffffd00 - AT91_BASE_SYS)	/* System Timer */
#define AT91_RTC	(0xfffffe00 - AT91_BASE_SYS)	/* Real-Time Clock */
#define AT91_MC		(0xffffff00 - AT91_BASE_SYS)	/* Memory Controllers */

#define AT91RM9200_BASE_DBGU	AT91_BASE_DBGU0	/* Debug Unit */
#define AT91RM9200_BASE_PIOA	0xfffff400	/* PIO Controller A */
#define AT91RM9200_BASE_PIOB	0xfffff600	/* PIO Controller B */
#define AT91RM9200_BASE_PIOC	0xfffff800	/* PIO Controller C */
#define AT91RM9200_BASE_PIOD	0xfffffa00	/* PIO Controller D */

#define AT91_USART0	AT91RM9200_BASE_US0
#define AT91_USART1	AT91RM9200_BASE_US1
#define AT91_USART2	AT91RM9200_BASE_US2
#define AT91_USART3	AT91RM9200_BASE_US3

#define AT91_MATRIX	0	/* not supported */

/*
 * Internal Memory.
 */
#define AT91RM9200_ROM_BASE	0x00100000	/* Internal ROM base address */
#define AT91RM9200_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */

#define AT91RM9200_SRAM_BASE	0x00200000	/* Internal SRAM base address */
#define AT91RM9200_SRAM_SIZE	SZ_16K		/* Internal SRAM size (16Kb) */

#define AT91RM9200_UHP_BASE	0x00300000	/* USB Host controller */


#endif
Commit	Line	Data
73a59c1c	1	/*
a09e64fb	2	* arch/arm/mach-at91/include/mach/at91rm9200.h
73a59c1c SP	3	*
	4	* Copyright (C) 2005 Ivan Kokshaysky
	5	* Copyright (C) SAN People
	6	*
	7	* Common definitions.
	8	* Based on AT91RM9200 datasheet revision E.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*/
	15
	16	#ifndef AT91RM9200_H
	17	#define AT91RM9200_H
	18
	19	/*
	20	* Peripheral identifiers/interrupts.
	21	*/
72729910 AV	22	#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
	23	#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
	24	#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
	25	#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
	26	#define AT91RM9200_ID_US0 6 /* USART 0 */
	27	#define AT91RM9200_ID_US1 7 /* USART 1 */
	28	#define AT91RM9200_ID_US2 8 /* USART 2 */
	29	#define AT91RM9200_ID_US3 9 /* USART 3 */
	30	#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
	31	#define AT91RM9200_ID_UDP 11 /* USB Device Port */
	32	#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
	33	#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
	34	#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
	35	#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
	36	#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
	37	#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
	38	#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
	39	#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
	40	#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
	41	#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
	42	#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
	43	#define AT91RM9200_ID_UHP 23 /* USB Host port */
	44	#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
	45	#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
	46	#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
	47	#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
	48	#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
	49	#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
	50	#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
	51	#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
73a59c1c SP	52
	53
	54	/*
	55	* Peripheral physical base addresses.
	56	*/
72729910 AV	57	#define AT91RM9200_BASE_TCB0 0xfffa0000
	58	#define AT91RM9200_BASE_TC0 0xfffa0000
	59	#define AT91RM9200_BASE_TC1 0xfffa0040
	60	#define AT91RM9200_BASE_TC2 0xfffa0080
	61	#define AT91RM9200_BASE_TCB1 0xfffa4000
	62	#define AT91RM9200_BASE_TC3 0xfffa4000
	63	#define AT91RM9200_BASE_TC4 0xfffa4040
	64	#define AT91RM9200_BASE_TC5 0xfffa4080
	65	#define AT91RM9200_BASE_UDP 0xfffb0000
	66	#define AT91RM9200_BASE_MCI 0xfffb4000
	67	#define AT91RM9200_BASE_TWI 0xfffb8000
	68	#define AT91RM9200_BASE_EMAC 0xfffbc000
	69	#define AT91RM9200_BASE_US0 0xfffc0000
	70	#define AT91RM9200_BASE_US1 0xfffc4000
	71	#define AT91RM9200_BASE_US2 0xfffc8000
	72	#define AT91RM9200_BASE_US3 0xfffcc000
	73	#define AT91RM9200_BASE_SSC0 0xfffd0000
	74	#define AT91RM9200_BASE_SSC1 0xfffd4000
	75	#define AT91RM9200_BASE_SSC2 0xfffd8000
	76	#define AT91RM9200_BASE_SPI 0xfffe0000
73a59c1c SP	77
73a59c1c SP	78
55d8baee AV	79	/*
	80	* System Peripherals (offset from AT91_BASE_SYS)
	81	*/
	82	#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
55d8baee AV	83	#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
	84	#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
	85	#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
	86	#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
	87
13079a73	88	#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
80e91cb8 JCPV	89	#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
	90	#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
	91	#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
	92	#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
	93
fa3218d8 GL	94	#define AT91_USART0 AT91RM9200_BASE_US0
	95	#define AT91_USART1 AT91RM9200_BASE_US1
	96	#define AT91_USART2 AT91RM9200_BASE_US2
	97	#define AT91_USART3 AT91RM9200_BASE_US3
	98
55d8baee AV	99	#define AT91_MATRIX 0 /* not supported */
55d8baee AV	100
72729910 AV	101	/*
	102	* Internal Memory.
	103	*/
	104	#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
	105	#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
	106
	107	#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
	108	#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
	109
	110	#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
	111
	112
73a59c1c	113	#endif