Commit | Line | Data |
---|---|---|
73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/clock.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2005 David Brownell | |
5 | * Copyright (C) 2005 Ivan Kokshaysky | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/fs.h> | |
17 | #include <linux/debugfs.h> | |
18 | #include <linux/seq_file.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/clk.h> | |
fced80c7 | 25 | #include <linux/io.h> |
eb5e76ff | 26 | #include <linux/of_address.h> |
73a59c1c | 27 | |
a09e64fb RK |
28 | #include <mach/hardware.h> |
29 | #include <mach/at91_pmc.h> | |
30 | #include <mach/cpu.h> | |
73a59c1c | 31 | |
0d781716 JCPV |
32 | #include <asm/proc-fns.h> |
33 | ||
2eeaaa21 | 34 | #include "clock.h" |
5e38efae | 35 | #include "generic.h" |
73a59c1c | 36 | |
b5514952 | 37 | void __iomem *at91_pmc_base; |
55c20c0a | 38 | |
73a59c1c SP |
39 | /* |
40 | * There's a lot more which can be done with clocks, including cpufreq | |
41 | * integration, slow clock mode support (for system suspend), letting | |
42 | * PLLB be used at other rates (on boards that don't need USB), etc. | |
43 | */ | |
44 | ||
2eeaaa21 AV |
45 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
46 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) | |
47 | #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) | |
d481f864 | 48 | #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) |
2eeaaa21 AV |
49 | |
50 | ||
6d0485a9 NF |
51 | /* |
52 | * Chips have some kind of clocks : group them by functionality | |
53 | */ | |
9918ceaf | 54 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ |
11128726 NF |
55 | || cpu_is_at91sam9g45() \ |
56 | || cpu_is_at91sam9x5()) | |
6d0485a9 | 57 | |
2ef9df7a | 58 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
11128726 | 59 | || cpu_is_at91sam9g45() \ |
74db4fb9 HX |
60 | || cpu_is_at91sam9x5() \ |
61 | || cpu_is_at91sam9n12()) | |
6d0485a9 | 62 | |
eab41708 | 63 | #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) |
6d0485a9 | 64 | |
2ef9df7a | 65 | #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ |
11128726 | 66 | || cpu_is_at91sam9g45() \ |
74db4fb9 HX |
67 | || cpu_is_at91sam9x5() \ |
68 | || cpu_is_at91sam9n12())) | |
2ef9df7a | 69 | |
11128726 NF |
70 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ |
71 | || cpu_is_at91sam9x5()) | |
6d0485a9 NF |
72 | |
73 | /* USB host HS & FS */ | |
74 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) | |
75 | ||
76 | /* USB device FS only */ | |
2ef9df7a | 77 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
11128726 NF |
78 | || cpu_is_at91sam9g45() \ |
79 | || cpu_is_at91sam9x5())) | |
80 | ||
81 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ | |
74db4fb9 HX |
82 | || cpu_is_at91sam9x5() \ |
83 | || cpu_is_at91sam9n12()) | |
11128726 NF |
84 | |
85 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ | |
74db4fb9 HX |
86 | || cpu_is_at91sam9x5() \ |
87 | || cpu_is_at91sam9n12()) | |
11128726 | 88 | |
74db4fb9 HX |
89 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ |
90 | || cpu_is_at91sam9n12()) | |
6d0485a9 | 91 | |
2eeaaa21 AV |
92 | static LIST_HEAD(clocks); |
93 | static DEFINE_SPINLOCK(clk_lock); | |
73a59c1c | 94 | |
2eeaaa21 | 95 | static u32 at91_pllb_usb_init; |
73a59c1c SP |
96 | |
97 | /* | |
98 | * Four primary clock sources: two crystal oscillators (32K, main), and | |
99 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at | |
100 | * 48 MHz (unless no USB function clocks are needed). The main clock and | |
101 | * both PLLs are turned off to run in "slow clock mode" (system suspend). | |
102 | */ | |
103 | static struct clk clk32k = { | |
104 | .name = "clk32k", | |
105 | .rate_hz = AT91_SLOW_CLOCK, | |
106 | .users = 1, /* always on */ | |
107 | .id = 0, | |
2eeaaa21 | 108 | .type = CLK_TYPE_PRIMARY, |
73a59c1c SP |
109 | }; |
110 | static struct clk main_clk = { | |
111 | .name = "main", | |
91f8ed83 | 112 | .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ |
73a59c1c | 113 | .id = 1, |
2eeaaa21 | 114 | .type = CLK_TYPE_PRIMARY, |
73a59c1c SP |
115 | }; |
116 | static struct clk plla = { | |
117 | .name = "plla", | |
118 | .parent = &main_clk, | |
91f8ed83 | 119 | .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ |
73a59c1c | 120 | .id = 2, |
2eeaaa21 | 121 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
73a59c1c SP |
122 | }; |
123 | ||
124 | static void pllb_mode(struct clk *clk, int is_on) | |
125 | { | |
126 | u32 value; | |
127 | ||
128 | if (is_on) { | |
129 | is_on = AT91_PMC_LOCKB; | |
130 | value = at91_pllb_usb_init; | |
131 | } else | |
132 | value = 0; | |
133 | ||
2eeaaa21 | 134 | // REVISIT: Add work-around for AT91RM9200 Errata #26 ? |
b5514952 | 135 | at91_pmc_write(AT91_CKGR_PLLBR, value); |
73a59c1c SP |
136 | |
137 | do { | |
138 | cpu_relax(); | |
b5514952 | 139 | } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); |
73a59c1c SP |
140 | } |
141 | ||
142 | static struct clk pllb = { | |
143 | .name = "pllb", | |
144 | .parent = &main_clk, | |
91f8ed83 | 145 | .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ |
73a59c1c SP |
146 | .mode = pllb_mode, |
147 | .id = 3, | |
2eeaaa21 | 148 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
73a59c1c SP |
149 | }; |
150 | ||
151 | static void pmc_sys_mode(struct clk *clk, int is_on) | |
152 | { | |
153 | if (is_on) | |
b5514952 | 154 | at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask); |
73a59c1c | 155 | else |
b5514952 | 156 | at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask); |
73a59c1c SP |
157 | } |
158 | ||
53d71680 SP |
159 | static void pmc_uckr_mode(struct clk *clk, int is_on) |
160 | { | |
b5514952 | 161 | unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR); |
53d71680 SP |
162 | |
163 | if (is_on) { | |
164 | is_on = AT91_PMC_LOCKU; | |
b5514952 | 165 | at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
53d71680 | 166 | } else |
b5514952 | 167 | at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); |
53d71680 SP |
168 | |
169 | do { | |
170 | cpu_relax(); | |
b5514952 | 171 | } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); |
53d71680 SP |
172 | } |
173 | ||
73a59c1c SP |
174 | /* USB function clocks (PLLB must be 48 MHz) */ |
175 | static struct clk udpck = { | |
176 | .name = "udpck", | |
177 | .parent = &pllb, | |
73a59c1c SP |
178 | .mode = pmc_sys_mode, |
179 | }; | |
bd602995 | 180 | struct clk utmi_clk = { |
53d71680 SP |
181 | .name = "utmi_clk", |
182 | .parent = &main_clk, | |
183 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ | |
184 | .mode = pmc_uckr_mode, | |
185 | .type = CLK_TYPE_PLL, | |
186 | }; | |
73a59c1c SP |
187 | static struct clk uhpck = { |
188 | .name = "uhpck", | |
6d0485a9 | 189 | /*.parent = ... we choose parent at runtime */ |
73a59c1c SP |
190 | .mode = pmc_sys_mode, |
191 | }; | |
192 | ||
73a59c1c SP |
193 | |
194 | /* | |
195 | * The master clock is divided from the CPU clock (by 1-4). It's used for | |
196 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more | |
197 | * (e.g baud rate generation). It's sourced from one of the primary clocks. | |
198 | */ | |
bd602995 | 199 | struct clk mck = { |
73a59c1c | 200 | .name = "mck", |
91f8ed83 | 201 | .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ |
73a59c1c SP |
202 | }; |
203 | ||
204 | static void pmc_periph_mode(struct clk *clk, int is_on) | |
205 | { | |
206 | if (is_on) | |
b5514952 | 207 | at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); |
73a59c1c | 208 | else |
b5514952 | 209 | at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); |
73a59c1c SP |
210 | } |
211 | ||
2eeaaa21 AV |
212 | static struct clk __init *at91_css_to_clk(unsigned long css) |
213 | { | |
214 | switch (css) { | |
215 | case AT91_PMC_CSS_SLOW: | |
216 | return &clk32k; | |
217 | case AT91_PMC_CSS_MAIN: | |
218 | return &main_clk; | |
219 | case AT91_PMC_CSS_PLLA: | |
220 | return &plla; | |
221 | case AT91_PMC_CSS_PLLB: | |
6d0485a9 NF |
222 | if (cpu_has_upll()) |
223 | /* CSS_PLLB == CSS_UPLL */ | |
224 | return &utmi_clk; | |
225 | else if (cpu_has_pllb()) | |
226 | return &pllb; | |
11128726 NF |
227 | break; |
228 | /* alternate PMC: can use master clock */ | |
229 | case AT91_PMC_CSS_MASTER: | |
230 | return &mck; | |
2eeaaa21 | 231 | } |
73a59c1c | 232 | |
2eeaaa21 AV |
233 | return NULL; |
234 | } | |
73a59c1c | 235 | |
11128726 NF |
236 | static int pmc_prescaler_divider(u32 reg) |
237 | { | |
238 | if (cpu_has_alt_prescaler()) { | |
239 | return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET); | |
240 | } else { | |
241 | return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET); | |
242 | } | |
243 | } | |
244 | ||
73a59c1c SP |
245 | static void __clk_enable(struct clk *clk) |
246 | { | |
247 | if (clk->parent) | |
248 | __clk_enable(clk->parent); | |
249 | if (clk->users++ == 0 && clk->mode) | |
250 | clk->mode(clk, 1); | |
251 | } | |
252 | ||
253 | int clk_enable(struct clk *clk) | |
254 | { | |
255 | unsigned long flags; | |
256 | ||
257 | spin_lock_irqsave(&clk_lock, flags); | |
258 | __clk_enable(clk); | |
259 | spin_unlock_irqrestore(&clk_lock, flags); | |
260 | return 0; | |
261 | } | |
262 | EXPORT_SYMBOL(clk_enable); | |
263 | ||
264 | static void __clk_disable(struct clk *clk) | |
265 | { | |
266 | BUG_ON(clk->users == 0); | |
267 | if (--clk->users == 0 && clk->mode) | |
268 | clk->mode(clk, 0); | |
269 | if (clk->parent) | |
270 | __clk_disable(clk->parent); | |
271 | } | |
272 | ||
273 | void clk_disable(struct clk *clk) | |
274 | { | |
275 | unsigned long flags; | |
276 | ||
277 | spin_lock_irqsave(&clk_lock, flags); | |
278 | __clk_disable(clk); | |
279 | spin_unlock_irqrestore(&clk_lock, flags); | |
280 | } | |
281 | EXPORT_SYMBOL(clk_disable); | |
282 | ||
283 | unsigned long clk_get_rate(struct clk *clk) | |
284 | { | |
285 | unsigned long flags; | |
286 | unsigned long rate; | |
287 | ||
288 | spin_lock_irqsave(&clk_lock, flags); | |
289 | for (;;) { | |
290 | rate = clk->rate_hz; | |
291 | if (rate || !clk->parent) | |
292 | break; | |
293 | clk = clk->parent; | |
294 | } | |
295 | spin_unlock_irqrestore(&clk_lock, flags); | |
296 | return rate; | |
297 | } | |
298 | EXPORT_SYMBOL(clk_get_rate); | |
299 | ||
300 | /*------------------------------------------------------------------------*/ | |
301 | ||
302 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS | |
303 | ||
304 | /* | |
305 | * For now, only the programmable clocks support reparenting (MCK could | |
306 | * do this too, with care) or rate changing (the PLLs could do this too, | |
307 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get | |
308 | * a better rate match; we don't. | |
309 | */ | |
310 | ||
311 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
312 | { | |
313 | unsigned long flags; | |
314 | unsigned prescale; | |
315 | unsigned long actual; | |
2ef9df7a | 316 | unsigned long prev = ULONG_MAX; |
73a59c1c | 317 | |
2eeaaa21 | 318 | if (!clk_is_programmable(clk)) |
73a59c1c SP |
319 | return -EINVAL; |
320 | spin_lock_irqsave(&clk_lock, flags); | |
321 | ||
322 | actual = clk->parent->rate_hz; | |
323 | for (prescale = 0; prescale < 7; prescale++) { | |
2ef9df7a NF |
324 | if (actual > rate) |
325 | prev = actual; | |
326 | ||
327 | if (actual && actual <= rate) { | |
328 | if ((prev - rate) < (rate - actual)) { | |
329 | actual = prev; | |
330 | prescale--; | |
331 | } | |
73a59c1c | 332 | break; |
2ef9df7a | 333 | } |
73a59c1c SP |
334 | actual >>= 1; |
335 | } | |
336 | ||
337 | spin_unlock_irqrestore(&clk_lock, flags); | |
338 | return (prescale < 7) ? actual : -ENOENT; | |
339 | } | |
340 | EXPORT_SYMBOL(clk_round_rate); | |
341 | ||
342 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
343 | { | |
344 | unsigned long flags; | |
345 | unsigned prescale; | |
11128726 | 346 | unsigned long prescale_offset, css_mask; |
73a59c1c SP |
347 | unsigned long actual; |
348 | ||
2eeaaa21 | 349 | if (!clk_is_programmable(clk)) |
73a59c1c SP |
350 | return -EINVAL; |
351 | if (clk->users) | |
352 | return -EBUSY; | |
11128726 NF |
353 | |
354 | if (cpu_has_alt_prescaler()) { | |
355 | prescale_offset = PMC_ALT_PRES_OFFSET; | |
356 | css_mask = AT91_PMC_ALT_PCKR_CSS; | |
357 | } else { | |
358 | prescale_offset = PMC_PRES_OFFSET; | |
359 | css_mask = AT91_PMC_CSS; | |
360 | } | |
361 | ||
73a59c1c SP |
362 | spin_lock_irqsave(&clk_lock, flags); |
363 | ||
364 | actual = clk->parent->rate_hz; | |
365 | for (prescale = 0; prescale < 7; prescale++) { | |
366 | if (actual && actual <= rate) { | |
367 | u32 pckr; | |
368 | ||
b5514952 | 369 | pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); |
11128726 NF |
370 | pckr &= css_mask; /* keep clock selection */ |
371 | pckr |= prescale << prescale_offset; | |
b5514952 | 372 | at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr); |
73a59c1c SP |
373 | clk->rate_hz = actual; |
374 | break; | |
375 | } | |
376 | actual >>= 1; | |
377 | } | |
378 | ||
379 | spin_unlock_irqrestore(&clk_lock, flags); | |
380 | return (prescale < 7) ? actual : -ENOENT; | |
381 | } | |
382 | EXPORT_SYMBOL(clk_set_rate); | |
383 | ||
384 | struct clk *clk_get_parent(struct clk *clk) | |
385 | { | |
386 | return clk->parent; | |
387 | } | |
388 | EXPORT_SYMBOL(clk_get_parent); | |
389 | ||
390 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
391 | { | |
392 | unsigned long flags; | |
393 | ||
394 | if (clk->users) | |
395 | return -EBUSY; | |
2eeaaa21 | 396 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
73a59c1c | 397 | return -EINVAL; |
2ef9df7a NF |
398 | |
399 | if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB) | |
400 | return -EINVAL; | |
401 | ||
73a59c1c SP |
402 | spin_lock_irqsave(&clk_lock, flags); |
403 | ||
404 | clk->rate_hz = parent->rate_hz; | |
405 | clk->parent = parent; | |
b5514952 | 406 | at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id); |
73a59c1c SP |
407 | |
408 | spin_unlock_irqrestore(&clk_lock, flags); | |
409 | return 0; | |
410 | } | |
411 | EXPORT_SYMBOL(clk_set_parent); | |
412 | ||
6d0485a9 | 413 | /* establish PCK0..PCKN parentage and rate */ |
72e7ae81 | 414 | static void __init init_programmable_clock(struct clk *clk) |
2eeaaa21 AV |
415 | { |
416 | struct clk *parent; | |
417 | u32 pckr; | |
11128726 NF |
418 | unsigned int css_mask; |
419 | ||
420 | if (cpu_has_alt_prescaler()) | |
421 | css_mask = AT91_PMC_ALT_PCKR_CSS; | |
422 | else | |
423 | css_mask = AT91_PMC_CSS; | |
2eeaaa21 | 424 | |
b5514952 | 425 | pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); |
11128726 | 426 | parent = at91_css_to_clk(pckr & css_mask); |
2eeaaa21 | 427 | clk->parent = parent; |
11128726 | 428 | clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); |
2eeaaa21 AV |
429 | } |
430 | ||
73a59c1c SP |
431 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ |
432 | ||
433 | /*------------------------------------------------------------------------*/ | |
434 | ||
435 | #ifdef CONFIG_DEBUG_FS | |
436 | ||
437 | static int at91_clk_show(struct seq_file *s, void *unused) | |
438 | { | |
53d71680 | 439 | u32 scsr, pcsr, uckr = 0, sr; |
2eeaaa21 | 440 | struct clk *clk; |
73a59c1c | 441 | |
b5514952 JCPV |
442 | scsr = at91_pmc_read(AT91_PMC_SCSR); |
443 | pcsr = at91_pmc_read(AT91_PMC_PCSR); | |
444 | sr = at91_pmc_read(AT91_PMC_SR); | |
940192e3 NF |
445 | seq_printf(s, "SCSR = %8x\n", scsr); |
446 | seq_printf(s, "PCSR = %8x\n", pcsr); | |
b5514952 JCPV |
447 | seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); |
448 | seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); | |
449 | seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); | |
6d0485a9 | 450 | if (cpu_has_pllb()) |
b5514952 | 451 | seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR)); |
940192e3 | 452 | if (cpu_has_utmi()) { |
b5514952 | 453 | uckr = at91_pmc_read(AT91_CKGR_UCKR); |
940192e3 NF |
454 | seq_printf(s, "UCKR = %8x\n", uckr); |
455 | } | |
b5514952 | 456 | seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR)); |
6d0485a9 | 457 | if (cpu_has_upll()) |
b5514952 | 458 | seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB)); |
940192e3 | 459 | seq_printf(s, "SR = %8x\n", sr); |
73a59c1c SP |
460 | |
461 | seq_printf(s, "\n"); | |
462 | ||
2eeaaa21 AV |
463 | list_for_each_entry(clk, &clocks, node) { |
464 | char *state; | |
73a59c1c SP |
465 | |
466 | if (clk->mode == pmc_sys_mode) | |
467 | state = (scsr & clk->pmc_mask) ? "on" : "off"; | |
468 | else if (clk->mode == pmc_periph_mode) | |
469 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | |
53d71680 SP |
470 | else if (clk->mode == pmc_uckr_mode) |
471 | state = (uckr & clk->pmc_mask) ? "on" : "off"; | |
73a59c1c SP |
472 | else if (clk->pmc_mask) |
473 | state = (sr & clk->pmc_mask) ? "on" : "off"; | |
474 | else if (clk == &clk32k || clk == &main_clk) | |
475 | state = "on"; | |
476 | else | |
477 | state = ""; | |
478 | ||
69b648a2 | 479 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", |
73a59c1c SP |
480 | clk->name, clk->users, state, clk_get_rate(clk), |
481 | clk->parent ? clk->parent->name : ""); | |
482 | } | |
483 | return 0; | |
484 | } | |
485 | ||
486 | static int at91_clk_open(struct inode *inode, struct file *file) | |
487 | { | |
488 | return single_open(file, at91_clk_show, NULL); | |
489 | } | |
490 | ||
5dfe4c96 | 491 | static const struct file_operations at91_clk_operations = { |
73a59c1c SP |
492 | .open = at91_clk_open, |
493 | .read = seq_read, | |
494 | .llseek = seq_lseek, | |
495 | .release = single_release, | |
496 | }; | |
497 | ||
498 | static int __init at91_clk_debugfs_init(void) | |
499 | { | |
500 | /* /sys/kernel/debug/at91_clk */ | |
501 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | postcore_initcall(at91_clk_debugfs_init); | |
506 | ||
507 | #endif | |
508 | ||
2eeaaa21 AV |
509 | /*------------------------------------------------------------------------*/ |
510 | ||
511 | /* Register a new clock */ | |
bd602995 JCPV |
512 | static void __init at91_clk_add(struct clk *clk) |
513 | { | |
514 | list_add_tail(&clk->node, &clocks); | |
515 | ||
516 | clk->cl.con_id = clk->name; | |
517 | clk->cl.clk = clk; | |
518 | clkdev_add(&clk->cl); | |
519 | } | |
520 | ||
2eeaaa21 AV |
521 | int __init clk_register(struct clk *clk) |
522 | { | |
523 | if (clk_is_peripheral(clk)) { | |
5afddee4 NF |
524 | if (!clk->parent) |
525 | clk->parent = &mck; | |
2eeaaa21 | 526 | clk->mode = pmc_periph_mode; |
2eeaaa21 | 527 | } |
d481f864 AV |
528 | else if (clk_is_sys(clk)) { |
529 | clk->parent = &mck; | |
530 | clk->mode = pmc_sys_mode; | |
d481f864 | 531 | } |
2eeaaa21 AV |
532 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
533 | else if (clk_is_programmable(clk)) { | |
534 | clk->mode = pmc_sys_mode; | |
535 | init_programmable_clock(clk); | |
2eeaaa21 AV |
536 | } |
537 | #endif | |
538 | ||
bd602995 JCPV |
539 | at91_clk_add(clk); |
540 | ||
2eeaaa21 AV |
541 | return 0; |
542 | } | |
543 | ||
73a59c1c SP |
544 | /*------------------------------------------------------------------------*/ |
545 | ||
546 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) | |
547 | { | |
548 | unsigned mul, div; | |
549 | ||
550 | div = reg & 0xff; | |
551 | mul = (reg >> 16) & 0x7ff; | |
552 | if (div && mul) { | |
553 | freq /= div; | |
554 | freq *= mul + 1; | |
555 | } else | |
556 | freq = 0; | |
69b648a2 | 557 | |
73a59c1c SP |
558 | return freq; |
559 | } | |
560 | ||
69b648a2 AV |
561 | static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) |
562 | { | |
563 | if (pll == &pllb && (reg & AT91_PMC_USB96M)) | |
564 | return freq / 2; | |
565 | else | |
566 | return freq; | |
567 | } | |
568 | ||
73a59c1c SP |
569 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) |
570 | { | |
571 | unsigned i, div = 0, mul = 0, diff = 1 << 30; | |
572 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; | |
573 | ||
574 | /* PLL output max 240 MHz (or 180 MHz per errata) */ | |
575 | if (out_freq > 240000000) | |
576 | goto fail; | |
577 | ||
578 | for (i = 1; i < 256; i++) { | |
579 | int diff1; | |
580 | unsigned input, mul1; | |
581 | ||
582 | /* | |
583 | * PLL input between 1MHz and 32MHz per spec, but lower | |
584 | * frequences seem necessary in some cases so allow 100K. | |
61352667 | 585 | * Warning: some newer products need 2MHz min. |
73a59c1c SP |
586 | */ |
587 | input = main_freq / i; | |
61352667 | 588 | if (cpu_is_at91sam9g20() && input < 2000000) |
589 | continue; | |
73a59c1c SP |
590 | if (input < 100000) |
591 | continue; | |
592 | if (input > 32000000) | |
593 | continue; | |
594 | ||
595 | mul1 = out_freq / input; | |
61352667 | 596 | if (cpu_is_at91sam9g20() && mul > 63) |
597 | continue; | |
73a59c1c SP |
598 | if (mul1 > 2048) |
599 | continue; | |
600 | if (mul1 < 2) | |
601 | goto fail; | |
602 | ||
603 | diff1 = out_freq - input * mul1; | |
604 | if (diff1 < 0) | |
605 | diff1 = -diff1; | |
606 | if (diff > diff1) { | |
607 | diff = diff1; | |
608 | div = i; | |
609 | mul = mul1; | |
610 | if (diff == 0) | |
611 | break; | |
612 | } | |
613 | } | |
614 | if (i == 256 && diff > (out_freq >> 5)) | |
615 | goto fail; | |
616 | return ret | ((mul - 1) << 16) | div; | |
617 | fail: | |
618 | return 0; | |
619 | } | |
620 | ||
2eeaaa21 AV |
621 | static struct clk *const standard_pmc_clocks[] __initdata = { |
622 | /* four primary clocks */ | |
623 | &clk32k, | |
624 | &main_clk, | |
625 | &plla, | |
2eeaaa21 AV |
626 | |
627 | /* MCK */ | |
628 | &mck | |
629 | }; | |
630 | ||
6d0485a9 NF |
631 | /* PLLB generated USB full speed clock init */ |
632 | static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) | |
633 | { | |
634 | /* | |
635 | * USB clock init: choose 48 MHz PLLB value, | |
636 | * disable 48MHz clock during usb peripheral suspend. | |
637 | * | |
638 | * REVISIT: assumes MCK doesn't derive from PLLB! | |
639 | */ | |
640 | uhpck.parent = &pllb; | |
641 | ||
642 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; | |
643 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); | |
644 | if (cpu_is_at91rm9200()) { | |
645 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; | |
646 | udpck.pmc_mask = AT91RM9200_PMC_UDP; | |
b5514952 | 647 | at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
eab41708 NF |
648 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || |
649 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || | |
7a2207a0 | 650 | cpu_is_at91sam9g10()) { |
6d0485a9 NF |
651 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
652 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; | |
6d0485a9 | 653 | } |
b5514952 | 654 | at91_pmc_write(AT91_CKGR_PLLBR, 0); |
6d0485a9 NF |
655 | |
656 | udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); | |
657 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); | |
658 | } | |
659 | ||
660 | /* UPLL generated USB full speed clock init */ | |
661 | static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) | |
662 | { | |
663 | /* | |
664 | * USB clock init: choose 480 MHz from UPLL, | |
665 | */ | |
666 | unsigned int usbr = AT91_PMC_USBS_UPLL; | |
667 | ||
668 | /* Setup divider by 10 to reach 48 MHz */ | |
669 | usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; | |
670 | ||
b5514952 | 671 | at91_pmc_write(AT91_PMC_USB, usbr); |
6d0485a9 NF |
672 | |
673 | /* Now set uhpck values */ | |
674 | uhpck.parent = &utmi_clk; | |
675 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; | |
8251544f | 676 | uhpck.rate_hz = utmi_clk.rate_hz; |
b5514952 | 677 | uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); |
6d0485a9 NF |
678 | } |
679 | ||
eb5e76ff | 680 | static int __init at91_pmc_init(unsigned long main_clock) |
73a59c1c SP |
681 | { |
682 | unsigned tmp, freq, mckr; | |
2eeaaa21 | 683 | int i; |
2ef9df7a | 684 | int pll_overclock = false; |
73a59c1c SP |
685 | |
686 | /* | |
687 | * When the bootloader initialized the main oscillator correctly, | |
688 | * there's no problem using the cycle counter. But if it didn't, | |
689 | * or when using oscillator bypass mode, we must be told the speed | |
690 | * of the main clock. | |
691 | */ | |
692 | if (!main_clock) { | |
693 | do { | |
b5514952 | 694 | tmp = at91_pmc_read(AT91_CKGR_MCFR); |
69b648a2 AV |
695 | } while (!(tmp & AT91_PMC_MAINRDY)); |
696 | main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); | |
73a59c1c SP |
697 | } |
698 | main_clk.rate_hz = main_clock; | |
699 | ||
700 | /* report if PLLA is more than mildly overclocked */ | |
b5514952 | 701 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); |
2ef9df7a NF |
702 | if (cpu_has_300M_plla()) { |
703 | if (plla.rate_hz > 300000000) | |
704 | pll_overclock = true; | |
705 | } else if (cpu_has_800M_plla()) { | |
706 | if (plla.rate_hz > 800000000) | |
707 | pll_overclock = true; | |
708 | } else { | |
709 | if (plla.rate_hz > 209000000) | |
710 | pll_overclock = true; | |
711 | } | |
712 | if (pll_overclock) | |
73a59c1c SP |
713 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
714 | ||
11128726 | 715 | if (cpu_has_plladiv2()) { |
b5514952 | 716 | mckr = at91_pmc_read(AT91_PMC_MCKR); |
2ef9df7a NF |
717 | plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ |
718 | } | |
6d0485a9 | 719 | |
2ef9df7a | 720 | if (!cpu_has_pllb() && cpu_has_upll()) { |
6d0485a9 NF |
721 | /* setup UTMI clock as the fourth primary clock |
722 | * (instead of pllb) */ | |
723 | utmi_clk.type |= CLK_TYPE_PRIMARY; | |
724 | utmi_clk.id = 3; | |
d481f864 | 725 | } |
73a59c1c | 726 | |
69b648a2 | 727 | |
53d71680 SP |
728 | /* |
729 | * USB HS clock init | |
730 | */ | |
5e38efae | 731 | if (cpu_has_utmi()) { |
53d71680 SP |
732 | /* |
733 | * multiplier is hard-wired to 40 | |
734 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) | |
735 | */ | |
736 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; | |
11128726 NF |
737 | |
738 | /* UTMI bias and PLL are managed at the same time */ | |
739 | if (cpu_has_upll()) | |
740 | utmi_clk.pmc_mask |= AT91_PMC_BIASEN; | |
5e38efae | 741 | } |
6d0485a9 NF |
742 | |
743 | /* | |
744 | * USB FS clock init | |
745 | */ | |
746 | if (cpu_has_pllb()) | |
747 | at91_pllb_usbfs_clock_init(main_clock); | |
748 | if (cpu_has_upll()) | |
749 | /* assumes that we choose UPLL for USB and not PLLA */ | |
750 | at91_upll_usbfs_clock_init(main_clock); | |
53d71680 | 751 | |
73a59c1c SP |
752 | /* |
753 | * MCK and CPU derive from one of those primary clocks. | |
754 | * For now, assume this parentage won't change. | |
755 | */ | |
b5514952 | 756 | mckr = at91_pmc_read(AT91_PMC_MCKR); |
2eeaaa21 | 757 | mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); |
73a59c1c | 758 | freq = mck.parent->rate_hz; |
11128726 | 759 | freq /= pmc_prescaler_divider(mckr); /* prescale */ |
6d0485a9 | 760 | if (cpu_is_at91rm9200()) { |
a95c729b | 761 | mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
6d0485a9 | 762 | } else if (cpu_is_at91sam9g20()) { |
61352667 | 763 | mck.rate_hz = (mckr & AT91_PMC_MDIV) ? |
764 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ | |
765 | if (mckr & AT91_PMC_PDIV) | |
766 | freq /= 2; /* processor clock division */ | |
11128726 | 767 | } else if (cpu_has_mdiv3()) { |
2ef9df7a NF |
768 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? |
769 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ | |
6d0485a9 | 770 | } else { |
5e38efae | 771 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
6d0485a9 | 772 | } |
73a59c1c | 773 | |
11128726 NF |
774 | if (cpu_has_alt_prescaler()) { |
775 | /* Programmable clocks can use MCK */ | |
776 | mck.type |= CLK_TYPE_PRIMARY; | |
777 | mck.id = 4; | |
778 | } | |
779 | ||
2eeaaa21 AV |
780 | /* Register the PMC's standard clocks */ |
781 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) | |
bd602995 | 782 | at91_clk_add(standard_pmc_clocks[i]); |
2eeaaa21 | 783 | |
6d0485a9 | 784 | if (cpu_has_pllb()) |
bd602995 | 785 | at91_clk_add(&pllb); |
6d0485a9 NF |
786 | |
787 | if (cpu_has_uhp()) | |
bd602995 | 788 | at91_clk_add(&uhpck); |
6d0485a9 NF |
789 | |
790 | if (cpu_has_udpfs()) | |
bd602995 | 791 | at91_clk_add(&udpck); |
6d0485a9 NF |
792 | |
793 | if (cpu_has_utmi()) | |
bd602995 | 794 | at91_clk_add(&utmi_clk); |
53d71680 | 795 | |
91f8ed83 AV |
796 | /* MCK and CPU clock are "always on" */ |
797 | clk_enable(&mck); | |
798 | ||
73a59c1c SP |
799 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", |
800 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, | |
801 | (unsigned) main_clock / 1000000, | |
802 | ((unsigned) main_clock % 1000000) / 1000); | |
803 | ||
c9b75d13 AV |
804 | return 0; |
805 | } | |
806 | ||
eb5e76ff JCPV |
807 | #if defined(CONFIG_OF) |
808 | static struct of_device_id pmc_ids[] = { | |
809 | { .compatible = "atmel,at91rm9200-pmc" }, | |
810 | { /*sentinel*/ } | |
811 | }; | |
812 | ||
813 | static struct of_device_id osc_ids[] = { | |
814 | { .compatible = "atmel,osc" }, | |
815 | { /*sentinel*/ } | |
816 | }; | |
817 | ||
818 | int __init at91_dt_clock_init(void) | |
819 | { | |
820 | struct device_node *np; | |
821 | u32 main_clock = 0; | |
822 | ||
823 | np = of_find_matching_node(NULL, pmc_ids); | |
824 | if (!np) | |
825 | panic("unable to find compatible pmc node in dtb\n"); | |
826 | ||
827 | at91_pmc_base = of_iomap(np, 0); | |
828 | if (!at91_pmc_base) | |
829 | panic("unable to map pmc cpu registers\n"); | |
830 | ||
831 | of_node_put(np); | |
832 | ||
833 | /* retrieve the freqency of fixed clocks from device tree */ | |
834 | np = of_find_matching_node(NULL, osc_ids); | |
835 | if (np) { | |
836 | u32 rate; | |
837 | if (!of_property_read_u32(np, "clock-frequency", &rate)) | |
838 | main_clock = rate; | |
839 | } | |
840 | ||
841 | of_node_put(np); | |
842 | ||
843 | return at91_pmc_init(main_clock); | |
844 | } | |
845 | #endif | |
846 | ||
847 | int __init at91_clock_init(unsigned long main_clock) | |
848 | { | |
849 | at91_pmc_base = ioremap(AT91_PMC, 256); | |
850 | if (!at91_pmc_base) | |
851 | panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC); | |
852 | ||
853 | return at91_pmc_init(main_clock); | |
854 | } | |
855 | ||
c9b75d13 AV |
856 | /* |
857 | * Several unused clocks may be active. Turn them off. | |
858 | */ | |
859 | static int __init at91_clock_reset(void) | |
860 | { | |
861 | unsigned long pcdr = 0; | |
862 | unsigned long scdr = 0; | |
863 | struct clk *clk; | |
864 | ||
865 | list_for_each_entry(clk, &clocks, node) { | |
866 | if (clk->users > 0) | |
867 | continue; | |
868 | ||
869 | if (clk->mode == pmc_periph_mode) | |
870 | pcdr |= clk->pmc_mask; | |
871 | ||
872 | if (clk->mode == pmc_sys_mode) | |
873 | scdr |= clk->pmc_mask; | |
874 | ||
875 | pr_debug("Clocks: disable unused %s\n", clk->name); | |
876 | } | |
91f8ed83 | 877 | |
b5514952 JCPV |
878 | at91_pmc_write(AT91_PMC_PCDR, pcdr); |
879 | at91_pmc_write(AT91_PMC_SCDR, scdr); | |
73a59c1c SP |
880 | |
881 | return 0; | |
882 | } | |
c9b75d13 | 883 | late_initcall(at91_clock_reset); |
0d781716 JCPV |
884 | |
885 | void at91sam9_idle(void) | |
886 | { | |
b5514952 | 887 | at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); |
0d781716 JCPV |
888 | cpu_do_idle(); |
889 | } |