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3ad0920d SB |
1 | /* |
2 | * linux/arch/arm/mach-at91/board-yl-9200.c | |
3 | * | |
e3ba22db AV |
4 | * Adapted from various board files in arch/arm/mach-at91 |
5 | * | |
6 | * Modifications for YL-9200 platform: | |
7 | * Copyright (C) 2007 S. Birtles | |
3ad0920d SB |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <linux/types.h> | |
2f8163ba | 25 | #include <linux/gpio.h> |
3ad0920d SB |
26 | #include <linux/init.h> |
27 | #include <linux/mm.h> | |
28 | #include <linux/module.h> | |
e3ba22db | 29 | #include <linux/dma-mapping.h> |
3ad0920d SB |
30 | #include <linux/platform_device.h> |
31 | #include <linux/spi/spi.h> | |
3ad0920d SB |
32 | #include <linux/spi/ads7846.h> |
33 | #include <linux/mtd/physmap.h> | |
e3ba22db AV |
34 | #include <linux/gpio_keys.h> |
35 | #include <linux/input.h> | |
3ad0920d | 36 | |
3ad0920d SB |
37 | #include <asm/setup.h> |
38 | #include <asm/mach-types.h> | |
39 | #include <asm/irq.h> | |
40 | ||
41 | #include <asm/mach/arch.h> | |
42 | #include <asm/mach/map.h> | |
43 | #include <asm/mach/irq.h> | |
44 | ||
e505240b | 45 | #include <mach/hardware.h> |
a09e64fb | 46 | #include <mach/board.h> |
a09e64fb | 47 | #include <mach/at91rm9200_mc.h> |
e57556e3 | 48 | #include <mach/cpu.h> |
3ad0920d SB |
49 | |
50 | #include "generic.h" | |
3ad0920d | 51 | |
3ad0920d | 52 | |
1b021a3b | 53 | static void __init yl9200_init_early(void) |
e3ba22db | 54 | { |
e57556e3 JCPV |
55 | /* Set cpu type: PQFP */ |
56 | at91rm9200_set_type(ARCH_REVISON_9200_PQFP); | |
57 | ||
e3ba22db | 58 | /* Initialize processor: 18.432 MHz crystal */ |
21d08b9d | 59 | at91_initialize(18432000); |
3ad0920d | 60 | |
e3ba22db AV |
61 | /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ |
62 | at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); | |
3ad0920d | 63 | |
e3ba22db AV |
64 | /* DBGU on ttyS0. (Rx & Tx only) */ |
65 | at91_register_uart(0, 0, 0); | |
3ad0920d | 66 | |
e3ba22db AV |
67 | /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ |
68 | at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS | |
69 | | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD | |
70 | | ATMEL_UART_RI); | |
3ad0920d | 71 | |
e3ba22db AV |
72 | /* USART0 on ttyS2. (Rx & Tx only to JP3) */ |
73 | at91_register_uart(AT91RM9200_ID_US0, 2, 0); | |
3ad0920d | 74 | |
e3ba22db AV |
75 | /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ |
76 | at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); | |
77 | ||
78 | /* set serial console to ttyS0 (ie, DBGU) */ | |
79 | at91_set_serial_console(0); | |
3ad0920d SB |
80 | } |
81 | ||
e3ba22db AV |
82 | /* |
83 | * LEDs | |
84 | */ | |
85 | static struct gpio_led yl9200_leds[] = { | |
86 | { /* D2 */ | |
87 | .name = "led2", | |
88 | .gpio = AT91_PIN_PB17, | |
89 | .active_low = 1, | |
90 | .default_trigger = "timer", | |
91 | }, | |
92 | { /* D3 */ | |
93 | .name = "led3", | |
94 | .gpio = AT91_PIN_PB16, | |
95 | .active_low = 1, | |
96 | .default_trigger = "heartbeat", | |
97 | }, | |
98 | { /* D4 */ | |
99 | .name = "led4", | |
100 | .gpio = AT91_PIN_PB15, | |
101 | .active_low = 1, | |
102 | }, | |
103 | { /* D5 */ | |
104 | .name = "led5", | |
105 | .gpio = AT91_PIN_PB8, | |
106 | .active_low = 1, | |
107 | } | |
3ad0920d SB |
108 | }; |
109 | ||
3ad0920d | 110 | /* |
e3ba22db AV |
111 | * Ethernet |
112 | */ | |
113 | static struct at91_eth_data __initdata yl9200_eth_data = { | |
114 | .phy_irq_pin = AT91_PIN_PB28, | |
115 | .is_rmii = 1, | |
3ad0920d | 116 | }; |
3ad0920d | 117 | |
e3ba22db AV |
118 | /* |
119 | * USB Host | |
120 | */ | |
121 | static struct at91_usbh_data __initdata yl9200_usbh_data = { | |
122 | .ports = 1, /* PQFP version of AT91RM9200 */ | |
3ad0920d SB |
123 | }; |
124 | ||
e3ba22db AV |
125 | /* |
126 | * USB Device | |
127 | */ | |
128 | static struct at91_udc_data __initdata yl9200_udc_data = { | |
129 | .pullup_pin = AT91_PIN_PC4, | |
130 | .vbus_pin = AT91_PIN_PC5, | |
131 | .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */ | |
3ad0920d | 132 | |
3ad0920d | 133 | }; |
3ad0920d | 134 | |
e3ba22db AV |
135 | /* |
136 | * MMC | |
137 | */ | |
138 | static struct at91_mmc_data __initdata yl9200_mmc_data = { | |
139 | .det_pin = AT91_PIN_PB9, | |
140 | // .wp_pin = ... not connected | |
141 | .wire4 = 1, | |
3ad0920d SB |
142 | }; |
143 | ||
e3ba22db AV |
144 | /* |
145 | * NAND Flash | |
146 | */ | |
147 | static struct mtd_partition __initdata yl9200_nand_partition[] = { | |
3ad0920d SB |
148 | { |
149 | .name = "AT91 NAND partition 1, boot", | |
150 | .offset = 0, | |
e505240b | 151 | .size = SZ_256K |
3ad0920d SB |
152 | }, |
153 | { | |
154 | .name = "AT91 NAND partition 2, kernel", | |
e505240b AV |
155 | .offset = MTDPART_OFS_NXTBLK, |
156 | .size = (2 * SZ_1M) - SZ_256K | |
3ad0920d SB |
157 | }, |
158 | { | |
159 | .name = "AT91 NAND partition 3, filesystem", | |
e505240b | 160 | .offset = MTDPART_OFS_NXTBLK, |
3ad0920d SB |
161 | .size = 14 * SZ_1M |
162 | }, | |
163 | { | |
164 | .name = "AT91 NAND partition 4, storage", | |
e505240b AV |
165 | .offset = MTDPART_OFS_NXTBLK, |
166 | .size = SZ_16M | |
3ad0920d SB |
167 | }, |
168 | { | |
169 | .name = "AT91 NAND partition 5, ext-fs", | |
e505240b AV |
170 | .offset = MTDPART_OFS_NXTBLK, |
171 | .size = SZ_32M | |
e3ba22db | 172 | } |
3ad0920d SB |
173 | }; |
174 | ||
ff877ea8 | 175 | static struct atmel_nand_data __initdata yl9200_nand_data = { |
e3ba22db AV |
176 | .ale = 6, |
177 | .cle = 7, | |
178 | // .det_pin = ... not connected | |
179 | .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */ | |
180 | .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */ | |
1754aab9 DES |
181 | .parts = yl9200_nand_partition, |
182 | .num_parts = ARRAY_SIZE(yl9200_nand_partition), | |
3ad0920d SB |
183 | }; |
184 | ||
3ad0920d | 185 | /* |
e3ba22db AV |
186 | * NOR Flash |
187 | */ | |
188 | #define YL9200_FLASH_BASE AT91_CHIPSELECT_0 | |
e505240b | 189 | #define YL9200_FLASH_SIZE SZ_16M |
3ad0920d | 190 | |
e3ba22db AV |
191 | static struct mtd_partition yl9200_flash_partitions[] = { |
192 | { | |
193 | .name = "Bootloader", | |
e3ba22db | 194 | .offset = 0, |
e505240b | 195 | .size = SZ_256K, |
e3ba22db AV |
196 | .mask_flags = MTD_WRITEABLE, /* force read-only */ |
197 | }, | |
3ad0920d | 198 | { |
e3ba22db | 199 | .name = "Kernel", |
e505240b AV |
200 | .offset = MTDPART_OFS_NXTBLK, |
201 | .size = (2 * SZ_1M) - SZ_256K | |
e3ba22db AV |
202 | }, |
203 | { | |
204 | .name = "Filesystem", | |
e505240b AV |
205 | .offset = MTDPART_OFS_NXTBLK, |
206 | .size = MTDPART_SIZ_FULL | |
3ad0920d | 207 | } |
3ad0920d SB |
208 | }; |
209 | ||
e3ba22db AV |
210 | static struct physmap_flash_data yl9200_flash_data = { |
211 | .width = 2, | |
212 | .parts = yl9200_flash_partitions, | |
213 | .nr_parts = ARRAY_SIZE(yl9200_flash_partitions), | |
3ad0920d SB |
214 | }; |
215 | ||
e3ba22db AV |
216 | static struct resource yl9200_flash_resources[] = { |
217 | { | |
218 | .start = YL9200_FLASH_BASE, | |
219 | .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1, | |
220 | .flags = IORESOURCE_MEM, | |
3ad0920d SB |
221 | } |
222 | }; | |
223 | ||
e3ba22db | 224 | static struct platform_device yl9200_flash = { |
3ad0920d SB |
225 | .name = "physmap-flash", |
226 | .id = 0, | |
227 | .dev = { | |
e3ba22db | 228 | .platform_data = &yl9200_flash_data, |
3ad0920d | 229 | }, |
e3ba22db AV |
230 | .resource = yl9200_flash_resources, |
231 | .num_resources = ARRAY_SIZE(yl9200_flash_resources), | |
3ad0920d SB |
232 | }; |
233 | ||
e3ba22db AV |
234 | /* |
235 | * I2C (TWI) | |
236 | */ | |
237 | static struct i2c_board_info __initdata yl9200_i2c_devices[] = { | |
238 | { /* EEPROM */ | |
239 | I2C_BOARD_INFO("24c128", 0x50), | |
3ad0920d SB |
240 | } |
241 | }; | |
242 | ||
e3ba22db | 243 | /* |
3ad0920d | 244 | * GPIO Buttons |
e3ba22db | 245 | */ |
3ad0920d | 246 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
e3ba22db | 247 | static struct gpio_keys_button yl9200_buttons[] = { |
3ad0920d SB |
248 | { |
249 | .gpio = AT91_PIN_PA24, | |
e3ba22db | 250 | .code = BTN_2, |
3ad0920d SB |
251 | .desc = "SW2", |
252 | .active_low = 1, | |
253 | .wakeup = 1, | |
254 | }, | |
255 | { | |
256 | .gpio = AT91_PIN_PB1, | |
e3ba22db | 257 | .code = BTN_3, |
3ad0920d SB |
258 | .desc = "SW3", |
259 | .active_low = 1, | |
260 | .wakeup = 1, | |
261 | }, | |
262 | { | |
263 | .gpio = AT91_PIN_PB2, | |
e3ba22db | 264 | .code = BTN_4, |
3ad0920d SB |
265 | .desc = "SW4", |
266 | .active_low = 1, | |
267 | .wakeup = 1, | |
268 | }, | |
269 | { | |
270 | .gpio = AT91_PIN_PB6, | |
e3ba22db | 271 | .code = BTN_5, |
3ad0920d SB |
272 | .desc = "SW5", |
273 | .active_low = 1, | |
274 | .wakeup = 1, | |
e3ba22db | 275 | } |
3ad0920d SB |
276 | }; |
277 | ||
e3ba22db AV |
278 | static struct gpio_keys_platform_data yl9200_button_data = { |
279 | .buttons = yl9200_buttons, | |
280 | .nbuttons = ARRAY_SIZE(yl9200_buttons), | |
3ad0920d SB |
281 | }; |
282 | ||
e3ba22db | 283 | static struct platform_device yl9200_button_device = { |
3ad0920d SB |
284 | .name = "gpio-keys", |
285 | .id = -1, | |
286 | .num_resources = 0, | |
287 | .dev = { | |
e3ba22db | 288 | .platform_data = &yl9200_button_data, |
3ad0920d SB |
289 | } |
290 | }; | |
291 | ||
e3ba22db | 292 | static void __init yl9200_add_device_buttons(void) |
3ad0920d | 293 | { |
e3ba22db | 294 | at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */ |
3ad0920d | 295 | at91_set_deglitch(AT91_PIN_PA24, 1); |
e3ba22db | 296 | at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */ |
3ad0920d | 297 | at91_set_deglitch(AT91_PIN_PB1, 1); |
e3ba22db | 298 | at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */ |
3ad0920d | 299 | at91_set_deglitch(AT91_PIN_PB2, 1); |
e3ba22db | 300 | at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */ |
3ad0920d SB |
301 | at91_set_deglitch(AT91_PIN_PB6, 1); |
302 | ||
e3ba22db AV |
303 | /* Enable buttons (Sheet 5) */ |
304 | at91_set_gpio_output(AT91_PIN_PB7, 1); | |
305 | ||
306 | platform_device_register(&yl9200_button_device); | |
307 | } | |
308 | #else | |
309 | static void __init yl9200_add_device_buttons(void) {} | |
310 | #endif | |
311 | ||
312 | /* | |
313 | * Touchscreen | |
314 | */ | |
315 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | |
316 | static int ads7843_pendown_state(void) | |
317 | { | |
318 | return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */ | |
319 | } | |
320 | ||
321 | static struct ads7846_platform_data ads_info = { | |
322 | .model = 7843, | |
323 | .x_min = 150, | |
324 | .x_max = 3830, | |
325 | .y_min = 190, | |
326 | .y_max = 3830, | |
327 | .vref_delay_usecs = 100, | |
328 | ||
329 | /* For a 8" touch-screen */ | |
330 | // .x_plate_ohms = 603, | |
331 | // .y_plate_ohms = 332, | |
332 | ||
333 | /* For a 10.4" touch-screen */ | |
334 | // .x_plate_ohms = 611, | |
335 | // .y_plate_ohms = 325, | |
336 | ||
337 | .x_plate_ohms = 576, | |
338 | .y_plate_ohms = 366, | |
339 | ||
340 | .pressure_max = 15000, /* generally nonsense on the 7843 */ | |
341 | .debounce_max = 1, | |
342 | .debounce_rep = 0, | |
343 | .debounce_tol = (~0), | |
344 | .get_pendown_state = ads7843_pendown_state, | |
345 | }; | |
3ad0920d | 346 | |
e3ba22db AV |
347 | static void __init yl9200_add_device_ts(void) |
348 | { | |
349 | at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */ | |
350 | at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */ | |
3ad0920d SB |
351 | } |
352 | #else | |
e3ba22db AV |
353 | static void __init yl9200_add_device_ts(void) {} |
354 | #endif | |
355 | ||
356 | /* | |
357 | * SPI devices | |
358 | */ | |
359 | static struct spi_board_info yl9200_spi_devices[] = { | |
360 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | |
361 | { /* Touchscreen */ | |
362 | .modalias = "ads7846", | |
363 | .chip_select = 0, | |
364 | .max_speed_hz = 5000 * 26, | |
365 | .platform_data = &ads_info, | |
366 | .irq = AT91_PIN_PB11, | |
367 | }, | |
3ad0920d | 368 | #endif |
e3ba22db AV |
369 | { /* CAN */ |
370 | .modalias = "mcp2510", | |
371 | .chip_select = 1, | |
372 | .max_speed_hz = 25000 * 26, | |
373 | .irq = AT91_PIN_PC0, | |
374 | } | |
375 | }; | |
3ad0920d | 376 | |
e3ba22db AV |
377 | /* |
378 | * LCD / VGA | |
379 | * | |
380 | * EPSON S1D13806 FB (discontinued chip) | |
381 | * EPSON S1D13506 FB | |
382 | */ | |
3b24f095 | 383 | #if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE) |
3ad0920d SB |
384 | #include <video/s1d13xxxfb.h> |
385 | ||
3ad0920d | 386 | |
b2eb5309 | 387 | static void yl9200_init_video(void) |
3ad0920d | 388 | { |
e3ba22db AV |
389 | /* NWAIT Signal */ |
390 | at91_set_A_periph(AT91_PIN_PC6, 0); | |
3ad0920d | 391 | |
e3ba22db AV |
392 | /* Initialization of the Static Memory Controller for Chip Select 2 */ |
393 | at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */ | |
394 | | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */ | |
395 | | AT91_SMC_TDF_(0x100) /* float time */ | |
396 | ); | |
3ad0920d SB |
397 | } |
398 | ||
e3ba22db | 399 | static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] = |
3ad0920d | 400 | { |
e3ba22db AV |
401 | {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/ |
402 | {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ | |
403 | {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/ | |
404 | {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/ | |
405 | {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/ | |
406 | {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/ | |
407 | {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/ | |
408 | {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/ | |
409 | {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/ | |
410 | {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/ | |
411 | {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/ | |
412 | {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/ | |
413 | {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/ | |
414 | {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/ | |
415 | {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/ | |
416 | {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/ | |
417 | {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/ | |
418 | {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/ | |
419 | {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/ | |
420 | {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/ | |
421 | {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/ | |
422 | {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/ | |
423 | {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/ | |
424 | {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/ | |
425 | {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/ | |
426 | {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/ | |
427 | {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/ | |
428 | {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/ | |
429 | {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/ | |
430 | {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/ | |
431 | {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/ | |
432 | {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/ | |
433 | {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/ | |
434 | {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/ | |
435 | {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/ | |
436 | {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/ | |
437 | {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/ | |
438 | {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/ | |
439 | {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/ | |
440 | {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/ | |
441 | {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/ | |
442 | {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/ | |
443 | {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/ | |
444 | {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */ | |
445 | {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/ | |
446 | {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/ | |
447 | {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/ | |
448 | {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/ | |
449 | {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/ | |
450 | {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/ | |
451 | {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/ | |
452 | {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/ | |
453 | {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/ | |
454 | {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/ | |
455 | {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/ | |
456 | {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/ | |
457 | {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/ | |
458 | {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/ | |
459 | {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/ | |
460 | {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/ | |
461 | {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/ | |
462 | {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/ | |
463 | {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/ | |
464 | {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/ | |
465 | {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/ | |
466 | {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/ | |
467 | {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/ | |
468 | {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/ | |
469 | {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/ | |
470 | {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/ | |
471 | {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/ | |
472 | {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/ | |
473 | {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/ | |
474 | {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/ | |
475 | {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/ | |
476 | {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/ | |
477 | {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/ | |
478 | {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/ | |
479 | {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/ | |
480 | {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/ | |
481 | {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/ | |
482 | {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/ | |
483 | {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/ | |
484 | {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/ | |
485 | {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/ | |
486 | {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/ | |
487 | {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/ | |
488 | {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/ | |
489 | {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/ | |
490 | {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/ | |
491 | {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/ | |
492 | {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/ | |
493 | {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/ | |
494 | {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/ | |
495 | {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/ | |
496 | {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/ | |
497 | {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/ | |
498 | {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/ | |
499 | {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/ | |
500 | {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/ | |
501 | {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/ | |
502 | {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/ | |
503 | {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/ | |
504 | {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/ | |
505 | {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ | |
3ad0920d SB |
506 | }; |
507 | ||
e3ba22db AV |
508 | static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = { |
509 | .initregs = yl9200_s1dfb_initregs, | |
510 | .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs), | |
511 | .platform_init_video = yl9200_init_video, | |
3ad0920d SB |
512 | }; |
513 | ||
e505240b AV |
514 | #define YL9200_FB_REG_BASE AT91_CHIPSELECT_7 |
515 | #define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M | |
516 | #define YL9200_FB_VMEM_SIZE SZ_2M | |
517 | ||
e3ba22db | 518 | static struct resource yl9200_s1dfb_resource[] = { |
3ad0920d | 519 | [0] = { /* video mem */ |
e3ba22db | 520 | .name = "s1d13xxxfb memory", |
e505240b AV |
521 | .start = YL9200_FB_VMEM_BASE, |
522 | .end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1, | |
e3ba22db | 523 | .flags = IORESOURCE_MEM, |
3ad0920d SB |
524 | }, |
525 | [1] = { /* video registers */ | |
e3ba22db | 526 | .name = "s1d13xxxfb registers", |
e505240b AV |
527 | .start = YL9200_FB_REG_BASE, |
528 | .end = YL9200_FB_REG_BASE + SZ_512 -1, | |
e3ba22db | 529 | .flags = IORESOURCE_MEM, |
3ad0920d SB |
530 | }, |
531 | }; | |
532 | ||
e505240b AV |
533 | static u64 s1dfb_dmamask = DMA_BIT_MASK(32); |
534 | ||
e3ba22db AV |
535 | static struct platform_device yl9200_s1dfb_device = { |
536 | .name = "s1d13806fb", | |
537 | .id = -1, | |
538 | .dev = { | |
3ad0920d | 539 | .dma_mask = &s1dfb_dmamask, |
e3ba22db AV |
540 | .coherent_dma_mask = DMA_BIT_MASK(32), |
541 | .platform_data = &yl9200_s1dfb_pdata, | |
3ad0920d | 542 | }, |
e3ba22db AV |
543 | .resource = yl9200_s1dfb_resource, |
544 | .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource), | |
3ad0920d SB |
545 | }; |
546 | ||
e3ba22db | 547 | void __init yl9200_add_device_video(void) |
3ad0920d | 548 | { |
e3ba22db | 549 | platform_device_register(&yl9200_s1dfb_device); |
3ad0920d SB |
550 | } |
551 | #else | |
e3ba22db | 552 | void __init yl9200_add_device_video(void) {} |
3ad0920d SB |
553 | #endif |
554 | ||
e3ba22db AV |
555 | |
556 | static void __init yl9200_board_init(void) | |
3ad0920d SB |
557 | { |
558 | /* Serial */ | |
559 | at91_add_device_serial(); | |
560 | /* Ethernet */ | |
e3ba22db | 561 | at91_add_device_eth(&yl9200_eth_data); |
3ad0920d | 562 | /* USB Host */ |
e3ba22db | 563 | at91_add_device_usbh(&yl9200_usbh_data); |
3ad0920d | 564 | /* USB Device */ |
e3ba22db | 565 | at91_add_device_udc(&yl9200_udc_data); |
3ad0920d | 566 | /* I2C */ |
e3ba22db AV |
567 | at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices)); |
568 | /* MMC */ | |
569 | at91_add_device_mmc(0, &yl9200_mmc_data); | |
3ad0920d | 570 | /* NAND */ |
e3ba22db | 571 | at91_add_device_nand(&yl9200_nand_data); |
3ad0920d | 572 | /* NOR Flash */ |
e3ba22db AV |
573 | platform_device_register(&yl9200_flash); |
574 | #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) | |
575 | /* SPI */ | |
576 | at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices)); | |
577 | /* Touchscreen */ | |
578 | yl9200_add_device_ts(); | |
579 | #endif | |
580 | /* LEDs. */ | |
581 | at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds)); | |
3ad0920d | 582 | /* Push Buttons */ |
e3ba22db AV |
583 | yl9200_add_device_buttons(); |
584 | /* VGA */ | |
585 | yl9200_add_device_video(); | |
3ad0920d SB |
586 | } |
587 | ||
588 | MACHINE_START(YL9200, "uCdragon YL-9200") | |
e3ba22db | 589 | /* Maintainer: S.Birtles */ |
e3ba22db | 590 | .timer = &at91rm9200_timer, |
21d08b9d | 591 | .map_io = at91_map_io, |
1b021a3b | 592 | .init_early = yl9200_init_early, |
92100c12 | 593 | .init_irq = at91_init_irq_default, |
e3ba22db | 594 | .init_machine = yl9200_board_init, |
3ad0920d | 595 | MACHINE_END |