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ARM: at91: add PWM clock
[linux-2.6-block.git] / arch / arm / mach-at91 / at91sam9g45.c
CommitLineData
789b23bc
NF		 1/*
2 * Chip-specific setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
f407c2e3 14#include <linux/dma-mapping.h>
2edb90ae 15#include <linux/clk/at91_pmc.h>
789b23bc
NF		 16
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
9f97da78 20#include <asm/system_misc.h>
789b23bc 21#include <mach/at91sam9g45.h>
5f9f0a41 22#include <mach/cpu.h>
789b23bc 23
a510b9ba 24#include "at91_aic.h"
21d08b9d 25#include "soc.h"
789b23bc
NF		 26#include "generic.h"
27#include "clock.h"
faee0cc3 28#include "sam9_smc.h"
5ad945ea 29#include "pm.h"
789b23bc 30
789b23bc
NF		 31/* --------------------------------------------------------------------
32 * Clocks
33 * -------------------------------------------------------------------- */
34
35/*
36 * The peripheral clocks.
37 */
38static struct clk pioA_clk = {
39 .name = "pioA_clk",
40 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk pioB_clk = {
44 .name = "pioB_clk",
45 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk pioC_clk = {
49 .name = "pioC_clk",
50 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk pioDE_clk = {
54 .name = "pioDE_clk",
55 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
56 .type = CLK_TYPE_PERIPHERAL,
57};
237a62a1
PK		 58static struct clk trng_clk = {
59 .name = "trng_clk",
60 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
61 .type = CLK_TYPE_PERIPHERAL,
62};
789b23bc
NF		 63static struct clk usart0_clk = {
64 .name = "usart0_clk",
65 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk usart1_clk = {
69 .name = "usart1_clk",
70 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk usart2_clk = {
74 .name = "usart2_clk",
75 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart3_clk = {
79 .name = "usart3_clk",
80 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk mmc0_clk = {
84 .name = "mci0_clk",
85 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk twi0_clk = {
89 .name = "twi0_clk",
90 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk twi1_clk = {
94 .name = "twi1_clk",
95 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk spi0_clk = {
99 .name = "spi0_clk",
100 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk spi1_clk = {
104 .name = "spi1_clk",
105 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk ssc0_clk = {
109 .name = "ssc0_clk",
110 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk ssc1_clk = {
114 .name = "ssc1_clk",
115 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
116 .type = CLK_TYPE_PERIPHERAL,
117};
ab64511c
FG		 118static struct clk tcb0_clk = {
119 .name = "tcb0_clk",
789b23bc
NF		 120 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk pwm_clk = {
124 .name = "pwm_clk",
125 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk tsc_clk = {
129 .name = "tsc_clk",
130 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk dma_clk = {
134 .name = "dma_clk",
135 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk uhphs_clk = {
139 .name = "uhphs_clk",
140 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk lcdc_clk = {
144 .name = "lcdc_clk",
145 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk ac97_clk = {
149 .name = "ac97_clk",
150 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk macb_clk = {
865d605e 154 .name = "pclk",
789b23bc
NF		 155 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk isi_clk = {
159 .name = "isi_clk",
160 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk udphs_clk = {
164 .name = "udphs_clk",
165 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk mmc1_clk = {
169 .name = "mci1_clk",
170 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173
5f9f0a41
NF		 174/* Video decoder clock - Only for sam9m10/sam9m11 */
175static struct clk vdec_clk = {
176 .name = "vdec_clk",
177 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
178 .type = CLK_TYPE_PERIPHERAL,
179};
180
4a5920e8
MR		 181static struct clk adc_op_clk = {
182 .name = "adc_op_clk",
183 .type = CLK_TYPE_PERIPHERAL,
184 .rate_hz = 13200000,
185};
186
815e9721
NR		 187/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
188static struct clk aestdessha_clk = {
189 .name = "aestdessha_clk",
190 .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
191 .type = CLK_TYPE_PERIPHERAL,
192};
193
789b23bc
NF		 194static struct clk *periph_clocks[] __initdata = {
195 &pioA_clk,
196 &pioB_clk,
197 &pioC_clk,
198 &pioDE_clk,
237a62a1 199 &trng_clk,
789b23bc
NF		 200 &usart0_clk,
201 &usart1_clk,
202 &usart2_clk,
203 &usart3_clk,
204 &mmc0_clk,
205 &twi0_clk,
206 &twi1_clk,
207 &spi0_clk,
208 &spi1_clk,
209 &ssc0_clk,
210 &ssc1_clk,
ab64511c 211 &tcb0_clk,
789b23bc
NF		 212 &pwm_clk,
213 &tsc_clk,
214 &dma_clk,
215 &uhphs_clk,
216 &lcdc_clk,
217 &ac97_clk,
218 &macb_clk,
219 &isi_clk,
220 &udphs_clk,
221 &mmc1_clk,
4a5920e8 222 &adc_op_clk,
815e9721 223 &aestdessha_clk,
789b23bc 224 // irq0
bd602995
JCPV		 225};
226
227static struct clk_lookup periph_clocks_lookups[] = {
865d605e
JI		 228 /* One additional fake clock for macb_hclk */
229 CLKDEV_CON_ID("hclk", &macb_clk),
bd602995
JCPV		 230 /* One additional fake clock for ohci */
231 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
bbd44f6b
JH		 232 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
233 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
9d87159e
JCPV		 234 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
235 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
236 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
237 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
238 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995
JCPV		 239 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
240 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
241 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
242 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
fac368a0
NV		 243 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
244 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
636036d2
BS		 245 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
246 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
099343c6
BS		 247 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
248 CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
237a62a1 249 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
815e9721
NR		 250 CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
251 CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
252 CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
49fe2ba3
NF		 253 /* more usart lookup table for DT entries */
254 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
255 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
256 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
257 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
258 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
3a61a5da
NF		 259 /* more tc lookup table for DT entries */
260 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
261 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
6a062459 262 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
62c5553a 263 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
23e3b24f
LD		 264 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
265 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
f7d19b90
LD		 266 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
267 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
f0db66a5
RG		 268 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
269 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
3cba498f
JCPV		 270 CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
271 CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
0af4316b
JCPV		 272 /* fake hclk clock */
273 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
5314ec8e
JCPV		 274 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
275 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
276 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
277 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
278 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
279
619d4a4b
JCPV		 280 CLKDEV_CON_ID("pioA", &pioA_clk),
281 CLKDEV_CON_ID("pioB", &pioB_clk),
282 CLKDEV_CON_ID("pioC", &pioC_clk),
283 CLKDEV_CON_ID("pioD", &pioDE_clk),
284 CLKDEV_CON_ID("pioE", &pioDE_clk),
4a5920e8
MR		 285 /* Fake adc clock */
286 CLKDEV_CON_ID("adc_clk", &tsc_clk),
050208df 287 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
bd602995
JCPV		 288};
289
290static struct clk_lookup usart_clocks_lookups[] = {
291 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
292 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
293 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
294 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
295 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
789b23bc
NF		 296};
297
298/*
299 * The two programmable clocks.
300 * You must configure pin multiplexing to bring these signals out.
301 */
302static struct clk pck0 = {
303 .name = "pck0",
304 .pmc_mask = AT91_PMC_PCK0,
305 .type = CLK_TYPE_PROGRAMMABLE,
306 .id = 0,
307};
308static struct clk pck1 = {
309 .name = "pck1",
310 .pmc_mask = AT91_PMC_PCK1,
311 .type = CLK_TYPE_PROGRAMMABLE,
312 .id = 1,
313};
314
315static void __init at91sam9g45_register_clocks(void)
316{
317 int i;
318
319 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
320 clk_register(periph_clocks[i]);
321
bd602995
JCPV		 322 clkdev_add_table(periph_clocks_lookups,
323 ARRAY_SIZE(periph_clocks_lookups));
324 clkdev_add_table(usart_clocks_lookups,
325 ARRAY_SIZE(usart_clocks_lookups));
326
5f9f0a41
NF		 327 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
328 clk_register(&vdec_clk);
329
789b23bc
NF		 330 clk_register(&pck0);
331 clk_register(&pck1);
332}
333
334/* --------------------------------------------------------------------
335 * GPIO
336 * -------------------------------------------------------------------- */
337
1a2d9156 338static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
789b23bc
NF		 339 {
340 .id = AT91SAM9G45_ID_PIOA,
80e91cb8 341 .regbase = AT91SAM9G45_BASE_PIOA,
789b23bc
NF		 342 }, {
343 .id = AT91SAM9G45_ID_PIOB,
80e91cb8 344 .regbase = AT91SAM9G45_BASE_PIOB,
789b23bc
NF		 345 }, {
346 .id = AT91SAM9G45_ID_PIOC,
80e91cb8 347 .regbase = AT91SAM9G45_BASE_PIOC,
789b23bc
NF		 348 }, {
349 .id = AT91SAM9G45_ID_PIODE,
80e91cb8 350 .regbase = AT91SAM9G45_BASE_PIOD,
789b23bc
NF		 351 }, {
352 .id = AT91SAM9G45_ID_PIODE,
80e91cb8 353 .regbase = AT91SAM9G45_BASE_PIOE,
789b23bc
NF		 354 }
355};
356
789b23bc
NF		 357/* --------------------------------------------------------------------
358 * AT91SAM9G45 processor initialization
359 * -------------------------------------------------------------------- */
360
21d08b9d 361static void __init at91sam9g45_map_io(void)
789b23bc 362{
f0051d82 363 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
1b021a3b 364}
789b23bc 365
cfa5a1fe
JCPV		 366static void __init at91sam9g45_ioremap_registers(void)
367{
f22deee5 368 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
e9f68b5c 369 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
f363c407
JCPV		 370 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
371 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
4ab0c599 372 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
faee0cc3 373 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
4342d647 374 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
6b625891 375 at91_pm_set_standby(at91_ddr_standby);
cfa5a1fe
JCPV		 376}
377
46539374 378static void __init at91sam9g45_initialize(void)
1b021a3b 379{
0d781716 380 arm_pm_idle = at91sam9_idle;
1b2073e7 381 arm_pm_restart = at91sam9g45_restart;
789b23bc 382
6de714c2 383 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
94c4c79f 384 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
6de714c2 385
789b23bc
NF		 386 /* Register GPIO subsystem */
387 at91_gpio_init(at91sam9g45_gpio, 5);
388}
389
390/* --------------------------------------------------------------------
391 * Interrupt initialization
392 * -------------------------------------------------------------------- */
393
394/*
395 * The default interrupt priority levels (0 = lowest, 7 = highest).
396 */
397static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
398 7, /* Advanced Interrupt Controller (FIQ) */
399 7, /* System Peripherals */
400 1, /* Parallel IO Controller A */
401 1, /* Parallel IO Controller B */
402 1, /* Parallel IO Controller C */
403 1, /* Parallel IO Controller D and E */
404 0,
405 5, /* USART 0 */
406 5, /* USART 1 */
407 5, /* USART 2 */
408 5, /* USART 3 */
409 0, /* Multimedia Card Interface 0 */
410 6, /* Two-Wire Interface 0 */
411 6, /* Two-Wire Interface 1 */
412 5, /* Serial Peripheral Interface 0 */
413 5, /* Serial Peripheral Interface 1 */
414 4, /* Serial Synchronous Controller 0 */
415 4, /* Serial Synchronous Controller 1 */
416 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
417 0, /* Pulse Width Modulation Controller */
418 0, /* Touch Screen Controller */
419 0, /* DMA Controller */
420 2, /* USB Host High Speed port */
421 3, /* LDC Controller */
422 5, /* AC97 Controller */
423 3, /* Ethernet */
424 0, /* Image Sensor Interface */
425 2, /* USB Device High speed port */
815e9721 426 0, /* AESTDESSHA Crypto HW Accelerators */
789b23bc
NF		 427 0, /* Multimedia Card Interface 1 */
428 0,
429 0, /* Advanced Interrupt Controller (IRQ0) */
430};
431
84ddb087 432AT91_SOC_START(at91sam9g45)
21d08b9d 433 .map_io = at91sam9g45_map_io,
92100c12 434 .default_irq_priority = at91sam9g45_default_irq_priority,
546c830c 435 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
cfa5a1fe 436 .ioremap_registers = at91sam9g45_ioremap_registers,
51ddec76 437 .register_clocks = at91sam9g45_register_clocks,
21d08b9d 438 .init = at91sam9g45_initialize,
8d39e0fd 439AT91_SOC_END
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