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789b23bc NF |
1 | /* |
2 | * Chip-specific setup code for the AT91SAM9G45 family | |
3 | * | |
4 | * Copyright (C) 2009 Atmel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
f407c2e3 | 14 | #include <linux/dma-mapping.h> |
2edb90ae | 15 | #include <linux/clk/at91_pmc.h> |
789b23bc NF |
16 | |
17 | #include <asm/irq.h> | |
18 | #include <asm/mach/arch.h> | |
19 | #include <asm/mach/map.h> | |
9f97da78 | 20 | #include <asm/system_misc.h> |
789b23bc | 21 | #include <mach/at91sam9g45.h> |
5f9f0a41 | 22 | #include <mach/cpu.h> |
ac11a1d4 | 23 | #include <mach/hardware.h> |
789b23bc | 24 | |
a510b9ba | 25 | #include "at91_aic.h" |
21d08b9d | 26 | #include "soc.h" |
789b23bc | 27 | #include "generic.h" |
faee0cc3 | 28 | #include "sam9_smc.h" |
5ad945ea | 29 | #include "pm.h" |
789b23bc | 30 | |
003b45e2 AB |
31 | #if defined(CONFIG_OLD_CLK_AT91) |
32 | #include "clock.h" | |
789b23bc NF |
33 | /* -------------------------------------------------------------------- |
34 | * Clocks | |
35 | * -------------------------------------------------------------------- */ | |
36 | ||
37 | /* | |
38 | * The peripheral clocks. | |
39 | */ | |
40 | static struct clk pioA_clk = { | |
41 | .name = "pioA_clk", | |
42 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOA, | |
43 | .type = CLK_TYPE_PERIPHERAL, | |
44 | }; | |
45 | static struct clk pioB_clk = { | |
46 | .name = "pioB_clk", | |
47 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOB, | |
48 | .type = CLK_TYPE_PERIPHERAL, | |
49 | }; | |
50 | static struct clk pioC_clk = { | |
51 | .name = "pioC_clk", | |
52 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOC, | |
53 | .type = CLK_TYPE_PERIPHERAL, | |
54 | }; | |
55 | static struct clk pioDE_clk = { | |
56 | .name = "pioDE_clk", | |
57 | .pmc_mask = 1 << AT91SAM9G45_ID_PIODE, | |
58 | .type = CLK_TYPE_PERIPHERAL, | |
59 | }; | |
237a62a1 PK |
60 | static struct clk trng_clk = { |
61 | .name = "trng_clk", | |
62 | .pmc_mask = 1 << AT91SAM9G45_ID_TRNG, | |
63 | .type = CLK_TYPE_PERIPHERAL, | |
64 | }; | |
789b23bc NF |
65 | static struct clk usart0_clk = { |
66 | .name = "usart0_clk", | |
67 | .pmc_mask = 1 << AT91SAM9G45_ID_US0, | |
68 | .type = CLK_TYPE_PERIPHERAL, | |
69 | }; | |
70 | static struct clk usart1_clk = { | |
71 | .name = "usart1_clk", | |
72 | .pmc_mask = 1 << AT91SAM9G45_ID_US1, | |
73 | .type = CLK_TYPE_PERIPHERAL, | |
74 | }; | |
75 | static struct clk usart2_clk = { | |
76 | .name = "usart2_clk", | |
77 | .pmc_mask = 1 << AT91SAM9G45_ID_US2, | |
78 | .type = CLK_TYPE_PERIPHERAL, | |
79 | }; | |
80 | static struct clk usart3_clk = { | |
81 | .name = "usart3_clk", | |
82 | .pmc_mask = 1 << AT91SAM9G45_ID_US3, | |
83 | .type = CLK_TYPE_PERIPHERAL, | |
84 | }; | |
85 | static struct clk mmc0_clk = { | |
86 | .name = "mci0_clk", | |
87 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI0, | |
88 | .type = CLK_TYPE_PERIPHERAL, | |
89 | }; | |
90 | static struct clk twi0_clk = { | |
91 | .name = "twi0_clk", | |
92 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI0, | |
93 | .type = CLK_TYPE_PERIPHERAL, | |
94 | }; | |
95 | static struct clk twi1_clk = { | |
96 | .name = "twi1_clk", | |
97 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI1, | |
98 | .type = CLK_TYPE_PERIPHERAL, | |
99 | }; | |
100 | static struct clk spi0_clk = { | |
101 | .name = "spi0_clk", | |
102 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI0, | |
103 | .type = CLK_TYPE_PERIPHERAL, | |
104 | }; | |
105 | static struct clk spi1_clk = { | |
106 | .name = "spi1_clk", | |
107 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI1, | |
108 | .type = CLK_TYPE_PERIPHERAL, | |
109 | }; | |
110 | static struct clk ssc0_clk = { | |
111 | .name = "ssc0_clk", | |
112 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC0, | |
113 | .type = CLK_TYPE_PERIPHERAL, | |
114 | }; | |
115 | static struct clk ssc1_clk = { | |
116 | .name = "ssc1_clk", | |
117 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC1, | |
118 | .type = CLK_TYPE_PERIPHERAL, | |
119 | }; | |
ab64511c FG |
120 | static struct clk tcb0_clk = { |
121 | .name = "tcb0_clk", | |
789b23bc NF |
122 | .pmc_mask = 1 << AT91SAM9G45_ID_TCB, |
123 | .type = CLK_TYPE_PERIPHERAL, | |
124 | }; | |
125 | static struct clk pwm_clk = { | |
126 | .name = "pwm_clk", | |
127 | .pmc_mask = 1 << AT91SAM9G45_ID_PWMC, | |
128 | .type = CLK_TYPE_PERIPHERAL, | |
129 | }; | |
130 | static struct clk tsc_clk = { | |
131 | .name = "tsc_clk", | |
132 | .pmc_mask = 1 << AT91SAM9G45_ID_TSC, | |
133 | .type = CLK_TYPE_PERIPHERAL, | |
134 | }; | |
135 | static struct clk dma_clk = { | |
136 | .name = "dma_clk", | |
137 | .pmc_mask = 1 << AT91SAM9G45_ID_DMA, | |
138 | .type = CLK_TYPE_PERIPHERAL, | |
139 | }; | |
140 | static struct clk uhphs_clk = { | |
141 | .name = "uhphs_clk", | |
142 | .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS, | |
143 | .type = CLK_TYPE_PERIPHERAL, | |
144 | }; | |
145 | static struct clk lcdc_clk = { | |
146 | .name = "lcdc_clk", | |
147 | .pmc_mask = 1 << AT91SAM9G45_ID_LCDC, | |
148 | .type = CLK_TYPE_PERIPHERAL, | |
149 | }; | |
150 | static struct clk ac97_clk = { | |
151 | .name = "ac97_clk", | |
152 | .pmc_mask = 1 << AT91SAM9G45_ID_AC97C, | |
153 | .type = CLK_TYPE_PERIPHERAL, | |
154 | }; | |
155 | static struct clk macb_clk = { | |
865d605e | 156 | .name = "pclk", |
789b23bc NF |
157 | .pmc_mask = 1 << AT91SAM9G45_ID_EMAC, |
158 | .type = CLK_TYPE_PERIPHERAL, | |
159 | }; | |
160 | static struct clk isi_clk = { | |
161 | .name = "isi_clk", | |
162 | .pmc_mask = 1 << AT91SAM9G45_ID_ISI, | |
163 | .type = CLK_TYPE_PERIPHERAL, | |
164 | }; | |
165 | static struct clk udphs_clk = { | |
166 | .name = "udphs_clk", | |
167 | .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS, | |
168 | .type = CLK_TYPE_PERIPHERAL, | |
169 | }; | |
170 | static struct clk mmc1_clk = { | |
171 | .name = "mci1_clk", | |
172 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI1, | |
173 | .type = CLK_TYPE_PERIPHERAL, | |
174 | }; | |
175 | ||
5f9f0a41 NF |
176 | /* Video decoder clock - Only for sam9m10/sam9m11 */ |
177 | static struct clk vdec_clk = { | |
178 | .name = "vdec_clk", | |
179 | .pmc_mask = 1 << AT91SAM9G45_ID_VDEC, | |
180 | .type = CLK_TYPE_PERIPHERAL, | |
181 | }; | |
182 | ||
4a5920e8 MR |
183 | static struct clk adc_op_clk = { |
184 | .name = "adc_op_clk", | |
185 | .type = CLK_TYPE_PERIPHERAL, | |
cab91594 | 186 | .rate_hz = 300000, |
4a5920e8 MR |
187 | }; |
188 | ||
815e9721 NR |
189 | /* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */ |
190 | static struct clk aestdessha_clk = { | |
191 | .name = "aestdessha_clk", | |
192 | .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA, | |
193 | .type = CLK_TYPE_PERIPHERAL, | |
194 | }; | |
195 | ||
789b23bc NF |
196 | static struct clk *periph_clocks[] __initdata = { |
197 | &pioA_clk, | |
198 | &pioB_clk, | |
199 | &pioC_clk, | |
200 | &pioDE_clk, | |
237a62a1 | 201 | &trng_clk, |
789b23bc NF |
202 | &usart0_clk, |
203 | &usart1_clk, | |
204 | &usart2_clk, | |
205 | &usart3_clk, | |
206 | &mmc0_clk, | |
207 | &twi0_clk, | |
208 | &twi1_clk, | |
209 | &spi0_clk, | |
210 | &spi1_clk, | |
211 | &ssc0_clk, | |
212 | &ssc1_clk, | |
ab64511c | 213 | &tcb0_clk, |
789b23bc NF |
214 | &pwm_clk, |
215 | &tsc_clk, | |
216 | &dma_clk, | |
217 | &uhphs_clk, | |
218 | &lcdc_clk, | |
219 | &ac97_clk, | |
220 | &macb_clk, | |
221 | &isi_clk, | |
222 | &udphs_clk, | |
223 | &mmc1_clk, | |
4a5920e8 | 224 | &adc_op_clk, |
815e9721 | 225 | &aestdessha_clk, |
789b23bc | 226 | // irq0 |
bd602995 JCPV |
227 | }; |
228 | ||
229 | static struct clk_lookup periph_clocks_lookups[] = { | |
865d605e JI |
230 | /* One additional fake clock for macb_hclk */ |
231 | CLKDEV_CON_ID("hclk", &macb_clk), | |
bd602995 JCPV |
232 | /* One additional fake clock for ohci */ |
233 | CLKDEV_CON_ID("ohci_clk", &uhphs_clk), | |
bbd44f6b JH |
234 | CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk), |
235 | CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk), | |
9d87159e JCPV |
236 | CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), |
237 | CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), | |
238 | CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), | |
239 | CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), | |
240 | CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), | |
bd602995 JCPV |
241 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
242 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), | |
243 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), | |
244 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), | |
fac368a0 NV |
245 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk), |
246 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk), | |
636036d2 BS |
247 | CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk), |
248 | CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk), | |
099343c6 BS |
249 | CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk), |
250 | CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk), | |
237a62a1 | 251 | CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), |
815e9721 NR |
252 | CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk), |
253 | CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk), | |
254 | CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk), | |
e030427f | 255 | CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk), |
49fe2ba3 NF |
256 | /* more usart lookup table for DT entries */ |
257 | CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), | |
258 | CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk), | |
259 | CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk), | |
260 | CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk), | |
261 | CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk), | |
3a61a5da NF |
262 | /* more tc lookup table for DT entries */ |
263 | CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk), | |
264 | CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk), | |
6a062459 | 265 | CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk), |
62c5553a | 266 | CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk), |
23e3b24f LD |
267 | CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk), |
268 | CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk), | |
f7d19b90 LD |
269 | CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk), |
270 | CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk), | |
f0db66a5 RG |
271 | CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), |
272 | CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), | |
3cba498f JCPV |
273 | CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk), |
274 | CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk), | |
0af4316b JCPV |
275 | /* fake hclk clock */ |
276 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), | |
5314ec8e JCPV |
277 | CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), |
278 | CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), | |
279 | CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), | |
280 | CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk), | |
281 | CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk), | |
282 | ||
619d4a4b JCPV |
283 | CLKDEV_CON_ID("pioA", &pioA_clk), |
284 | CLKDEV_CON_ID("pioB", &pioB_clk), | |
285 | CLKDEV_CON_ID("pioC", &pioC_clk), | |
286 | CLKDEV_CON_ID("pioD", &pioDE_clk), | |
287 | CLKDEV_CON_ID("pioE", &pioDE_clk), | |
4a5920e8 MR |
288 | /* Fake adc clock */ |
289 | CLKDEV_CON_ID("adc_clk", &tsc_clk), | |
050208df | 290 | CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk), |
bd602995 JCPV |
291 | }; |
292 | ||
293 | static struct clk_lookup usart_clocks_lookups[] = { | |
294 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), | |
295 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), | |
296 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), | |
297 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), | |
298 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), | |
789b23bc NF |
299 | }; |
300 | ||
301 | /* | |
302 | * The two programmable clocks. | |
303 | * You must configure pin multiplexing to bring these signals out. | |
304 | */ | |
305 | static struct clk pck0 = { | |
306 | .name = "pck0", | |
307 | .pmc_mask = AT91_PMC_PCK0, | |
308 | .type = CLK_TYPE_PROGRAMMABLE, | |
309 | .id = 0, | |
310 | }; | |
311 | static struct clk pck1 = { | |
312 | .name = "pck1", | |
313 | .pmc_mask = AT91_PMC_PCK1, | |
314 | .type = CLK_TYPE_PROGRAMMABLE, | |
315 | .id = 1, | |
316 | }; | |
317 | ||
318 | static void __init at91sam9g45_register_clocks(void) | |
319 | { | |
320 | int i; | |
321 | ||
322 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | |
323 | clk_register(periph_clocks[i]); | |
324 | ||
bd602995 JCPV |
325 | clkdev_add_table(periph_clocks_lookups, |
326 | ARRAY_SIZE(periph_clocks_lookups)); | |
327 | clkdev_add_table(usart_clocks_lookups, | |
328 | ARRAY_SIZE(usart_clocks_lookups)); | |
329 | ||
5f9f0a41 NF |
330 | if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) |
331 | clk_register(&vdec_clk); | |
332 | ||
789b23bc NF |
333 | clk_register(&pck0); |
334 | clk_register(&pck1); | |
335 | } | |
003b45e2 AB |
336 | #else |
337 | #define at91sam9g45_register_clocks NULL | |
338 | #endif | |
789b23bc NF |
339 | |
340 | /* -------------------------------------------------------------------- | |
341 | * GPIO | |
342 | * -------------------------------------------------------------------- */ | |
343 | ||
1a2d9156 | 344 | static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = { |
789b23bc NF |
345 | { |
346 | .id = AT91SAM9G45_ID_PIOA, | |
80e91cb8 | 347 | .regbase = AT91SAM9G45_BASE_PIOA, |
789b23bc NF |
348 | }, { |
349 | .id = AT91SAM9G45_ID_PIOB, | |
80e91cb8 | 350 | .regbase = AT91SAM9G45_BASE_PIOB, |
789b23bc NF |
351 | }, { |
352 | .id = AT91SAM9G45_ID_PIOC, | |
80e91cb8 | 353 | .regbase = AT91SAM9G45_BASE_PIOC, |
789b23bc NF |
354 | }, { |
355 | .id = AT91SAM9G45_ID_PIODE, | |
80e91cb8 | 356 | .regbase = AT91SAM9G45_BASE_PIOD, |
789b23bc NF |
357 | }, { |
358 | .id = AT91SAM9G45_ID_PIODE, | |
80e91cb8 | 359 | .regbase = AT91SAM9G45_BASE_PIOE, |
789b23bc NF |
360 | } |
361 | }; | |
362 | ||
789b23bc NF |
363 | /* -------------------------------------------------------------------- |
364 | * AT91SAM9G45 processor initialization | |
365 | * -------------------------------------------------------------------- */ | |
366 | ||
21d08b9d | 367 | static void __init at91sam9g45_map_io(void) |
789b23bc | 368 | { |
f0051d82 | 369 | at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); |
1b021a3b | 370 | } |
789b23bc | 371 | |
cfa5a1fe JCPV |
372 | static void __init at91sam9g45_ioremap_registers(void) |
373 | { | |
f22deee5 | 374 | at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); |
e9f68b5c | 375 | at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); |
f363c407 JCPV |
376 | at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512); |
377 | at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512); | |
4ab0c599 | 378 | at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); |
faee0cc3 | 379 | at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); |
4342d647 | 380 | at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX); |
6b625891 | 381 | at91_pm_set_standby(at91_ddr_standby); |
cfa5a1fe JCPV |
382 | } |
383 | ||
46539374 | 384 | static void __init at91sam9g45_initialize(void) |
1b021a3b | 385 | { |
0d781716 | 386 | arm_pm_idle = at91sam9_idle; |
1b2073e7 | 387 | arm_pm_restart = at91sam9g45_restart; |
789b23bc | 388 | |
6de714c2 | 389 | at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC); |
94c4c79f | 390 | at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT); |
6de714c2 | 391 | |
789b23bc NF |
392 | /* Register GPIO subsystem */ |
393 | at91_gpio_init(at91sam9g45_gpio, 5); | |
394 | } | |
395 | ||
396 | /* -------------------------------------------------------------------- | |
397 | * Interrupt initialization | |
398 | * -------------------------------------------------------------------- */ | |
399 | ||
400 | /* | |
401 | * The default interrupt priority levels (0 = lowest, 7 = highest). | |
402 | */ | |
403 | static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { | |
404 | 7, /* Advanced Interrupt Controller (FIQ) */ | |
405 | 7, /* System Peripherals */ | |
406 | 1, /* Parallel IO Controller A */ | |
407 | 1, /* Parallel IO Controller B */ | |
408 | 1, /* Parallel IO Controller C */ | |
409 | 1, /* Parallel IO Controller D and E */ | |
410 | 0, | |
411 | 5, /* USART 0 */ | |
412 | 5, /* USART 1 */ | |
413 | 5, /* USART 2 */ | |
414 | 5, /* USART 3 */ | |
415 | 0, /* Multimedia Card Interface 0 */ | |
416 | 6, /* Two-Wire Interface 0 */ | |
417 | 6, /* Two-Wire Interface 1 */ | |
418 | 5, /* Serial Peripheral Interface 0 */ | |
419 | 5, /* Serial Peripheral Interface 1 */ | |
420 | 4, /* Serial Synchronous Controller 0 */ | |
421 | 4, /* Serial Synchronous Controller 1 */ | |
422 | 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ | |
423 | 0, /* Pulse Width Modulation Controller */ | |
424 | 0, /* Touch Screen Controller */ | |
425 | 0, /* DMA Controller */ | |
426 | 2, /* USB Host High Speed port */ | |
427 | 3, /* LDC Controller */ | |
428 | 5, /* AC97 Controller */ | |
429 | 3, /* Ethernet */ | |
430 | 0, /* Image Sensor Interface */ | |
431 | 2, /* USB Device High speed port */ | |
815e9721 | 432 | 0, /* AESTDESSHA Crypto HW Accelerators */ |
789b23bc NF |
433 | 0, /* Multimedia Card Interface 1 */ |
434 | 0, | |
435 | 0, /* Advanced Interrupt Controller (IRQ0) */ | |
436 | }; | |
437 | ||
84ddb087 | 438 | AT91_SOC_START(at91sam9g45) |
21d08b9d | 439 | .map_io = at91sam9g45_map_io, |
92100c12 | 440 | .default_irq_priority = at91sam9g45_default_irq_priority, |
546c830c | 441 | .extern_irq = (1 << AT91SAM9G45_ID_IRQ0), |
cfa5a1fe | 442 | .ioremap_registers = at91sam9g45_ioremap_registers, |
51ddec76 | 443 | .register_clocks = at91sam9g45_register_clocks, |
21d08b9d | 444 | .init = at91sam9g45_initialize, |
8d39e0fd | 445 | AT91_SOC_END |