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ARM: at91: make DBGU soc independent
[linux-block.git] / arch / arm / mach-at91 / at91sam9263_devices.c
CommitLineData
b2c65616
AV		 1/*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
c6686ff9 15#include <linux/dma-mapping.h>
2f8163ba 16#include <linux/gpio.h>
b2c65616 17#include <linux/platform_device.h>
f230d3f5 18#include <linux/i2c-gpio.h>
b2c65616 19
f230d3f5 20#include <linux/fb.h>
b8b78609
JA		 21#include <video/atmel_lcdc.h>
22
a09e64fb 23#include <mach/board.h>
a09e64fb
RK		 24#include <mach/at91sam9263.h>
25#include <mach/at91sam9263_matrix.h>
26#include <mach/at91sam9_smc.h>
b2c65616
AV		 27
28#include "generic.h"
29
b2c65616
AV		 30
31/* --------------------------------------------------------------------
32 * USB Host
33 * -------------------------------------------------------------------- */
34
35#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 36static u64 ohci_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 37static struct at91_usbh_data usbh_data;
38
39static struct resource usbh_resources[] = {
40 [0] = {
41 .start = AT91SAM9263_UHP_BASE,
42 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9263_ID_UHP,
47 .end = AT91SAM9263_ID_UHP,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static struct platform_device at91_usbh_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
c6686ff9 57 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 58 .platform_data = &usbh_data,
59 },
60 .resource = usbh_resources,
61 .num_resources = ARRAY_SIZE(usbh_resources),
62};
63
64void __init at91_add_device_usbh(struct at91_usbh_data *data)
65{
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (data->vbus_pin[i])
74 at91_set_gpio_output(data->vbus_pin[i], 0);
75 }
76
1fcaea7e
TP		 77 /* Enable overcurrent notification */
78 for (i = 0; i < data->ports; i++) {
79 if (data->overcurrent_pin[i])
80 at91_set_gpio_input(data->overcurrent_pin[i], 1);
81 }
82
b2c65616
AV		 83 usbh_data = *data;
84 platform_device_register(&at91_usbh_device);
85}
86#else
87void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
88#endif
89
90
91/* --------------------------------------------------------------------
92 * USB Device (Gadget)
93 * -------------------------------------------------------------------- */
94
95#ifdef CONFIG_USB_GADGET_AT91
96static struct at91_udc_data udc_data;
97
98static struct resource udc_resources[] = {
99 [0] = {
100 .start = AT91SAM9263_BASE_UDP,
101 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = AT91SAM9263_ID_UDP,
106 .end = AT91SAM9263_ID_UDP,
107 .flags = IORESOURCE_IRQ,
108 },
109};
110
111static struct platform_device at91_udc_device = {
112 .name = "at91_udc",
113 .id = -1,
114 .dev = {
115 .platform_data = &udc_data,
116 },
117 .resource = udc_resources,
118 .num_resources = ARRAY_SIZE(udc_resources),
119};
120
121void __init at91_add_device_udc(struct at91_udc_data *data)
122{
123 if (!data)
124 return;
125
126 if (data->vbus_pin) {
127 at91_set_gpio_input(data->vbus_pin, 0);
128 at91_set_deglitch(data->vbus_pin, 1);
129 }
130
131 /* Pullup pin is handled internally by USB device peripheral */
132
133 udc_data = *data;
134 platform_device_register(&at91_udc_device);
135}
136#else
137void __init at91_add_device_udc(struct at91_udc_data *data) {}
138#endif
139
140
141/* --------------------------------------------------------------------
142 * Ethernet
143 * -------------------------------------------------------------------- */
144
145#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
c6686ff9 146static u64 eth_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 147static struct at91_eth_data eth_data;
148
149static struct resource eth_resources[] = {
150 [0] = {
151 .start = AT91SAM9263_BASE_EMAC,
152 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
153 .flags = IORESOURCE_MEM,
154 },
155 [1] = {
156 .start = AT91SAM9263_ID_EMAC,
157 .end = AT91SAM9263_ID_EMAC,
158 .flags = IORESOURCE_IRQ,
159 },
160};
161
162static struct platform_device at91sam9263_eth_device = {
163 .name = "macb",
164 .id = -1,
165 .dev = {
166 .dma_mask = &eth_dmamask,
c6686ff9 167 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 168 .platform_data = &eth_data,
169 },
170 .resource = eth_resources,
171 .num_resources = ARRAY_SIZE(eth_resources),
172};
173
174void __init at91_add_device_eth(struct at91_eth_data *data)
175{
176 if (!data)
177 return;
178
179 if (data->phy_irq_pin) {
180 at91_set_gpio_input(data->phy_irq_pin, 0);
181 at91_set_deglitch(data->phy_irq_pin, 1);
182 }
183
184 /* Pins used for MII and RMII */
185 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
186 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
187 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
188 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
189 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
190 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
191 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
192 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
193 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
194 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
195
196 if (!data->is_rmii) {
197 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
198 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
199 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
200 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
201 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
202 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
203 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
204 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
205 }
206
207 eth_data = *data;
208 platform_device_register(&at91sam9263_eth_device);
209}
210#else
211void __init at91_add_device_eth(struct at91_eth_data *data) {}
212#endif
213
214
215/* --------------------------------------------------------------------
216 * MMC / SD
217 * -------------------------------------------------------------------- */
218
219#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 220static u64 mmc_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 221static struct at91_mmc_data mmc0_data, mmc1_data;
222
223static struct resource mmc0_resources[] = {
224 [0] = {
225 .start = AT91SAM9263_BASE_MCI0,
226 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
227 .flags = IORESOURCE_MEM,
228 },
229 [1] = {
230 .start = AT91SAM9263_ID_MCI0,
231 .end = AT91SAM9263_ID_MCI0,
232 .flags = IORESOURCE_IRQ,
233 },
234};
235
236static struct platform_device at91sam9263_mmc0_device = {
237 .name = "at91_mci",
238 .id = 0,
239 .dev = {
240 .dma_mask = &mmc_dmamask,
c6686ff9 241 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 242 .platform_data = &mmc0_data,
243 },
244 .resource = mmc0_resources,
245 .num_resources = ARRAY_SIZE(mmc0_resources),
246};
247
248static struct resource mmc1_resources[] = {
249 [0] = {
250 .start = AT91SAM9263_BASE_MCI1,
251 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 [1] = {
255 .start = AT91SAM9263_ID_MCI1,
256 .end = AT91SAM9263_ID_MCI1,
257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct platform_device at91sam9263_mmc1_device = {
262 .name = "at91_mci",
263 .id = 1,
264 .dev = {
265 .dma_mask = &mmc_dmamask,
c6686ff9 266 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 267 .platform_data = &mmc1_data,
268 },
269 .resource = mmc1_resources,
270 .num_resources = ARRAY_SIZE(mmc1_resources),
271};
272
273void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
274{
275 if (!data)
276 return;
277
278 /* input/irq */
279 if (data->det_pin) {
280 at91_set_gpio_input(data->det_pin, 1);
281 at91_set_deglitch(data->det_pin, 1);
282 }
283 if (data->wp_pin)
284 at91_set_gpio_input(data->wp_pin, 1);
285 if (data->vcc_pin)
286 at91_set_gpio_output(data->vcc_pin, 0);
287
288 if (mmc_id == 0) { /* MCI0 */
289 /* CLK */
290 at91_set_A_periph(AT91_PIN_PA12, 0);
291
292 if (data->slot_b) {
293 /* CMD */
294 at91_set_A_periph(AT91_PIN_PA16, 1);
295
296 /* DAT0, maybe DAT1..DAT3 */
297 at91_set_A_periph(AT91_PIN_PA17, 1);
298 if (data->wire4) {
299 at91_set_A_periph(AT91_PIN_PA18, 1);
300 at91_set_A_periph(AT91_PIN_PA19, 1);
301 at91_set_A_periph(AT91_PIN_PA20, 1);
302 }
303 } else {
304 /* CMD */
305 at91_set_A_periph(AT91_PIN_PA1, 1);
306
307 /* DAT0, maybe DAT1..DAT3 */
308 at91_set_A_periph(AT91_PIN_PA0, 1);
309 if (data->wire4) {
310 at91_set_A_periph(AT91_PIN_PA3, 1);
311 at91_set_A_periph(AT91_PIN_PA4, 1);
312 at91_set_A_periph(AT91_PIN_PA5, 1);
313 }
314 }
315
316 mmc0_data = *data;
b2c65616
AV		 317 platform_device_register(&at91sam9263_mmc0_device);
318 } else { /* MCI1 */
319 /* CLK */
320 at91_set_A_periph(AT91_PIN_PA6, 0);
321
322 if (data->slot_b) {
323 /* CMD */
324 at91_set_A_periph(AT91_PIN_PA21, 1);
325
326 /* DAT0, maybe DAT1..DAT3 */
327 at91_set_A_periph(AT91_PIN_PA22, 1);
328 if (data->wire4) {
329 at91_set_A_periph(AT91_PIN_PA23, 1);
330 at91_set_A_periph(AT91_PIN_PA24, 1);
331 at91_set_A_periph(AT91_PIN_PA25, 1);
332 }
333 } else {
334 /* CMD */
335 at91_set_A_periph(AT91_PIN_PA7, 1);
336
337 /* DAT0, maybe DAT1..DAT3 */
338 at91_set_A_periph(AT91_PIN_PA8, 1);
339 if (data->wire4) {
340 at91_set_A_periph(AT91_PIN_PA9, 1);
341 at91_set_A_periph(AT91_PIN_PA10, 1);
342 at91_set_A_periph(AT91_PIN_PA11, 1);
343 }
344 }
345
346 mmc1_data = *data;
b2c65616
AV		 347 platform_device_register(&at91sam9263_mmc1_device);
348 }
349}
350#else
351void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
352#endif
353
e565f206
SG		 354/* --------------------------------------------------------------------
355 * Compact Flash (PCMCIA or IDE)
356 * -------------------------------------------------------------------- */
357
358#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
359 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
360
361static struct at91_cf_data cf0_data;
362
363static struct resource cf0_resources[] = {
364 [0] = {
365 .start = AT91_CHIPSELECT_4,
366 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
367 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
368 }
369};
370
371static struct platform_device cf0_device = {
372 .id = 0,
373 .dev = {
374 .platform_data = &cf0_data,
375 },
376 .resource = cf0_resources,
377 .num_resources = ARRAY_SIZE(cf0_resources),
378};
379
380static struct at91_cf_data cf1_data;
381
382static struct resource cf1_resources[] = {
383 [0] = {
384 .start = AT91_CHIPSELECT_5,
385 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
386 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
387 }
388};
389
390static struct platform_device cf1_device = {
391 .id = 1,
392 .dev = {
393 .platform_data = &cf1_data,
394 },
395 .resource = cf1_resources,
396 .num_resources = ARRAY_SIZE(cf1_resources),
397};
398
399void __init at91_add_device_cf(struct at91_cf_data *data)
400{
401 unsigned long ebi0_csa;
402 struct platform_device *pdev;
403
404 if (!data)
405 return;
406
407 /*
408 * assign CS4 or CS5 to SMC with Compact Flash logic support,
409 * we assume SMC timings are configured by board code,
410 * except True IDE where timings are controlled by driver
411 */
412 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
413 switch (data->chipselect) {
414 case 4:
415 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
416 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
417 cf0_data = *data;
418 pdev = &cf0_device;
419 break;
420 case 5:
421 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
422 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
423 cf1_data = *data;
424 pdev = &cf1_device;
425 break;
426 default:
427 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
428 data->chipselect);
429 return;
430 }
431 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
432
433 if (data->det_pin) {
434 at91_set_gpio_input(data->det_pin, 1);
435 at91_set_deglitch(data->det_pin, 1);
436 }
437
438 if (data->irq_pin) {
439 at91_set_gpio_input(data->irq_pin, 1);
440 at91_set_deglitch(data->irq_pin, 1);
441 }
442
443 if (data->vcc_pin)
444 /* initially off */
445 at91_set_gpio_output(data->vcc_pin, 0);
446
447 /* enable EBI controlled pins */
448 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
449 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
452
453 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
454 platform_device_register(pdev);
455}
456#else
457void __init at91_add_device_cf(struct at91_cf_data *data) {}
458#endif
b2c65616
AV		 459
460/* --------------------------------------------------------------------
461 * NAND / SmartMedia
462 * -------------------------------------------------------------------- */
463
f6ed6f78 464#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 465static struct atmel_nand_data nand_data;
b2c65616
AV		 466
467#define NAND_BASE AT91_CHIPSELECT_3
468
469static struct resource nand_resources[] = {
d7a2415f 470 [0] = {
b2c65616
AV		 471 .start = NAND_BASE,
472 .end = NAND_BASE + SZ_256M - 1,
473 .flags = IORESOURCE_MEM,
d7a2415f
AV		 474 },
475 [1] = {
d28edd1b
JCPV		 476 .start = AT91SAM9263_BASE_ECC0,
477 .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
d7a2415f 478 .flags = IORESOURCE_MEM,
b2c65616
AV		 479 }
480};
481
482static struct platform_device at91sam9263_nand_device = {
3c3796cc 483 .name = "atmel_nand",
b2c65616
AV		 484 .id = -1,
485 .dev = {
486 .platform_data = &nand_data,
487 },
488 .resource = nand_resources,
489 .num_resources = ARRAY_SIZE(nand_resources),
490};
491
3c3796cc 492void __init at91_add_device_nand(struct atmel_nand_data *data)
b2c65616 493{
461d3b4d 494 unsigned long csa;
b2c65616
AV		 495
496 if (!data)
497 return;
498
499 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
22823558 500 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
b2c65616 501
b2c65616
AV		 502 /* enable pin */
503 if (data->enable_pin)
504 at91_set_gpio_output(data->enable_pin, 1);
505
506 /* ready/busy pin */
507 if (data->rdy_pin)
508 at91_set_gpio_input(data->rdy_pin, 1);
509
510 /* card detect pin */
511 if (data->det_pin)
512 at91_set_gpio_input(data->det_pin, 1);
513
514 nand_data = *data;
515 platform_device_register(&at91sam9263_nand_device);
516}
517#else
3c3796cc 518void __init at91_add_device_nand(struct atmel_nand_data *data) {}
b2c65616
AV		 519#endif
520
521
522/* --------------------------------------------------------------------
523 * TWI (i2c)
524 * -------------------------------------------------------------------- */
525
f230d3f5
AV		 526/*
527 * Prefer the GPIO code since the TWI controller isn't robust
528 * (gets overruns and underruns under load) and can only issue
529 * repeated STARTs in one scenario (the driver doesn't yet handle them).
530 */
531#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
532
533static struct i2c_gpio_platform_data pdata = {
534 .sda_pin = AT91_PIN_PB4,
535 .sda_is_open_drain = 1,
536 .scl_pin = AT91_PIN_PB5,
537 .scl_is_open_drain = 1,
538 .udelay = 2, /* ~100 kHz */
539};
540
541static struct platform_device at91sam9263_twi_device = {
542 .name = "i2c-gpio",
543 .id = -1,
544 .dev.platform_data = &pdata,
545};
546
547void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
548{
549 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
550 at91_set_multi_drive(AT91_PIN_PB4, 1);
551
552 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
553 at91_set_multi_drive(AT91_PIN_PB5, 1);
554
555 i2c_register_board_info(0, devices, nr_devices);
556 platform_device_register(&at91sam9263_twi_device);
557}
558
559#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
b2c65616
AV		 560
561static struct resource twi_resources[] = {
562 [0] = {
563 .start = AT91SAM9263_BASE_TWI,
564 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
565 .flags = IORESOURCE_MEM,
566 },
567 [1] = {
568 .start = AT91SAM9263_ID_TWI,
569 .end = AT91SAM9263_ID_TWI,
570 .flags = IORESOURCE_IRQ,
571 },
572};
573
574static struct platform_device at91sam9263_twi_device = {
575 .name = "at91_i2c",
576 .id = -1,
577 .resource = twi_resources,
578 .num_resources = ARRAY_SIZE(twi_resources),
579};
580
f230d3f5 581void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
b2c65616
AV		 582{
583 /* pins used for TWI interface */
584 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
585 at91_set_multi_drive(AT91_PIN_PB4, 1);
586
587 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
588 at91_set_multi_drive(AT91_PIN_PB5, 1);
589
f230d3f5 590 i2c_register_board_info(0, devices, nr_devices);
b2c65616
AV		 591 platform_device_register(&at91sam9263_twi_device);
592}
593#else
f230d3f5 594void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
b2c65616
AV		 595#endif
596
597
598/* --------------------------------------------------------------------
599 * SPI
600 * -------------------------------------------------------------------- */
601
602#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 603static u64 spi_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 604
605static struct resource spi0_resources[] = {
606 [0] = {
607 .start = AT91SAM9263_BASE_SPI0,
608 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
609 .flags = IORESOURCE_MEM,
610 },
611 [1] = {
612 .start = AT91SAM9263_ID_SPI0,
613 .end = AT91SAM9263_ID_SPI0,
614 .flags = IORESOURCE_IRQ,
615 },
616};
617
618static struct platform_device at91sam9263_spi0_device = {
619 .name = "atmel_spi",
620 .id = 0,
621 .dev = {
622 .dma_mask = &spi_dmamask,
c6686ff9 623 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 624 },
625 .resource = spi0_resources,
626 .num_resources = ARRAY_SIZE(spi0_resources),
627};
628
629static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
630
631static struct resource spi1_resources[] = {
632 [0] = {
633 .start = AT91SAM9263_BASE_SPI1,
634 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
635 .flags = IORESOURCE_MEM,
636 },
637 [1] = {
638 .start = AT91SAM9263_ID_SPI1,
639 .end = AT91SAM9263_ID_SPI1,
640 .flags = IORESOURCE_IRQ,
641 },
642};
643
644static struct platform_device at91sam9263_spi1_device = {
645 .name = "atmel_spi",
646 .id = 1,
647 .dev = {
648 .dma_mask = &spi_dmamask,
c6686ff9 649 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 650 },
651 .resource = spi1_resources,
652 .num_resources = ARRAY_SIZE(spi1_resources),
653};
654
655static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
656
657void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
658{
659 int i;
660 unsigned long cs_pin;
661 short enable_spi0 = 0;
662 short enable_spi1 = 0;
663
664 /* Choose SPI chip-selects */
665 for (i = 0; i < nr_devices; i++) {
666 if (devices[i].controller_data)
667 cs_pin = (unsigned long) devices[i].controller_data;
668 else if (devices[i].bus_num == 0)
669 cs_pin = spi0_standard_cs[devices[i].chip_select];
670 else
671 cs_pin = spi1_standard_cs[devices[i].chip_select];
672
673 if (devices[i].bus_num == 0)
674 enable_spi0 = 1;
675 else
676 enable_spi1 = 1;
677
678 /* enable chip-select pin */
679 at91_set_gpio_output(cs_pin, 1);
680
681 /* pass chip-select pin to driver */
682 devices[i].controller_data = (void *) cs_pin;
683 }
684
685 spi_register_board_info(devices, nr_devices);
686
687 /* Configure SPI bus(es) */
688 if (enable_spi0) {
689 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
690 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
7f6e2d99 691 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
b2c65616 692
b2c65616
AV		 693 platform_device_register(&at91sam9263_spi0_device);
694 }
695 if (enable_spi1) {
696 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
697 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
698 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
699
b2c65616
AV		 700 platform_device_register(&at91sam9263_spi1_device);
701 }
702}
703#else
704void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
705#endif
706
707
7776a94c
AV		 708/* --------------------------------------------------------------------
709 * AC97
710 * -------------------------------------------------------------------- */
711
d656f07a 712#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
c6686ff9 713static u64 ac97_dmamask = DMA_BIT_MASK(32);
d656f07a 714static struct ac97c_platform_data ac97_data;
7776a94c
AV		 715
716static struct resource ac97_resources[] = {
717 [0] = {
718 .start = AT91SAM9263_BASE_AC97C,
719 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
720 .flags = IORESOURCE_MEM,
721 },
722 [1] = {
723 .start = AT91SAM9263_ID_AC97C,
724 .end = AT91SAM9263_ID_AC97C,
725 .flags = IORESOURCE_IRQ,
726 },
727};
728
729static struct platform_device at91sam9263_ac97_device = {
d656f07a 730 .name = "atmel_ac97c",
731 .id = 0,
7776a94c
AV		 732 .dev = {
733 .dma_mask = &ac97_dmamask,
c6686ff9 734 .coherent_dma_mask = DMA_BIT_MASK(32),
7776a94c
AV		 735 .platform_data = &ac97_data,
736 },
737 .resource = ac97_resources,
738 .num_resources = ARRAY_SIZE(ac97_resources),
739};
740
d656f07a 741void __init at91_add_device_ac97(struct ac97c_platform_data *data)
7776a94c
AV		 742{
743 if (!data)
744 return;
745
746 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
747 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
748 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
749 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
750
751 /* reset */
752 if (data->reset_pin)
753 at91_set_gpio_output(data->reset_pin, 0);
754
d656f07a 755 ac97_data = *data;
7776a94c
AV		 756 platform_device_register(&at91sam9263_ac97_device);
757}
758#else
d656f07a 759void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
7776a94c
AV		 760#endif
761
58a587dc
MKB		 762/* --------------------------------------------------------------------
763 * CAN Controller
764 * -------------------------------------------------------------------- */
765
766#if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
767static struct resource can_resources[] = {
768 [0] = {
769 .start = AT91SAM9263_BASE_CAN,
770 .end = AT91SAM9263_BASE_CAN + SZ_16K - 1,
771 .flags = IORESOURCE_MEM,
772 },
773 [1] = {
774 .start = AT91SAM9263_ID_CAN,
775 .end = AT91SAM9263_ID_CAN,
776 .flags = IORESOURCE_IRQ,
777 },
778};
779
780static struct platform_device at91sam9263_can_device = {
781 .name = "at91_can",
782 .id = -1,
783 .resource = can_resources,
784 .num_resources = ARRAY_SIZE(can_resources),
785};
786
787void __init at91_add_device_can(struct at91_can_data *data)
788{
789 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
790 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
791 at91sam9263_can_device.dev.platform_data = data;
792
793 platform_device_register(&at91sam9263_can_device);
794}
795#else
796void __init at91_add_device_can(struct at91_can_data *data) {}
797#endif
7776a94c
AV		 798
799/* --------------------------------------------------------------------
800 * LCD Controller
801 * -------------------------------------------------------------------- */
802
803#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 804static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c
AV		 805static struct atmel_lcdfb_info lcdc_data;
806
807static struct resource lcdc_resources[] = {
808 [0] = {
809 .start = AT91SAM9263_LCDC_BASE,
810 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
811 .flags = IORESOURCE_MEM,
812 },
813 [1] = {
814 .start = AT91SAM9263_ID_LCDC,
815 .end = AT91SAM9263_ID_LCDC,
816 .flags = IORESOURCE_IRQ,
817 },
818};
819
820static struct platform_device at91_lcdc_device = {
821 .name = "atmel_lcdfb",
822 .id = 0,
823 .dev = {
824 .dma_mask = &lcdc_dmamask,
c6686ff9 825 .coherent_dma_mask = DMA_BIT_MASK(32),
7776a94c
AV		 826 .platform_data = &lcdc_data,
827 },
828 .resource = lcdc_resources,
829 .num_resources = ARRAY_SIZE(lcdc_resources),
830};
831
832void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
833{
834 if (!data)
835 return;
836
837 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
838 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
839 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
840 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
841 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
842 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
843 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
844 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
845 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
846 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
847 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
848 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
849 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
850 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
851 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
852 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
853 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
854 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
855 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
856 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
857 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
858 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
859
860 lcdc_data = *data;
861 platform_device_register(&at91_lcdc_device);
862}
863#else
864void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
865#endif
866
867
e2920802
AV		 868/* --------------------------------------------------------------------
869 * Image Sensor Interface
870 * -------------------------------------------------------------------- */
871
872#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
873
874struct resource isi_resources[] = {
875 [0] = {
876 .start = AT91SAM9263_BASE_ISI,
877 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
878 .flags = IORESOURCE_MEM,
879 },
880 [1] = {
881 .start = AT91SAM9263_ID_ISI,
882 .end = AT91SAM9263_ID_ISI,
883 .flags = IORESOURCE_IRQ,
884 },
885};
886
887static struct platform_device at91sam9263_isi_device = {
888 .name = "at91_isi",
889 .id = -1,
890 .resource = isi_resources,
891 .num_resources = ARRAY_SIZE(isi_resources),
892};
893
894void __init at91_add_device_isi(void)
895{
896 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
897 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
898 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
899 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
900 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
901 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
902 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
903 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
904 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
905 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
906 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
907 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
908 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
909 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
910 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
911 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
912}
913#else
914void __init at91_add_device_isi(void) {}
915#endif
916
917
e5f40bfa
AV		 918/* --------------------------------------------------------------------
919 * Timer/Counter block
920 * -------------------------------------------------------------------- */
921
922#ifdef CONFIG_ATMEL_TCLIB
923
924static struct resource tcb_resources[] = {
925 [0] = {
926 .start = AT91SAM9263_BASE_TCB0,
927 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
928 .flags = IORESOURCE_MEM,
929 },
930 [1] = {
931 .start = AT91SAM9263_ID_TCB,
932 .end = AT91SAM9263_ID_TCB,
933 .flags = IORESOURCE_IRQ,
934 },
935};
936
937static struct platform_device at91sam9263_tcb_device = {
938 .name = "atmel_tcb",
939 .id = 0,
940 .resource = tcb_resources,
941 .num_resources = ARRAY_SIZE(tcb_resources),
942};
943
944static void __init at91_add_device_tc(void)
945{
e5f40bfa
AV		 946 platform_device_register(&at91sam9263_tcb_device);
947}
948#else
949static void __init at91_add_device_tc(void) { }
950#endif
951
952
884f5a6a
AV		 953/* --------------------------------------------------------------------
954 * RTT
955 * -------------------------------------------------------------------- */
956
957static struct resource rtt0_resources[] = {
958 {
eab5fd67
JCPV		 959 .start = AT91SAM9263_BASE_RTT0,
960 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
884f5a6a
AV		 961 .flags = IORESOURCE_MEM,
962 }
963};
964
965static struct platform_device at91sam9263_rtt0_device = {
966 .name = "at91_rtt",
967 .id = 0,
968 .resource = rtt0_resources,
969 .num_resources = ARRAY_SIZE(rtt0_resources),
970};
971
972static struct resource rtt1_resources[] = {
973 {
eab5fd67
JCPV		 974 .start = AT91SAM9263_BASE_RTT1,
975 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
884f5a6a
AV		 976 .flags = IORESOURCE_MEM,
977 }
978};
979
980static struct platform_device at91sam9263_rtt1_device = {
981 .name = "at91_rtt",
982 .id = 1,
983 .resource = rtt1_resources,
984 .num_resources = ARRAY_SIZE(rtt1_resources),
985};
986
987static void __init at91_add_device_rtt(void)
988{
989 platform_device_register(&at91sam9263_rtt0_device);
990 platform_device_register(&at91sam9263_rtt1_device);
991}
992
993
994/* --------------------------------------------------------------------
995 * Watchdog
996 * -------------------------------------------------------------------- */
997
2af29b78 998#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 999static struct resource wdt_resources[] = {
1000 {
1001 .start = AT91SAM9263_BASE_WDT,
1002 .end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
1003 .flags = IORESOURCE_MEM,
1004 }
1005};
1006
884f5a6a
AV		 1007static struct platform_device at91sam9263_wdt_device = {
1008 .name = "at91_wdt",
1009 .id = -1,
c1c30a29
JCPV		 1010 .resource = wdt_resources,
1011 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 1012};
1013
1014static void __init at91_add_device_watchdog(void)
1015{
1016 platform_device_register(&at91sam9263_wdt_device);
1017}
1018#else
1019static void __init at91_add_device_watchdog(void) {}
1020#endif
1021
1022
bb1ad68b
AV		 1023/* --------------------------------------------------------------------
1024 * PWM
1025 * --------------------------------------------------------------------*/
1026
1027#if defined(CONFIG_ATMEL_PWM)
1028static u32 pwm_mask;
1029
1030static struct resource pwm_resources[] = {
1031 [0] = {
1032 .start = AT91SAM9263_BASE_PWMC,
1033 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
1034 .flags = IORESOURCE_MEM,
1035 },
1036 [1] = {
1037 .start = AT91SAM9263_ID_PWMC,
1038 .end = AT91SAM9263_ID_PWMC,
1039 .flags = IORESOURCE_IRQ,
1040 },
1041};
1042
1043static struct platform_device at91sam9263_pwm0_device = {
1044 .name = "atmel_pwm",
1045 .id = -1,
1046 .dev = {
1047 .platform_data = &pwm_mask,
1048 },
1049 .resource = pwm_resources,
1050 .num_resources = ARRAY_SIZE(pwm_resources),
1051};
1052
1053void __init at91_add_device_pwm(u32 mask)
1054{
1055 if (mask & (1 << AT91_PWM0))
1056 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
1057
1058 if (mask & (1 << AT91_PWM1))
1059 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
1060
1061 if (mask & (1 << AT91_PWM2))
1062 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
1063
1064 if (mask & (1 << AT91_PWM3))
1065 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
1066
1067 pwm_mask = mask;
1068
1069 platform_device_register(&at91sam9263_pwm0_device);
1070}
1071#else
1072void __init at91_add_device_pwm(u32 mask) {}
1073#endif
1074
1075
bfbc3266
AV		 1076/* --------------------------------------------------------------------
1077 * SSC -- Synchronous Serial Controller
1078 * -------------------------------------------------------------------- */
1079
1080#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1081static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1082
1083static struct resource ssc0_resources[] = {
1084 [0] = {
1085 .start = AT91SAM9263_BASE_SSC0,
1086 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
1087 .flags = IORESOURCE_MEM,
1088 },
1089 [1] = {
1090 .start = AT91SAM9263_ID_SSC0,
1091 .end = AT91SAM9263_ID_SSC0,
1092 .flags = IORESOURCE_IRQ,
1093 },
1094};
1095
1096static struct platform_device at91sam9263_ssc0_device = {
1097 .name = "ssc",
1098 .id = 0,
1099 .dev = {
1100 .dma_mask = &ssc0_dmamask,
1101 .coherent_dma_mask = DMA_BIT_MASK(32),
1102 },
1103 .resource = ssc0_resources,
1104 .num_resources = ARRAY_SIZE(ssc0_resources),
1105};
1106
1107static inline void configure_ssc0_pins(unsigned pins)
1108{
1109 if (pins & ATMEL_SSC_TF)
1110 at91_set_B_periph(AT91_PIN_PB0, 1);
1111 if (pins & ATMEL_SSC_TK)
1112 at91_set_B_periph(AT91_PIN_PB1, 1);
1113 if (pins & ATMEL_SSC_TD)
1114 at91_set_B_periph(AT91_PIN_PB2, 1);
1115 if (pins & ATMEL_SSC_RD)
1116 at91_set_B_periph(AT91_PIN_PB3, 1);
1117 if (pins & ATMEL_SSC_RK)
1118 at91_set_B_periph(AT91_PIN_PB4, 1);
1119 if (pins & ATMEL_SSC_RF)
1120 at91_set_B_periph(AT91_PIN_PB5, 1);
1121}
1122
1123static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1124
1125static struct resource ssc1_resources[] = {
1126 [0] = {
1127 .start = AT91SAM9263_BASE_SSC1,
1128 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
1129 .flags = IORESOURCE_MEM,
1130 },
1131 [1] = {
1132 .start = AT91SAM9263_ID_SSC1,
1133 .end = AT91SAM9263_ID_SSC1,
1134 .flags = IORESOURCE_IRQ,
1135 },
1136};
1137
1138static struct platform_device at91sam9263_ssc1_device = {
1139 .name = "ssc",
1140 .id = 1,
1141 .dev = {
1142 .dma_mask = &ssc1_dmamask,
1143 .coherent_dma_mask = DMA_BIT_MASK(32),
1144 },
1145 .resource = ssc1_resources,
1146 .num_resources = ARRAY_SIZE(ssc1_resources),
1147};
1148
1149static inline void configure_ssc1_pins(unsigned pins)
1150{
1151 if (pins & ATMEL_SSC_TF)
1152 at91_set_A_periph(AT91_PIN_PB6, 1);
1153 if (pins & ATMEL_SSC_TK)
1154 at91_set_A_periph(AT91_PIN_PB7, 1);
1155 if (pins & ATMEL_SSC_TD)
1156 at91_set_A_periph(AT91_PIN_PB8, 1);
1157 if (pins & ATMEL_SSC_RD)
1158 at91_set_A_periph(AT91_PIN_PB9, 1);
1159 if (pins & ATMEL_SSC_RK)
1160 at91_set_A_periph(AT91_PIN_PB10, 1);
1161 if (pins & ATMEL_SSC_RF)
1162 at91_set_A_periph(AT91_PIN_PB11, 1);
1163}
1164
1165/*
bfbc3266
AV		 1166 * SSC controllers are accessed through library code, instead of any
1167 * kind of all-singing/all-dancing driver. For example one could be
1168 * used by a particular I2S audio codec's driver, while another one
1169 * on the same system might be used by a custom data capture driver.
1170 */
1171void __init at91_add_device_ssc(unsigned id, unsigned pins)
1172{
1173 struct platform_device *pdev;
1174
1175 /*
1176 * NOTE: caller is responsible for passing information matching
1177 * "pins" to whatever will be using each particular controller.
1178 */
1179 switch (id) {
1180 case AT91SAM9263_ID_SSC0:
1181 pdev = &at91sam9263_ssc0_device;
1182 configure_ssc0_pins(pins);
bfbc3266
AV		 1183 break;
1184 case AT91SAM9263_ID_SSC1:
1185 pdev = &at91sam9263_ssc1_device;
1186 configure_ssc1_pins(pins);
bfbc3266
AV		 1187 break;
1188 default:
1189 return;
1190 }
1191
1192 platform_device_register(pdev);
1193}
1194
1195#else
1196void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1197#endif
1198
1199
b2c65616
AV		 1200/* --------------------------------------------------------------------
1201 * UART
1202 * -------------------------------------------------------------------- */
1203
1204#if defined(CONFIG_SERIAL_ATMEL)
1205
1206static struct resource dbgu_resources[] = {
1207 [0] = {
13079a73
JCPV		 1208 .start = AT91SAM9263_BASE_DBGU,
1209 .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
b2c65616
AV		 1210 .flags = IORESOURCE_MEM,
1211 },
1212 [1] = {
1213 .start = AT91_ID_SYS,
1214 .end = AT91_ID_SYS,
1215 .flags = IORESOURCE_IRQ,
1216 },
1217};
1218
1219static struct atmel_uart_data dbgu_data = {
1220 .use_dma_tx = 0,
1221 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
b2c65616
AV		 1222};
1223
c6686ff9
AV		 1224static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1225
b2c65616
AV		 1226static struct platform_device at91sam9263_dbgu_device = {
1227 .name = "atmel_usart",
1228 .id = 0,
1229 .dev = {
c6686ff9
AV		 1230 .dma_mask = &dbgu_dmamask,
1231 .coherent_dma_mask = DMA_BIT_MASK(32),
1232 .platform_data = &dbgu_data,
b2c65616
AV		 1233 },
1234 .resource = dbgu_resources,
1235 .num_resources = ARRAY_SIZE(dbgu_resources),
1236};
1237
1238static inline void configure_dbgu_pins(void)
1239{
1240 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1241 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1242}
1243
1244static struct resource uart0_resources[] = {
1245 [0] = {
1246 .start = AT91SAM9263_BASE_US0,
1247 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1248 .flags = IORESOURCE_MEM,
1249 },
1250 [1] = {
1251 .start = AT91SAM9263_ID_US0,
1252 .end = AT91SAM9263_ID_US0,
1253 .flags = IORESOURCE_IRQ,
1254 },
1255};
1256
1257static struct atmel_uart_data uart0_data = {
1258 .use_dma_tx = 1,
1259 .use_dma_rx = 1,
1260};
1261
c6686ff9
AV		 1262static u64 uart0_dmamask = DMA_BIT_MASK(32);
1263
b2c65616
AV		 1264static struct platform_device at91sam9263_uart0_device = {
1265 .name = "atmel_usart",
1266 .id = 1,
1267 .dev = {
c6686ff9
AV		 1268 .dma_mask = &uart0_dmamask,
1269 .coherent_dma_mask = DMA_BIT_MASK(32),
1270 .platform_data = &uart0_data,
b2c65616
AV		 1271 },
1272 .resource = uart0_resources,
1273 .num_resources = ARRAY_SIZE(uart0_resources),
1274};
1275
c8f385a6 1276static inline void configure_usart0_pins(unsigned pins)
b2c65616
AV		 1277{
1278 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1279 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
c8f385a6
AV		 1280
1281 if (pins & ATMEL_UART_RTS)
1282 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1283 if (pins & ATMEL_UART_CTS)
1284 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
b2c65616
AV		 1285}
1286
1287static struct resource uart1_resources[] = {
1288 [0] = {
1289 .start = AT91SAM9263_BASE_US1,
1290 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1291 .flags = IORESOURCE_MEM,
1292 },
1293 [1] = {
1294 .start = AT91SAM9263_ID_US1,
1295 .end = AT91SAM9263_ID_US1,
1296 .flags = IORESOURCE_IRQ,
1297 },
1298};
1299
1300static struct atmel_uart_data uart1_data = {
1301 .use_dma_tx = 1,
1302 .use_dma_rx = 1,
1303};
1304
c6686ff9
AV		 1305static u64 uart1_dmamask = DMA_BIT_MASK(32);
1306
b2c65616
AV		 1307static struct platform_device at91sam9263_uart1_device = {
1308 .name = "atmel_usart",
1309 .id = 2,
1310 .dev = {
c6686ff9
AV		 1311 .dma_mask = &uart1_dmamask,
1312 .coherent_dma_mask = DMA_BIT_MASK(32),
1313 .platform_data = &uart1_data,
b2c65616
AV		 1314 },
1315 .resource = uart1_resources,
1316 .num_resources = ARRAY_SIZE(uart1_resources),
1317};
1318
c8f385a6 1319static inline void configure_usart1_pins(unsigned pins)
b2c65616
AV		 1320{
1321 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1322 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
c8f385a6
AV		 1323
1324 if (pins & ATMEL_UART_RTS)
1325 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1326 if (pins & ATMEL_UART_CTS)
1327 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
b2c65616
AV		 1328}
1329
1330static struct resource uart2_resources[] = {
1331 [0] = {
1332 .start = AT91SAM9263_BASE_US2,
1333 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1334 .flags = IORESOURCE_MEM,
1335 },
1336 [1] = {
1337 .start = AT91SAM9263_ID_US2,
1338 .end = AT91SAM9263_ID_US2,
1339 .flags = IORESOURCE_IRQ,
1340 },
1341};
1342
1343static struct atmel_uart_data uart2_data = {
1344 .use_dma_tx = 1,
1345 .use_dma_rx = 1,
1346};
1347
c6686ff9
AV		 1348static u64 uart2_dmamask = DMA_BIT_MASK(32);
1349
b2c65616
AV		 1350static struct platform_device at91sam9263_uart2_device = {
1351 .name = "atmel_usart",
1352 .id = 3,
1353 .dev = {
c6686ff9
AV		 1354 .dma_mask = &uart2_dmamask,
1355 .coherent_dma_mask = DMA_BIT_MASK(32),
1356 .platform_data = &uart2_data,
b2c65616
AV		 1357 },
1358 .resource = uart2_resources,
1359 .num_resources = ARRAY_SIZE(uart2_resources),
1360};
1361
c8f385a6 1362static inline void configure_usart2_pins(unsigned pins)
b2c65616
AV		 1363{
1364 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1365 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
c8f385a6
AV		 1366
1367 if (pins & ATMEL_UART_RTS)
1368 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1369 if (pins & ATMEL_UART_CTS)
1370 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
b2c65616
AV		 1371}
1372
11aadac4 1373static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
b2c65616
AV		 1374struct platform_device *atmel_default_console_device; /* the serial console device */
1375
c8f385a6
AV		 1376void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1377{
1378 struct platform_device *pdev;
2b348e2f 1379 struct atmel_uart_data *pdata;
c8f385a6
AV		 1380
1381 switch (id) {
1382 case 0: /* DBGU */
1383 pdev = &at91sam9263_dbgu_device;
1384 configure_dbgu_pins();
c8f385a6
AV		 1385 break;
1386 case AT91SAM9263_ID_US0:
1387 pdev = &at91sam9263_uart0_device;
1388 configure_usart0_pins(pins);
c8f385a6
AV		 1389 break;
1390 case AT91SAM9263_ID_US1:
1391 pdev = &at91sam9263_uart1_device;
1392 configure_usart1_pins(pins);
c8f385a6
AV		 1393 break;
1394 case AT91SAM9263_ID_US2:
1395 pdev = &at91sam9263_uart2_device;
1396 configure_usart2_pins(pins);
c8f385a6
AV		 1397 break;
1398 default:
1399 return;
1400 }
2b348e2f
JCPV		 1401 pdata = pdev->dev.platform_data;
1402 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1403
1404 if (portnr < ATMEL_MAX_UART)
1405 at91_uarts[portnr] = pdev;
1406}
1407
1408void __init at91_set_serial_console(unsigned portnr)
1409{
bd602995 1410 if (portnr < ATMEL_MAX_UART) {
c8f385a6 1411 atmel_default_console_device = at91_uarts[portnr];
5c1f9668 1412 at91sam9263_set_console_clock(at91_uarts[portnr]->id);
bd602995 1413 }
c8f385a6
AV		 1414}
1415
b2c65616
AV		 1416void __init at91_add_device_serial(void)
1417{
1418 int i;
1419
1420 for (i = 0; i < ATMEL_MAX_UART; i++) {
1421 if (at91_uarts[i])
1422 platform_device_register(at91_uarts[i]);
1423 }
11aadac4
AV		 1424
1425 if (!atmel_default_console_device)
1426 printk(KERN_INFO "AT91: No default serial console defined.\n");
b2c65616
AV		 1427}
1428#else
c8f385a6
AV		 1429void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1430void __init at91_set_serial_console(unsigned portnr) {}
b2c65616
AV		 1431void __init at91_add_device_serial(void) {}
1432#endif
1433
1434
1435/* -------------------------------------------------------------------- */
1436/*
1437 * These devices are always present and don't need any board-specific
1438 * setup.
1439 */
1440static int __init at91_add_standard_devices(void)
1441{
884f5a6a
AV		 1442 at91_add_device_rtt();
1443 at91_add_device_watchdog();
e5f40bfa 1444 at91_add_device_tc();
b2c65616
AV		 1445 return 0;
1446}
1447
1448arch_initcall(at91_add_standard_devices);
Linux 6.x block layer and io_uring tree(s)