[linux-2.6-block.git] / arch / arm / mach-at91 / at91sam9263.c

/*
 * arch/arm/mach-at91/at91sam9263.c
 *
 *  Copyright (C) 2007 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/clk/at91_pmc.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9263.h>
#include <mach/hardware.h>

#include "at91_aic.h"
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"
#include "pm.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
	.name		= "pioCDE_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOCDE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
	.name		= "can_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_CAN,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
	.name		= "tcb_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91SAM9263_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twodge_clk = {
	.name		= "2dge_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_2DGE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioCDE_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc0_clk,
	&mmc1_clk,
	&can_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ac97_clk,
	&tcb_clk,
	&pwm_clk,
	&macb_clk,
	&twodge_clk,
	&udc_clk,
	&isi_clk,
	&lcdc_clk,
	&dma_clk,
	&ohci_clk,
	// irq0 .. irq1
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for macb_hclk */
	CLKDEV_CON_ID("hclk", &macb_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
	CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioCDE_clk),
	CLKDEV_CON_ID("pioD", &pioCDE_clk),
	CLKDEV_CON_ID("pioE", &pioCDE_clk),
	/* more usart lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	/* more tc lookup table for DT entries */
	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

static void __init at91sam9263_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
	{
		.id		= AT91SAM9263_ID_PIOA,
		.regbase	= AT91SAM9263_BASE_PIOA,
	}, {
		.id		= AT91SAM9263_ID_PIOB,
		.regbase	= AT91SAM9263_BASE_PIOB,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.regbase	= AT91SAM9263_BASE_PIOC,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.regbase	= AT91SAM9263_BASE_PIOD,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.regbase	= AT91SAM9263_BASE_PIOE,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9263 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9263_map_io(void)
{
	at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
}

static void __init at91sam9263_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
	at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
	at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
	at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
	at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
	at91_pm_set_standby(at91sam9_sdram_standby);
}

static void __init at91sam9263_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;

	at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
	at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9263_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C, D and E */
	0,
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface 0 */
	0,	/* Multimedia Card Interface 1 */
	3,	/* CAN */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	5,	/* AC97 Controller */
	0,	/* Timer Counter 0, 1 and 2 */
	0,	/* Pulse Width Modulation Controller */
	3,	/* Ethernet */
	0,
	0,	/* 2D Graphic Engine */
	2,	/* USB Device Port */
	0,	/* Image Sensor Interface */
	3,	/* LDC Controller */
	0,	/* DMA Controller */
	0,
	2,	/* USB Host port */
	0,	/* Advanced Interrupt Controller (IRQ0) */
	0,	/* Advanced Interrupt Controller (IRQ1) */
};

AT91_SOC_START(at91sam9263)
	.map_io = at91sam9263_map_io,
	.default_irq_priority = at91sam9263_default_irq_priority,
	.extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
	.ioremap_registers = at91sam9263_ioremap_registers,
	.register_clocks = at91sam9263_register_clocks,
	.init = at91sam9263_initialize,
AT91_SOC_END
Commit	Line	Data
b2c65616 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9263.c
	3	*
	4	* Copyright (C) 2007 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
2edb90ae	14	#include <linux/clk/at91_pmc.h>
b2c65616	15
c9dfafba	16	#include <asm/proc-fns.h>
80b02c17	17	#include <asm/irq.h>
b2c65616 AV	18	#include <asm/mach/arch.h>
b2c65616 AV	19	#include <asm/mach/map.h>
9f97da78	20	#include <asm/system_misc.h>
a09e64fb	21	#include <mach/at91sam9263.h>
ac11a1d4	22	#include <mach/hardware.h>
b2c65616	23
a510b9ba	24	#include "at91_aic.h"
f0995d08	25	#include "at91_rstc.h"
21d08b9d	26	#include "soc.h"
b2c65616 AV	27	#include "generic.h"
b2c65616 AV	28	#include "clock.h"
faee0cc3	29	#include "sam9_smc.h"
5ad945ea	30	#include "pm.h"
b2c65616	31
b2c65616 AV	32	/* --------------------------------------------------------------------
	33	* Clocks
	34	* -------------------------------------------------------------------- */
	35
	36	/*
	37	* The peripheral clocks.
	38	*/
	39	static struct clk pioA_clk = {
	40	.name = "pioA_clk",
	41	.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
	42	.type = CLK_TYPE_PERIPHERAL,
	43	};
	44	static struct clk pioB_clk = {
	45	.name = "pioB_clk",
	46	.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
	47	.type = CLK_TYPE_PERIPHERAL,
	48	};
	49	static struct clk pioCDE_clk = {
	50	.name = "pioCDE_clk",
	51	.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
	52	.type = CLK_TYPE_PERIPHERAL,
	53	};
	54	static struct clk usart0_clk = {
	55	.name = "usart0_clk",
	56	.pmc_mask = 1 << AT91SAM9263_ID_US0,
	57	.type = CLK_TYPE_PERIPHERAL,
	58	};
	59	static struct clk usart1_clk = {
	60	.name = "usart1_clk",
	61	.pmc_mask = 1 << AT91SAM9263_ID_US1,
	62	.type = CLK_TYPE_PERIPHERAL,
	63	};
	64	static struct clk usart2_clk = {
	65	.name = "usart2_clk",
	66	.pmc_mask = 1 << AT91SAM9263_ID_US2,
	67	.type = CLK_TYPE_PERIPHERAL,
	68	};
	69	static struct clk mmc0_clk = {
	70	.name = "mci0_clk",
	71	.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
	72	.type = CLK_TYPE_PERIPHERAL,
	73	};
	74	static struct clk mmc1_clk = {
	75	.name = "mci1_clk",
	76	.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
	77	.type = CLK_TYPE_PERIPHERAL,
	78	};
e8788bab AV	79	static struct clk can_clk = {
	80	.name = "can_clk",
	81	.pmc_mask = 1 << AT91SAM9263_ID_CAN,
	82	.type = CLK_TYPE_PERIPHERAL,
	83	};
b2c65616 AV	84	static struct clk twi_clk = {
	85	.name = "twi_clk",
	86	.pmc_mask = 1 << AT91SAM9263_ID_TWI,
	87	.type = CLK_TYPE_PERIPHERAL,
	88	};
	89	static struct clk spi0_clk = {
	90	.name = "spi0_clk",
	91	.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
	92	.type = CLK_TYPE_PERIPHERAL,
	93	};
	94	static struct clk spi1_clk = {
	95	.name = "spi1_clk",
	96	.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
	97	.type = CLK_TYPE_PERIPHERAL,
	98	};
e8788bab AV	99	static struct clk ssc0_clk = {
	100	.name = "ssc0_clk",
	101	.pmc_mask = 1 << AT91SAM9263_ID_SSC0,
	102	.type = CLK_TYPE_PERIPHERAL,
	103	};
	104	static struct clk ssc1_clk = {
	105	.name = "ssc1_clk",
	106	.pmc_mask = 1 << AT91SAM9263_ID_SSC1,
	107	.type = CLK_TYPE_PERIPHERAL,
	108	};
	109	static struct clk ac97_clk = {
	110	.name = "ac97_clk",
	111	.pmc_mask = 1 << AT91SAM9263_ID_AC97C,
	112	.type = CLK_TYPE_PERIPHERAL,
	113	};
b2c65616 AV	114	static struct clk tcb_clk = {
	115	.name = "tcb_clk",
	116	.pmc_mask = 1 << AT91SAM9263_ID_TCB,
	117	.type = CLK_TYPE_PERIPHERAL,
	118	};
bb1ad68b AV	119	static struct clk pwm_clk = {
bb1ad68b AV	120	.name = "pwm_clk",
e8788bab AV	121	.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
	122	.type = CLK_TYPE_PERIPHERAL,
	123	};
69b2e99c	124	static struct clk macb_clk = {
865d605e	125	.name = "pclk",
b2c65616 AV	126	.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
	127	.type = CLK_TYPE_PERIPHERAL,
	128	};
e8788bab AV	129	static struct clk dma_clk = {
	130	.name = "dma_clk",
	131	.pmc_mask = 1 << AT91SAM9263_ID_DMA,
	132	.type = CLK_TYPE_PERIPHERAL,
	133	};
	134	static struct clk twodge_clk = {
	135	.name = "2dge_clk",
	136	.pmc_mask = 1 << AT91SAM9263_ID_2DGE,
	137	.type = CLK_TYPE_PERIPHERAL,
	138	};
b2c65616 AV	139	static struct clk udc_clk = {
	140	.name = "udc_clk",
	141	.pmc_mask = 1 << AT91SAM9263_ID_UDP,
	142	.type = CLK_TYPE_PERIPHERAL,
	143	};
	144	static struct clk isi_clk = {
	145	.name = "isi_clk",
	146	.pmc_mask = 1 << AT91SAM9263_ID_ISI,
	147	.type = CLK_TYPE_PERIPHERAL,
	148	};
	149	static struct clk lcdc_clk = {
	150	.name = "lcdc_clk",
7f6e2d99	151	.pmc_mask = 1 << AT91SAM9263_ID_LCDC,
b2c65616 AV	152	.type = CLK_TYPE_PERIPHERAL,
	153	};
	154	static struct clk ohci_clk = {
	155	.name = "ohci_clk",
	156	.pmc_mask = 1 << AT91SAM9263_ID_UHP,
	157	.type = CLK_TYPE_PERIPHERAL,
	158	};
	159
	160	static struct clk *periph_clocks[] __initdata = {
	161	&pioA_clk,
	162	&pioB_clk,
	163	&pioCDE_clk,
	164	&usart0_clk,
	165	&usart1_clk,
	166	&usart2_clk,
	167	&mmc0_clk,
	168	&mmc1_clk,
e8788bab	169	&can_clk,
b2c65616 AV	170	&twi_clk,
	171	&spi0_clk,
	172	&spi1_clk,
e8788bab AV	173	&ssc0_clk,
	174	&ssc1_clk,
	175	&ac97_clk,
b2c65616	176	&tcb_clk,
bb1ad68b	177	&pwm_clk,
69b2e99c	178	&macb_clk,
e8788bab	179	&twodge_clk,
b2c65616 AV	180	&udc_clk,
	181	&isi_clk,
	182	&lcdc_clk,
e8788bab	183	&dma_clk,
b2c65616 AV	184	&ohci_clk,
	185	// irq0 .. irq1
	186	};
	187
bd602995	188	static struct clk_lookup periph_clocks_lookups[] = {
865d605e JI	189	/* One additional fake clock for macb_hclk */
865d605e JI	190	CLKDEV_CON_ID("hclk", &macb_clk),
636036d2 BS	191	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
636036d2 BS	192	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
099343c6 BS	193	CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
099343c6 BS	194	CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
bbd44f6b	195	CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
4cf3326a LD	196	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
4cf3326a LD	197	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995 JCPV	198	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	199	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	200	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
302090a6	201	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
0af4316b JCPV	202	/* fake hclk clock */
0af4316b JCPV	203	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
619d4a4b JCPV	204	CLKDEV_CON_ID("pioA", &pioA_clk),
	205	CLKDEV_CON_ID("pioB", &pioB_clk),
	206	CLKDEV_CON_ID("pioC", &pioCDE_clk),
	207	CLKDEV_CON_ID("pioD", &pioCDE_clk),
	208	CLKDEV_CON_ID("pioE", &pioCDE_clk),
4abb3677 JCPV	209	/* more usart lookup table for DT entries */
	210	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	211	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	212	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	213	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	214	/* more tc lookup table for DT entries */
	215	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
	216	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
	217	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
	218	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
23e3b24f LD	219	CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
23e3b24f LD	220	CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
f7d19b90	221	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
5314ec8e JCPV	222	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
	223	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
	224	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
	225	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
	226	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
050208df	227	CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
bd602995 JCPV	228	};
	229
	230	static struct clk_lookup usart_clocks_lookups[] = {
	231	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	232	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	233	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	234	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	235	};
	236
b2c65616 AV	237	/*
	238	* The four programmable clocks.
	239	* You must configure pin multiplexing to bring these signals out.
	240	*/
	241	static struct clk pck0 = {
	242	.name = "pck0",
	243	.pmc_mask = AT91_PMC_PCK0,
	244	.type = CLK_TYPE_PROGRAMMABLE,
	245	.id = 0,
	246	};
	247	static struct clk pck1 = {
	248	.name = "pck1",
	249	.pmc_mask = AT91_PMC_PCK1,
	250	.type = CLK_TYPE_PROGRAMMABLE,
	251	.id = 1,
	252	};
	253	static struct clk pck2 = {
	254	.name = "pck2",
	255	.pmc_mask = AT91_PMC_PCK2,
	256	.type = CLK_TYPE_PROGRAMMABLE,
	257	.id = 2,
	258	};
	259	static struct clk pck3 = {
	260	.name = "pck3",
	261	.pmc_mask = AT91_PMC_PCK3,
	262	.type = CLK_TYPE_PROGRAMMABLE,
	263	.id = 3,
	264	};
	265
	266	static void __init at91sam9263_register_clocks(void)
	267	{
	268	int i;
	269
	270	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	271	clk_register(periph_clocks[i]);
	272
bd602995 JCPV	273	clkdev_add_table(periph_clocks_lookups,
	274	ARRAY_SIZE(periph_clocks_lookups));
	275	clkdev_add_table(usart_clocks_lookups,
	276	ARRAY_SIZE(usart_clocks_lookups));
	277
b2c65616 AV	278	clk_register(&pck0);
	279	clk_register(&pck1);
	280	clk_register(&pck2);
	281	clk_register(&pck3);
	282	}
	283
	284	/* --------------------------------------------------------------------
	285	* GPIO
	286	* -------------------------------------------------------------------- */
	287
1a2d9156	288	static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
b2c65616 AV	289	{
b2c65616 AV	290	.id = AT91SAM9263_ID_PIOA,
80e91cb8	291	.regbase = AT91SAM9263_BASE_PIOA,
b2c65616 AV	292	}, {
b2c65616 AV	293	.id = AT91SAM9263_ID_PIOB,
80e91cb8	294	.regbase = AT91SAM9263_BASE_PIOB,
b2c65616 AV	295	}, {
b2c65616 AV	296	.id = AT91SAM9263_ID_PIOCDE,
80e91cb8	297	.regbase = AT91SAM9263_BASE_PIOC,
b2c65616 AV	298	}, {
b2c65616 AV	299	.id = AT91SAM9263_ID_PIOCDE,
80e91cb8	300	.regbase = AT91SAM9263_BASE_PIOD,
b2c65616 AV	301	}, {
b2c65616 AV	302	.id = AT91SAM9263_ID_PIOCDE,
80e91cb8	303	.regbase = AT91SAM9263_BASE_PIOE,
b2c65616 AV	304	}
	305	};
	306
b2c65616 AV	307	/* --------------------------------------------------------------------
	308	* AT91SAM9263 processor initialization
	309	* -------------------------------------------------------------------- */
	310
21d08b9d	311	static void __init at91sam9263_map_io(void)
b2c65616	312	{
f0051d82 JCPV	313	at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
f0051d82 JCPV	314	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
1b021a3b	315	}
b2c65616	316
cfa5a1fe JCPV	317	static void __init at91sam9263_ioremap_registers(void)
cfa5a1fe JCPV	318	{
f22deee5	319	at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
e9f68b5c	320	at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
f363c407 JCPV	321	at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
f363c407 JCPV	322	at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
4ab0c599	323	at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
faee0cc3 JCPV	324	at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
faee0cc3 JCPV	325	at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
4342d647	326	at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
6b625891	327	at91_pm_set_standby(at91sam9_sdram_standby);
cfa5a1fe JCPV	328	}
cfa5a1fe JCPV	329
46539374	330	static void __init at91sam9263_initialize(void)
1b021a3b	331	{
0d781716	332	arm_pm_idle = at91sam9_idle;
1b2073e7	333	arm_pm_restart = at91sam9_alt_restart;
b2c65616	334
94c4c79f JH	335	at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
	336	at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
	337
b2c65616 AV	338	/* Register GPIO subsystem */
	339	at91_gpio_init(at91sam9263_gpio, 5);
	340	}
	341
	342	/* --------------------------------------------------------------------
	343	* Interrupt initialization
	344	* -------------------------------------------------------------------- */
	345
	346	/*
	347	* The default interrupt priority levels (0 = lowest, 7 = highest).
	348	*/
	349	static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	350	7, /* Advanced Interrupt Controller (FIQ) */
	351	7, /* System Peripherals */
7cbed2b5 AV	352	1, /* Parallel IO Controller A */
	353	1, /* Parallel IO Controller B */
	354	1, /* Parallel IO Controller C, D and E */
b2c65616 AV	355	0,
b2c65616 AV	356	0,
7cbed2b5 AV	357	5, /* USART 0 */
	358	5, /* USART 1 */
	359	5, /* USART 2 */
b2c65616 AV	360	0, /* Multimedia Card Interface 0 */
b2c65616 AV	361	0, /* Multimedia Card Interface 1 */
7cbed2b5 AV	362	3, /* CAN */
	363	6, /* Two-Wire Interface */
	364	5, /* Serial Peripheral Interface 0 */
	365	5, /* Serial Peripheral Interface 1 */
	366	4, /* Serial Synchronous Controller 0 */
	367	4, /* Serial Synchronous Controller 1 */
	368	5, /* AC97 Controller */
b2c65616 AV	369	0, /* Timer Counter 0, 1 and 2 */
	370	0, /* Pulse Width Modulation Controller */
	371	3, /* Ethernet */
	372	0,
	373	0, /* 2D Graphic Engine */
7cbed2b5	374	2, /* USB Device Port */
b2c65616 AV	375	0, /* Image Sensor Interface */
	376	3, /* LDC Controller */
	377	0, /* DMA Controller */
	378	0,
7cbed2b5	379	2, /* USB Host port */
b2c65616 AV	380	0, /* Advanced Interrupt Controller (IRQ0) */
	381	0, /* Advanced Interrupt Controller (IRQ1) */
	382	};
	383
84ddb087	384	AT91_SOC_START(at91sam9263)
21d08b9d	385	.map_io = at91sam9263_map_io,
92100c12	386	.default_irq_priority = at91sam9263_default_irq_priority,
546c830c	387	.extern_irq = (1 << AT91SAM9263_ID_IRQ0) \| (1 << AT91SAM9263_ID_IRQ1),
cfa5a1fe	388	.ioremap_registers = at91sam9263_ioremap_registers,
51ddec76	389	.register_clocks = at91sam9263_register_clocks,
21d08b9d	390	.init = at91sam9263_initialize,
8d39e0fd	391	AT91_SOC_END