[linux-2.6-block.git] / arch / arm / mach-at91 / at91rm9200_time.c

/*
 * linux/arch/arm/mach-at91/at91rm9200_time.c
 *
 *  Copyright (C) 2003 SAN People
 *  Copyright (C) 2003 ATMEL
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>

#include <asm/mach/time.h>

#include <mach/at91_st.h>

static unsigned long last_crtr;
static u32 irqmask;
static struct clock_event_device clkevt;

/*
 * The ST_CRTR is updated asynchronously to the master clock ... but
 * the updates as seen by the CPU don't seem to be strictly monotonic.
 * Waiting until we read the same value twice avoids glitching.
 */
static inline unsigned long read_CRTR(void)
{
	unsigned long x1, x2;

	x1 = at91_sys_read(AT91_ST_CRTR);
	do {
		x2 = at91_sys_read(AT91_ST_CRTR);
		if (x1 == x2)
			break;
		x1 = x2;
	} while (1);
	return x1;
}

/*
 * IRQ handler for the timer.
 */
static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
{
	u32	sr = at91_sys_read(AT91_ST_SR) & irqmask;

	/* simulate "oneshot" timer with alarm */
	if (sr & AT91_ST_ALMS) {
		clkevt.event_handler(&clkevt);
		return IRQ_HANDLED;
	}

	/* periodic mode should handle delayed ticks */
	if (sr & AT91_ST_PITS) {
		u32	crtr = read_CRTR();

		while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) {
			last_crtr += LATCH;
			clkevt.event_handler(&clkevt);
		}
		return IRQ_HANDLED;
	}

	/* this irq is shared ... */
	return IRQ_NONE;
}

static struct irqaction at91rm9200_timer_irq = {
	.name		= "at91_tick",
	.flags		= IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= at91rm9200_timer_interrupt
};

static cycle_t read_clk32k(struct clocksource *cs)
{
	return read_CRTR();
}

static struct clocksource clk32k = {
	.name		= "32k_counter",
	.rating		= 150,
	.read		= read_clk32k,
	.mask		= CLOCKSOURCE_MASK(20),
	.shift		= 10,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void
clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
	/* Disable and flush pending timer interrupts */
	at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
	(void) at91_sys_read(AT91_ST_SR);

	last_crtr = read_CRTR();
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* PIT for periodic irqs; fixed rate of 1/HZ */
		irqmask = AT91_ST_PITS;
		at91_sys_write(AT91_ST_PIMR, LATCH);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* ALM for oneshot irqs, set by next_event()
		 * before 32 seconds have passed
		 */
		irqmask = AT91_ST_ALMS;
		at91_sys_write(AT91_ST_RTAR, last_crtr);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		irqmask = 0;
		break;
	}
	at91_sys_write(AT91_ST_IER, irqmask);
}

static int
clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
{
	unsigned long	flags;
	u32		alm;
	int		status = 0;

	BUG_ON(delta < 2);

	/* Use "raw" primitives so we behave correctly on RT kernels. */
	raw_local_irq_save(flags);

	/*
	 * According to Thomas Gleixner irqs are already disabled here.  Simply
	 * removing raw_local_irq_save above (and the matching
	 * raw_local_irq_restore) was not accepted.  See
	 * http://thread.gmane.org/gmane.linux.ports.arm.kernel/41174
	 * So for now (2008-11-20) just warn once if irqs were not disabled ...
	 */
	WARN_ON_ONCE(!raw_irqs_disabled_flags(flags));

	/* The alarm IRQ uses absolute time (now+delta), not the relative
	 * time (delta) in our calling convention.  Like all clockevents
	 * using such "match" hardware, we have a race to defend against.
	 *
	 * Our defense here is to have set up the clockevent device so the
	 * delta is at least two.  That way we never end up writing RTAR
	 * with the value then held in CRTR ... which would mean the match
	 * wouldn't trigger until 32 seconds later, after CRTR wraps.
	 */
	alm = read_CRTR();

	/* Cancel any pending alarm; flush any pending IRQ */
	at91_sys_write(AT91_ST_RTAR, alm);
	(void) at91_sys_read(AT91_ST_SR);

	/* Schedule alarm by writing RTAR. */
	alm += delta;
	at91_sys_write(AT91_ST_RTAR, alm);

	raw_local_irq_restore(flags);
	return status;
}

static struct clock_event_device clkevt = {
	.name		= "at91_tick",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.rating		= 150,
	.set_next_event	= clkevt32k_next_event,
	.set_mode	= clkevt32k_mode,
};

/*
 * ST (system timer) module supports both clockevents and clocksource.
 */
void __init at91rm9200_timer_init(void)
{
	/* Disable all timer interrupts, and clear any pending ones */
	at91_sys_write(AT91_ST_IDR,
		AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
	(void) at91_sys_read(AT91_ST_SR);

	/* Make IRQs happen for the system timer */
	setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);

	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
	 * directly for the clocksource and all clockevents, after adjusting
	 * its prescaler from the 1 Hz default.
	 */
	at91_sys_write(AT91_ST_RTMR, 1);

	/* Setup timer clockevent, with minimum of two ticks (important!!) */
	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
	clkevt.cpumask = cpumask_of(0);
	clockevents_register_device(&clkevt);

	/* register clocksource */
	clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
	clocksource_register(&clk32k);
}

struct sys_timer at91rm9200_timer = {
	.init		= at91rm9200_timer_init,
};
Commit	Line	Data
73a59c1c	1	/*
9d041268	2	* linux/arch/arm/mach-at91/at91rm9200_time.c
73a59c1c SP	3	*
	4	* Copyright (C) 2003 SAN People
	5	* Copyright (C) 2003 ATMEL
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
5e802dfa	22	#include <linux/kernel.h>
73a59c1c	23	#include <linux/interrupt.h>
07d265dd	24	#include <linux/irq.h>
5e802dfa	25	#include <linux/clockchips.h>
73a59c1c	26
73a59c1c SP	27	#include <asm/mach/time.h>
73a59c1c SP	28
a09e64fb	29	#include <mach/at91_st.h>
55d8baee	30
963151f2	31	static unsigned long last_crtr;
5e802dfa DB	32	static u32 irqmask;
5e802dfa DB	33	static struct clock_event_device clkevt;
963151f2	34
73a59c1c	35	/*
5e802dfa DB	36	* The ST_CRTR is updated asynchronously to the master clock ... but
	37	* the updates as seen by the CPU don't seem to be strictly monotonic.
	38	* Waiting until we read the same value twice avoids glitching.
73a59c1c	39	*/
5e802dfa DB	40	static inline unsigned long read_CRTR(void)
5e802dfa DB	41	{
73a59c1c SP	42	unsigned long x1, x2;
73a59c1c SP	43
5e802dfa	44	x1 = at91_sys_read(AT91_ST_CRTR);
73a59c1c	45	do {
73a59c1c	46	x2 = at91_sys_read(AT91_ST_CRTR);
5e802dfa DB	47	if (x1 == x2)
	48	break;
	49	x1 = x2;
	50	} while (1);
73a59c1c SP	51	return x1;
	52	}
	53
73a59c1c SP	54	/*
	55	* IRQ handler for the timer.
	56	*/
0cd61b68	57	static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
73a59c1c	58	{
5e802dfa	59	u32 sr = at91_sys_read(AT91_ST_SR) & irqmask;
73a59c1c	60
5e802dfa DB	61	/* simulate "oneshot" timer with alarm */
	62	if (sr & AT91_ST_ALMS) {
	63	clkevt.event_handler(&clkevt);
	64	return IRQ_HANDLED;
	65	}
73a59c1c	66
5e802dfa DB	67	/* periodic mode should handle delayed ticks */
	68	if (sr & AT91_ST_PITS) {
	69	u32 crtr = read_CRTR();
73a59c1c	70
5e802dfa DB	71	while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) {
	72	last_crtr += LATCH;
	73	clkevt.event_handler(&clkevt);
	74	}
73a59c1c SP	75	return IRQ_HANDLED;
73a59c1c SP	76	}
5e802dfa DB	77
	78	/* this irq is shared ... */
	79	return IRQ_NONE;
73a59c1c SP	80	}
	81
	82	static struct irqaction at91rm9200_timer_irq = {
	83	.name = "at91_tick",
b30fabad	84	.flags = IRQF_SHARED \| IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
73a59c1c SP	85	.handler = at91rm9200_timer_interrupt
	86	};
	87
8e19608e	88	static cycle_t read_clk32k(struct clocksource *cs)
2a6f9902	89	{
5e802dfa DB	90	return read_CRTR();
5e802dfa DB	91	}
2a6f9902	92
5e802dfa DB	93	static struct clocksource clk32k = {
	94	.name = "32k_counter",
	95	.rating = 150,
	96	.read = read_clk32k,
	97	.mask = CLOCKSOURCE_MASK(20),
	98	.shift = 10,
	99	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	100	};
	101
	102	static void
	103	clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
	104	{
	105	/* Disable and flush pending timer interrupts */
	106	at91_sys_write(AT91_ST_IDR, AT91_ST_PITS \| AT91_ST_ALMS);
	107	(void) at91_sys_read(AT91_ST_SR);
2a6f9902	108
5e802dfa DB	109	last_crtr = read_CRTR();
	110	switch (mode) {
	111	case CLOCK_EVT_MODE_PERIODIC:
	112	/* PIT for periodic irqs; fixed rate of 1/HZ */
	113	irqmask = AT91_ST_PITS;
	114	at91_sys_write(AT91_ST_PIMR, LATCH);
	115	break;
	116	case CLOCK_EVT_MODE_ONESHOT:
	117	/* ALM for oneshot irqs, set by next_event()
	118	* before 32 seconds have passed
	119	*/
	120	irqmask = AT91_ST_ALMS;
	121	at91_sys_write(AT91_ST_RTAR, last_crtr);
	122	break;
	123	case CLOCK_EVT_MODE_SHUTDOWN:
	124	case CLOCK_EVT_MODE_UNUSED:
	125	case CLOCK_EVT_MODE_RESUME:
	126	irqmask = 0;
	127	break;
	128	}
	129	at91_sys_write(AT91_ST_IER, irqmask);
	130	}
2a6f9902	131
5e802dfa DB	132	static int
	133	clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
	134	{
	135	unsigned long flags;
	136	u32 alm;
	137	int status = 0;
	138
	139	BUG_ON(delta < 2);
	140
	141	/* Use "raw" primitives so we behave correctly on RT kernels. */
	142	raw_local_irq_save(flags);
	143
c4edfced UKK	144	/*
	145	* According to Thomas Gleixner irqs are already disabled here. Simply
	146	* removing raw_local_irq_save above (and the matching
	147	* raw_local_irq_restore) was not accepted. See
	148	* http://thread.gmane.org/gmane.linux.ports.arm.kernel/41174
	149	* So for now (2008-11-20) just warn once if irqs were not disabled ...
	150	*/
	151	WARN_ON_ONCE(!raw_irqs_disabled_flags(flags));
	152
5e802dfa DB	153	/* The alarm IRQ uses absolute time (now+delta), not the relative
	154	* time (delta) in our calling convention. Like all clockevents
	155	* using such "match" hardware, we have a race to defend against.
	156	*
	157	* Our defense here is to have set up the clockevent device so the
	158	* delta is at least two. That way we never end up writing RTAR
	159	* with the value then held in CRTR ... which would mean the match
	160	* wouldn't trigger until 32 seconds later, after CRTR wraps.
	161	*/
	162	alm = read_CRTR();
	163
	164	/* Cancel any pending alarm; flush any pending IRQ */
	165	at91_sys_write(AT91_ST_RTAR, alm);
d100f259 AV	166	(void) at91_sys_read(AT91_ST_SR);
d100f259 AV	167
5e802dfa DB	168	/* Schedule alarm by writing RTAR. */
	169	alm += delta;
	170	at91_sys_write(AT91_ST_RTAR, alm);
	171
	172	raw_local_irq_restore(flags);
	173	return status;
2a6f9902 AV	174	}
2a6f9902 AV	175
5e802dfa DB	176	static struct clock_event_device clkevt = {
	177	.name = "at91_tick",
	178	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	179	.shift = 32,
	180	.rating = 150,
5e802dfa DB	181	.set_next_event = clkevt32k_next_event,
	182	.set_mode = clkevt32k_mode,
	183	};
	184
73a59c1c	185	/*
5e802dfa	186	* ST (system timer) module supports both clockevents and clocksource.
73a59c1c SP	187	*/
	188	void __init at91rm9200_timer_init(void)
	189	{
5e802dfa DB	190	/* Disable all timer interrupts, and clear any pending ones */
	191	at91_sys_write(AT91_ST_IDR,
	192	AT91_ST_PITS \| AT91_ST_WDOVF \| AT91_ST_RTTINC \| AT91_ST_ALMS);
	193	(void) at91_sys_read(AT91_ST_SR);
73a59c1c	194
2a6f9902	195	/* Make IRQs happen for the system timer */
73a59c1c SP	196	setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
73a59c1c SP	197
5e802dfa DB	198	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
	199	* directly for the clocksource and all clockevents, after adjusting
	200	* its prescaler from the 1 Hz default.
	201	*/
	202	at91_sys_write(AT91_ST_RTMR, 1);
73a59c1c	203
5e802dfa DB	204	/* Setup timer clockevent, with minimum of two ticks (important!!) */
	205	clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
	206	clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
	207	clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
320ab2b0	208	clkevt.cpumask = cpumask_of(0);
5e802dfa	209	clockevents_register_device(&clkevt);
2a6f9902	210
5e802dfa DB	211	/* register clocksource */
	212	clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
	213	clocksource_register(&clk32k);
73a59c1c SP	214	}
	215
	216	struct sys_timer at91rm9200_timer = {
	217	.init = at91rm9200_timer_init,
73a59c1c	218	};
2a6f9902	219