Commit | Line | Data |
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73a59c1c | 1 | /* |
9d041268 | 2 | * arch/arm/mach-at91/at91rm9200.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2005 SAN People | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | */ | |
12 | ||
73a59c1c SP |
13 | #include <linux/module.h> |
14 | ||
80b02c17 | 15 | #include <asm/irq.h> |
73a59c1c SP |
16 | #include <asm/mach/arch.h> |
17 | #include <asm/mach/map.h> | |
a09e64fb RK |
18 | #include <mach/at91rm9200.h> |
19 | #include <mach/at91_pmc.h> | |
20 | #include <mach/at91_st.h> | |
e57556e3 | 21 | #include <mach/cpu.h> |
73a59c1c | 22 | |
21d08b9d | 23 | #include "soc.h" |
10e8e1fb | 24 | #include "generic.h" |
2eeaaa21 | 25 | #include "clock.h" |
faee0cc3 | 26 | #include "sam9_smc.h" |
73a59c1c SP |
27 | |
28 | static struct map_desc at91rm9200_io_desc[] __initdata = { | |
29 | { | |
73a59c1c | 30 | .virtual = AT91_VA_BASE_EMAC, |
72729910 | 31 | .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), |
73a59c1c SP |
32 | .length = SZ_16K, |
33 | .type = MT_DEVICE, | |
73a59c1c SP |
34 | }, |
35 | }; | |
36 | ||
2eeaaa21 AV |
37 | /* -------------------------------------------------------------------- |
38 | * Clocks | |
39 | * -------------------------------------------------------------------- */ | |
40 | ||
41 | /* | |
42 | * The peripheral clocks. | |
43 | */ | |
44 | static struct clk udc_clk = { | |
45 | .name = "udc_clk", | |
46 | .pmc_mask = 1 << AT91RM9200_ID_UDP, | |
47 | .type = CLK_TYPE_PERIPHERAL, | |
48 | }; | |
49 | static struct clk ohci_clk = { | |
50 | .name = "ohci_clk", | |
51 | .pmc_mask = 1 << AT91RM9200_ID_UHP, | |
52 | .type = CLK_TYPE_PERIPHERAL, | |
53 | }; | |
54 | static struct clk ether_clk = { | |
55 | .name = "ether_clk", | |
56 | .pmc_mask = 1 << AT91RM9200_ID_EMAC, | |
57 | .type = CLK_TYPE_PERIPHERAL, | |
58 | }; | |
59 | static struct clk mmc_clk = { | |
60 | .name = "mci_clk", | |
61 | .pmc_mask = 1 << AT91RM9200_ID_MCI, | |
62 | .type = CLK_TYPE_PERIPHERAL, | |
63 | }; | |
64 | static struct clk twi_clk = { | |
65 | .name = "twi_clk", | |
66 | .pmc_mask = 1 << AT91RM9200_ID_TWI, | |
67 | .type = CLK_TYPE_PERIPHERAL, | |
68 | }; | |
69 | static struct clk usart0_clk = { | |
70 | .name = "usart0_clk", | |
71 | .pmc_mask = 1 << AT91RM9200_ID_US0, | |
72 | .type = CLK_TYPE_PERIPHERAL, | |
73 | }; | |
74 | static struct clk usart1_clk = { | |
75 | .name = "usart1_clk", | |
76 | .pmc_mask = 1 << AT91RM9200_ID_US1, | |
77 | .type = CLK_TYPE_PERIPHERAL, | |
78 | }; | |
79 | static struct clk usart2_clk = { | |
80 | .name = "usart2_clk", | |
81 | .pmc_mask = 1 << AT91RM9200_ID_US2, | |
82 | .type = CLK_TYPE_PERIPHERAL, | |
83 | }; | |
84 | static struct clk usart3_clk = { | |
85 | .name = "usart3_clk", | |
86 | .pmc_mask = 1 << AT91RM9200_ID_US3, | |
87 | .type = CLK_TYPE_PERIPHERAL, | |
88 | }; | |
89 | static struct clk spi_clk = { | |
90 | .name = "spi_clk", | |
91 | .pmc_mask = 1 << AT91RM9200_ID_SPI, | |
92 | .type = CLK_TYPE_PERIPHERAL, | |
93 | }; | |
94 | static struct clk pioA_clk = { | |
95 | .name = "pioA_clk", | |
96 | .pmc_mask = 1 << AT91RM9200_ID_PIOA, | |
97 | .type = CLK_TYPE_PERIPHERAL, | |
98 | }; | |
99 | static struct clk pioB_clk = { | |
100 | .name = "pioB_clk", | |
101 | .pmc_mask = 1 << AT91RM9200_ID_PIOB, | |
102 | .type = CLK_TYPE_PERIPHERAL, | |
103 | }; | |
104 | static struct clk pioC_clk = { | |
105 | .name = "pioC_clk", | |
106 | .pmc_mask = 1 << AT91RM9200_ID_PIOC, | |
107 | .type = CLK_TYPE_PERIPHERAL, | |
108 | }; | |
109 | static struct clk pioD_clk = { | |
110 | .name = "pioD_clk", | |
111 | .pmc_mask = 1 << AT91RM9200_ID_PIOD, | |
112 | .type = CLK_TYPE_PERIPHERAL, | |
113 | }; | |
e8788bab AV |
114 | static struct clk ssc0_clk = { |
115 | .name = "ssc0_clk", | |
116 | .pmc_mask = 1 << AT91RM9200_ID_SSC0, | |
117 | .type = CLK_TYPE_PERIPHERAL, | |
118 | }; | |
119 | static struct clk ssc1_clk = { | |
120 | .name = "ssc1_clk", | |
121 | .pmc_mask = 1 << AT91RM9200_ID_SSC1, | |
122 | .type = CLK_TYPE_PERIPHERAL, | |
123 | }; | |
124 | static struct clk ssc2_clk = { | |
125 | .name = "ssc2_clk", | |
126 | .pmc_mask = 1 << AT91RM9200_ID_SSC2, | |
127 | .type = CLK_TYPE_PERIPHERAL, | |
128 | }; | |
c177a1e7 AV |
129 | static struct clk tc0_clk = { |
130 | .name = "tc0_clk", | |
131 | .pmc_mask = 1 << AT91RM9200_ID_TC0, | |
132 | .type = CLK_TYPE_PERIPHERAL, | |
133 | }; | |
134 | static struct clk tc1_clk = { | |
135 | .name = "tc1_clk", | |
136 | .pmc_mask = 1 << AT91RM9200_ID_TC1, | |
137 | .type = CLK_TYPE_PERIPHERAL, | |
138 | }; | |
139 | static struct clk tc2_clk = { | |
140 | .name = "tc2_clk", | |
141 | .pmc_mask = 1 << AT91RM9200_ID_TC2, | |
142 | .type = CLK_TYPE_PERIPHERAL, | |
143 | }; | |
144 | static struct clk tc3_clk = { | |
145 | .name = "tc3_clk", | |
146 | .pmc_mask = 1 << AT91RM9200_ID_TC3, | |
147 | .type = CLK_TYPE_PERIPHERAL, | |
148 | }; | |
149 | static struct clk tc4_clk = { | |
150 | .name = "tc4_clk", | |
151 | .pmc_mask = 1 << AT91RM9200_ID_TC4, | |
152 | .type = CLK_TYPE_PERIPHERAL, | |
153 | }; | |
154 | static struct clk tc5_clk = { | |
155 | .name = "tc5_clk", | |
156 | .pmc_mask = 1 << AT91RM9200_ID_TC5, | |
157 | .type = CLK_TYPE_PERIPHERAL, | |
158 | }; | |
2eeaaa21 AV |
159 | |
160 | static struct clk *periph_clocks[] __initdata = { | |
161 | &pioA_clk, | |
162 | &pioB_clk, | |
163 | &pioC_clk, | |
164 | &pioD_clk, | |
165 | &usart0_clk, | |
166 | &usart1_clk, | |
167 | &usart2_clk, | |
168 | &usart3_clk, | |
169 | &mmc_clk, | |
170 | &udc_clk, | |
171 | &twi_clk, | |
172 | &spi_clk, | |
e8788bab AV |
173 | &ssc0_clk, |
174 | &ssc1_clk, | |
175 | &ssc2_clk, | |
c177a1e7 AV |
176 | &tc0_clk, |
177 | &tc1_clk, | |
178 | &tc2_clk, | |
179 | &tc3_clk, | |
180 | &tc4_clk, | |
181 | &tc5_clk, | |
2eeaaa21 AV |
182 | &ohci_clk, |
183 | ðer_clk, | |
184 | // irq0 .. irq6 | |
185 | }; | |
186 | ||
bd602995 JCPV |
187 | static struct clk_lookup periph_clocks_lookups[] = { |
188 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), | |
189 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), | |
190 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), | |
191 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), | |
192 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), | |
193 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), | |
c5efefac JE |
194 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
195 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), | |
196 | CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), | |
0af4316b JCPV |
197 | /* fake hclk clock */ |
198 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), | |
619d4a4b JCPV |
199 | CLKDEV_CON_ID("pioA", &pioA_clk), |
200 | CLKDEV_CON_ID("pioB", &pioB_clk), | |
201 | CLKDEV_CON_ID("pioC", &pioC_clk), | |
202 | CLKDEV_CON_ID("pioD", &pioD_clk), | |
bd602995 JCPV |
203 | }; |
204 | ||
205 | static struct clk_lookup usart_clocks_lookups[] = { | |
206 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), | |
207 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), | |
208 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), | |
209 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), | |
210 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), | |
211 | }; | |
212 | ||
2eeaaa21 AV |
213 | /* |
214 | * The four programmable clocks. | |
215 | * You must configure pin multiplexing to bring these signals out. | |
216 | */ | |
217 | static struct clk pck0 = { | |
218 | .name = "pck0", | |
219 | .pmc_mask = AT91_PMC_PCK0, | |
220 | .type = CLK_TYPE_PROGRAMMABLE, | |
221 | .id = 0, | |
222 | }; | |
223 | static struct clk pck1 = { | |
224 | .name = "pck1", | |
225 | .pmc_mask = AT91_PMC_PCK1, | |
226 | .type = CLK_TYPE_PROGRAMMABLE, | |
227 | .id = 1, | |
228 | }; | |
229 | static struct clk pck2 = { | |
230 | .name = "pck2", | |
231 | .pmc_mask = AT91_PMC_PCK2, | |
232 | .type = CLK_TYPE_PROGRAMMABLE, | |
233 | .id = 2, | |
234 | }; | |
235 | static struct clk pck3 = { | |
236 | .name = "pck3", | |
237 | .pmc_mask = AT91_PMC_PCK3, | |
238 | .type = CLK_TYPE_PROGRAMMABLE, | |
239 | .id = 3, | |
240 | }; | |
241 | ||
242 | static void __init at91rm9200_register_clocks(void) | |
73a59c1c | 243 | { |
2eeaaa21 AV |
244 | int i; |
245 | ||
246 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | |
247 | clk_register(periph_clocks[i]); | |
248 | ||
bd602995 JCPV |
249 | clkdev_add_table(periph_clocks_lookups, |
250 | ARRAY_SIZE(periph_clocks_lookups)); | |
251 | clkdev_add_table(usart_clocks_lookups, | |
252 | ARRAY_SIZE(usart_clocks_lookups)); | |
253 | ||
2eeaaa21 AV |
254 | clk_register(&pck0); |
255 | clk_register(&pck1); | |
256 | clk_register(&pck2); | |
257 | clk_register(&pck3); | |
258 | } | |
259 | ||
bd602995 JCPV |
260 | static struct clk_lookup console_clock_lookup; |
261 | ||
262 | void __init at91rm9200_set_console_clock(int id) | |
263 | { | |
264 | if (id >= ARRAY_SIZE(usart_clocks_lookups)) | |
265 | return; | |
266 | ||
267 | console_clock_lookup.con_id = "usart"; | |
268 | console_clock_lookup.clk = usart_clocks_lookups[id].clk; | |
269 | clkdev_add(&console_clock_lookup); | |
270 | } | |
271 | ||
f2173834 AV |
272 | /* -------------------------------------------------------------------- |
273 | * GPIO | |
274 | * -------------------------------------------------------------------- */ | |
275 | ||
1a2d9156 | 276 | static struct at91_gpio_bank at91rm9200_gpio[] __initdata = { |
f2173834 AV |
277 | { |
278 | .id = AT91RM9200_ID_PIOA, | |
80e91cb8 | 279 | .regbase = AT91RM9200_BASE_PIOA, |
f2173834 AV |
280 | }, { |
281 | .id = AT91RM9200_ID_PIOB, | |
80e91cb8 | 282 | .regbase = AT91RM9200_BASE_PIOB, |
f2173834 AV |
283 | }, { |
284 | .id = AT91RM9200_ID_PIOC, | |
80e91cb8 | 285 | .regbase = AT91RM9200_BASE_PIOC, |
f2173834 AV |
286 | }, { |
287 | .id = AT91RM9200_ID_PIOD, | |
80e91cb8 | 288 | .regbase = AT91RM9200_BASE_PIOD, |
f2173834 AV |
289 | } |
290 | }; | |
2eeaaa21 | 291 | |
1b2073e7 | 292 | static void at91rm9200_restart(char mode, const char *cmd) |
1f4fd0a0 AV |
293 | { |
294 | /* | |
295 | * Perform a hardware reset with the use of the Watchdog timer. | |
296 | */ | |
297 | at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); | |
298 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); | |
299 | } | |
300 | ||
2eeaaa21 AV |
301 | /* -------------------------------------------------------------------- |
302 | * AT91RM9200 processor initialization | |
303 | * -------------------------------------------------------------------- */ | |
21d08b9d | 304 | static void __init at91rm9200_map_io(void) |
2eeaaa21 AV |
305 | { |
306 | /* Map peripherals */ | |
f0051d82 | 307 | at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); |
73a59c1c | 308 | iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); |
1b021a3b | 309 | } |
2eeaaa21 | 310 | |
cfa5a1fe JCPV |
311 | static void __init at91rm9200_ioremap_registers(void) |
312 | { | |
313 | } | |
314 | ||
46539374 | 315 | static void __init at91rm9200_initialize(void) |
1b021a3b | 316 | { |
1b2073e7 | 317 | arm_pm_restart = at91rm9200_restart; |
1f4fd0a0 AV |
318 | at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) |
319 | | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) | |
320 | | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) | |
321 | | (1 << AT91RM9200_ID_IRQ6); | |
322 | ||
f2173834 | 323 | /* Initialize GPIO subsystem */ |
e57556e3 JCPV |
324 | at91_gpio_init(at91rm9200_gpio, |
325 | cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP); | |
73a59c1c SP |
326 | } |
327 | ||
f2173834 AV |
328 | |
329 | /* -------------------------------------------------------------------- | |
330 | * Interrupt initialization | |
331 | * -------------------------------------------------------------------- */ | |
332 | ||
ba854e18 AV |
333 | /* |
334 | * The default interrupt priority levels (0 = lowest, 7 = highest). | |
335 | */ | |
336 | static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { | |
337 | 7, /* Advanced Interrupt Controller (FIQ) */ | |
338 | 7, /* System Peripherals */ | |
7cbed2b5 AV |
339 | 1, /* Parallel IO Controller A */ |
340 | 1, /* Parallel IO Controller B */ | |
341 | 1, /* Parallel IO Controller C */ | |
342 | 1, /* Parallel IO Controller D */ | |
343 | 5, /* USART 0 */ | |
344 | 5, /* USART 1 */ | |
345 | 5, /* USART 2 */ | |
346 | 5, /* USART 3 */ | |
ba854e18 | 347 | 0, /* Multimedia Card Interface */ |
7cbed2b5 AV |
348 | 2, /* USB Device Port */ |
349 | 6, /* Two-Wire Interface */ | |
350 | 5, /* Serial Peripheral Interface */ | |
351 | 4, /* Serial Synchronous Controller 0 */ | |
352 | 4, /* Serial Synchronous Controller 1 */ | |
353 | 4, /* Serial Synchronous Controller 2 */ | |
ba854e18 AV |
354 | 0, /* Timer Counter 0 */ |
355 | 0, /* Timer Counter 1 */ | |
356 | 0, /* Timer Counter 2 */ | |
357 | 0, /* Timer Counter 3 */ | |
358 | 0, /* Timer Counter 4 */ | |
359 | 0, /* Timer Counter 5 */ | |
7cbed2b5 | 360 | 2, /* USB Host port */ |
ba854e18 AV |
361 | 3, /* Ethernet MAC */ |
362 | 0, /* Advanced Interrupt Controller (IRQ0) */ | |
363 | 0, /* Advanced Interrupt Controller (IRQ1) */ | |
364 | 0, /* Advanced Interrupt Controller (IRQ2) */ | |
365 | 0, /* Advanced Interrupt Controller (IRQ3) */ | |
366 | 0, /* Advanced Interrupt Controller (IRQ4) */ | |
367 | 0, /* Advanced Interrupt Controller (IRQ5) */ | |
368 | 0 /* Advanced Interrupt Controller (IRQ6) */ | |
369 | }; | |
370 | ||
8c3583b6 | 371 | struct at91_init_soc __initdata at91rm9200_soc = { |
21d08b9d | 372 | .map_io = at91rm9200_map_io, |
92100c12 | 373 | .default_irq_priority = at91rm9200_default_irq_priority, |
cfa5a1fe | 374 | .ioremap_registers = at91rm9200_ioremap_registers, |
51ddec76 | 375 | .register_clocks = at91rm9200_register_clocks, |
21d08b9d JCPV |
376 | .init = at91rm9200_initialize, |
377 | }; |